CN205883049U - Use digit synchronization logic control circuit's DCDC converter - Google Patents
Use digit synchronization logic control circuit's DCDC converter Download PDFInfo
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- CN205883049U CN205883049U CN201620796547.1U CN201620796547U CN205883049U CN 205883049 U CN205883049 U CN 205883049U CN 201620796547 U CN201620796547 U CN 201620796547U CN 205883049 U CN205883049 U CN 205883049U
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- door
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- trigger
- clock
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Abstract
The utility model relates to an use digit synchronization logic control circuit's DCDC converter, its characterized in that receives outside first clock signal, including oscillator module and the receipt that is used for producing the 2nd clock signal first clock signal and the 2nd clock signal's synchronization and clock control module, when when first clock signal exists, synchronous and clock control module exports first clock signal works as when first clock signal does not exist, synchronous and clock control module exports the 2nd clock signal, still including receiving the clock buffer module of first clock signal or the 2nd clock signal and output. The utility model discloses a DCDC converter structure need not external outside synchronous circuit also can realize the synchronous logic function of multiunit DCDC converter, has improved the integrated level of chip and the convenience of use.
Description
[technical field]
This utility model relates to electronic circuit, particularly relates to use the dcdc converter of digital synchronous logic control circuit.
[background technology]
Power supply is function most basic in Circuits System.The main linear manostat of power management chip now and DCDC
Changer.And owing to needing the electric energy of efficient conversion battery in portable equipment, dcdc converter just has than linear voltage regulator
Bigger advantage.Owing to being provided that safer and bigger load capacity, many group dcdc converter synchronism output are used to power into
Important development direction for power management chip.Existing dcdc converter circuit framework in synchronizing function is the most more complicated,
Needing the synchronous circuit by external outside, it is achieved form is complex, this results in and cannot realize higher integrated level
Less chip area.
[utility model content]
For solving foregoing problems, the utility model proposes a kind of integrated level higher use digital synchronous logic control circuit
Dcdc converter.
For reaching object defined above, this utility model adopts the following technical scheme that and uses digital synchronous logic control circuit
Dcdc converter, it is characterised in that the first clock signal outside Jie Shouing；Including the agitator for producing second clock signal
Module and receive described first clock signal and the synchronization of second clock signal and clock control module；
In the presence of described first clock signal, described synchronization exports described first clock signal with clock control module,
When described first clock signal not in the presence of, described synchronization and clock control module export described second clock signal；
Also include receiving described first clock signal or second clock signal the clock buffer module exported.
First preferred version of the present utility model is: described synchronization and clock control module include first with door, second with
Door, the 3rd and door, the 4th and door, the first delayed-trigger, the second delayed-trigger, the 3rd delayed-trigger, the 4th delay are touched
Sending out device, reverser or door, selection switch, described selection switchs described first clock signal of reception and second clock signal,
Described first receives described first clock signal with the first input end of door, described first with the second input of door
Receiving reset signal, described second and the first input end reception reset signal of door, described second inputs termination with the second of door
Receive described second clock signal；Described first is connected answering of the first delayed-trigger and the second delayed-trigger with the outfan of door
Position pin, described first is connected described 3rd delayed-trigger and the 4th with the outfan of door by described reverser postpones to trigger
The reset pin of device；The described second clock input being connected the first delayed-trigger and the 3rd delayed-trigger with the outfan of door
Pin；
Described first delayed-trigger D end and the non-end of Q connect the clock input pin of described second delayed-trigger, described
The Q end of the first delayed-trigger connects the first input end of the 3rd and door；It is non-that the D end of described second delayed-trigger connects its Q
End, the Q end of described second delayed-trigger connects second input of the 3rd and door；
Described 3rd delayed-trigger D end and the non-end of Q connect the clock input pin of described 4th delayed-trigger, described
The Q end of the 3rd delayed-trigger connects the first input end of the 4th and door；It is non-that the D end of described 4th delayed-trigger connects its Q
End, the Q end of described 4th delayed-trigger connects second input of the 4th and door；
Described 3rd is connected the described or first input end of door with the outfan of door, and the described 4th is connected with the outfan of door
Described or the second input of door, described or door selects switch to be connected with described, when described or time door is output as high level, described
Switch is selected to export described first clock signal, when described or time door is output as low level, described selection switch output described the
Two clock signals.
Second preferred version of the present utility model is: described oscillator module is by except 2 synchronization with described with reseting module
It is connected with clock control module.
3rd preferred version of the present utility model is: also include at least one power tube, and the drain electrode of described power tube connects
Voltage output pin, source ground, grid connect the outfan of described clock buffer module.
4th preferred version of the present utility model is: also include and clock control module and oscillator module synchronization with described
The overheat protector module connected.
This utility model possesses following technique effect: this dcdc converter structure need not external external synchronizing circuit also can be real
Now the synchronous logic functions organizing dcdc converter, improve the integrated level of chip and the convenience of use more.
These features of the present utility model and advantage will be detailed in following detailed description of the invention, accompanying drawing exposure.
[accompanying drawing explanation]
Below in conjunction with the accompanying drawings this utility model is described further:
Fig. 1 is the theory diagram of the dcdc converter of this utility model embodiment 1.
Fig. 2 is master chip and the connection diagram from chip of this utility model embodiment 1.
Fig. 3 is the synchronization partial circuit diagram with clock control module of this utility model embodiment 1.
[detailed description of the invention]
Below in conjunction with the accompanying drawing of this utility model embodiment the technical scheme of this utility model embodiment explained and
Illustrate, but following embodiment is only preferred embodiment of the present utility model, and not all.Based on the embodiment in embodiment,
Those skilled in the art are obtained other embodiments on the premise of not making creative work, broadly fall into of the present utility model
Protection domain.
Embodiment 1.
Referring to Fig. 1 and Fig. 3, a kind of dcdc converter using digital synchronous logic control circuit, hereinafter referred to as DCDC becomes
Parallel operation, receives the first clock signal Fin of outside master chip；Including the oscillator module for producing second clock signal Fosc
And receive the first clock signal Fin and the synchronization of second clock signal Fosc and clock control module, second clock signal Fosc
Frequency when the outfan of oscillator module is 800kHz, oscillator module by except 2 with reseting module and synchronization and clock
Control module connect, except 2 with reseting module the second clock signal that second clock signal frequency split is 400kHz of 800kHz, and
It is sent to synchronize and clock control module.
In the presence of the first clock signal Fin, synchronize to export the first clock signal Fin, when first with clock control module
Clock signal Fin not in the presence of, synchronize with clock control module export second clock signal Fosc；Aforementioned dcdc converter also wraps
Include and receive the first clock signal Fin or second clock signal Fosc the clock buffer module exported.
Synchronize to include first and door AND1, second and door AND2, the 3rd and door AND3, the 4th and door with clock control module
AND4, the first delayed-trigger DFF1, the second delayed-trigger DFF2, the 3rd delayed-trigger DFF3, the 4th delayed-trigger
DFF4, reverser INV or door OR, selection switch, select switch to receive the first clock signal Fin and second clock signal Fosc.
The first input end of first and door AND1 receives the first clock signal Fin, second input of first and door AND2
Receiving reset signal Rt, the first input end of second and door AND2 receives reset signal Rt, and second inputs with the second of door AND2
End receives second clock signal Fosc；First is connected the first delayed-trigger DFF1 and second with the outfan of door AND1 postpones to touch
Sending out the reset pin Reset of device DFF2, first is connected the 3rd delayed-trigger with the outfan of door AND1 by reverser INV
DFF3 and the reset pin Reset of the 4th delayed-trigger DFF4；Second is connected the first delay with the outfan of door AND2 triggers
Device DFF1 and the clock input pin CLK of the 3rd delayed-trigger DFF3.
The D end of the first delayed-trigger DFF1 and the non-end of Q connect the clock input pin of the second delayed-trigger DFF2
The Q end of CLK, the first delayed-trigger DFF1 connects the first input end of the 3rd and door AND3；The D of the second delayed-trigger DFF2
End connects the non-end of its Q, and the Q end of the second delayed-trigger DFF2 connects second input of the 3rd and door AND3.
The D end of the 3rd delayed-trigger DFF3 and the non-end of Q connect the clock input pin of the 4th delayed-trigger DFF4
The Q end of CLK, the 3rd delayed-trigger DFF3 connects the first input end of the 4th and door AND4；The D of the 4th delayed-trigger DFF4
End connects the non-end of its Q, and the Q end of the 4th delayed-trigger DFF4 connects second input of the 4th and door AND4.
3rd is connected or the first input end of door OR with the outfan of door AND3, the 4th be connected with the outfan of door AND4 or
Door OR the second input, or door OR with select switch is connected, when or door OR output CHO be high level time, select switch export
First clock signal Fin, when described or door OR output CHO is low level, described selection switch exports described second clock letter
Number Fosc.
Aforementioned dcdc converter also includes that the drain electrode of two power tube LDMOS, described power tube LDMOS connects voltage output
Pin (Vd1, Vd2), source ground, grid connect the outfan of described clock buffer module.
Aforementioned dcdc converter also includes protecting with the described synchronization excess temperature being connected with clock control module and oscillator module
Protect module.When chip self-temperature is too high, turn off described oscillator module and synchronization and clock control module.
Aforementioned dcdc converter also includes with Tong Bu with clock control module and except 2 bi-directional logic being connected with reseting module
Module, described bi-directional logic module is connected with the clock input/output signal end CkIn/Out of dcdc converter, for the most defeated
Go out second clock signal Fosc that oscillator module produces or receive the first outside clock signal Fin and pass to synchronization and time
Clock control module.
The sync pin of aforementioned dcdc converter connects synchronization and clock control module and bi-directional logic module, when sync is
During low level, bi-directional logic module to clock input/output signal end CkIn/Out export second clock signal Fosc, synchronize with
Clock control module output second clock signal Fosc, now this dcdc converter is master chip；When sync is high level, double
Export the first clock signal Fin to logic module to synchronization and clock control module, synchronize outwards to export with clock control module
First clock signal Fin, now this dcdc converter is from chip.
Referring to Fig. 2.Master chip is can be common dcdc converter, it is also possible to for using digital synchronous logic control electricity
The dcdc converter on road.It it is the dcdc converter using digital synchronous logic control circuit from chip.
When needing to synchronize, high level (5V) will be connect from the synchronous digital signal Sync of chip, the first clock letter of master chip
Number enter into the clock input/output signal end CkIn/Out from chip from clock input/output signal end CkIn/Out, by with
Step and clock control module control from chip, make from the clock of chip controls output pipe LDMOS and main master chip
Control output pipe LDMOS clock synchronize.
Aforesaid plurality of delayed-trigger is all D type flip-flop.
The above, detailed description of the invention the most of the present utility model, but protection domain of the present utility model does not limit to
In this, it is familiar with this those skilled in the art and should be understood that this utility model includes but not limited to accompanying drawing and specific embodiment party above
Content described in formula.Any amendment without departing from function of the present utility model and structural principle is intended to be included in claims
Scope in.
Claims (5)
1. use the dcdc converter of digital synchronous logic control circuit, it is characterised in that the first clock signal outside Jie Shouing；
Including for producing the oscillator module of second clock signal and receiving the same of described first clock signal and second clock signal
Step and clock control module；
In the presence of described first clock signal, described synchronization exports described first clock signal with clock control module, works as institute
State the first clock signal not in the presence of, described synchronization and clock control module export described second clock signal；
Also include receiving described first clock signal or second clock signal the clock buffer module exported.
Use the dcdc converter of digital synchronous logic control circuit the most according to claim 1, it is characterised in that: described same
Step and clock control module include first with door, second with door, the 3rd with door, the 4th with door, the first delayed-trigger, second prolong
Trigger, the 3rd delayed-trigger, the 4th delayed-trigger, reverser or door, selection switch late, described selection switchs reception
Described first clock signal and second clock signal,
Described first receives described first clock signal with the first input end of door, and described first receives with the second input of door
Reset signal, described second receives reset signal with the first input end of door, and described second receives institute with the second input of door
State second clock signal；Described first reset being connected the first delayed-trigger and the second delayed-trigger with the outfan of door is drawn
Foot, described first is connected described 3rd delayed-trigger and the 4th delayed-trigger with the outfan of door by described reverser
Reset pin；The described second clock input being connected the first delayed-trigger and the 3rd delayed-trigger with the outfan of door is drawn
Foot；
Described first delayed-trigger D end and the clock input pin of Q non-end described second delayed-trigger of connection, described first
The Q end of delayed-trigger connects the first input end of the 3rd and door；The D end of described second delayed-trigger connects the non-end of its Q, institute
The Q end stating the second delayed-trigger connects second input of the 3rd and door；
Described 3rd delayed-trigger D end and the clock input pin of Q non-end described 4th delayed-trigger of connection, the described 3rd
The Q end of delayed-trigger connects the first input end of the 4th and door；The D end of described 4th delayed-trigger connects the non-end of its Q, institute
The Q end stating the 4th delayed-trigger connects second input of the 4th and door；
Described 3rd is connected the described or first input end of door with the outfan of door, the described 4th be connected with the outfan of door described in
Or the second input of door, described or door selects switch to be connected with described, when described or time door is output as high level, and described selection
Switch exports described first clock signal, when described or time door is output as low level, during described selection switch output described second
Clock signal.
Use the dcdc converter of digital synchronous logic control circuit the most according to claim 1, it is characterised in that shake described in:
Swing device module by synchronization being connected with clock control module with described with reseting module except 2.
Use the dcdc converter of digital synchronous logic control circuit the most according to claim 1, it is characterised in that: also include
At least one power tube, the drain electrode connection voltage output pin of described power tube, source ground, grid connect described clock buffer mould
The outfan of block.
Use the dcdc converter of digital synchronous logic control circuit the most according to claim 1, it is characterised in that: also include
With the described synchronization overheat protector module being connected with clock control module and oscillator module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620796547.1U CN205883049U (en) | 2016-07-27 | 2016-07-27 | Use digit synchronization logic control circuit's DCDC converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620796547.1U CN205883049U (en) | 2016-07-27 | 2016-07-27 | Use digit synchronization logic control circuit's DCDC converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205883049U true CN205883049U (en) | 2017-01-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620796547.1U Active CN205883049U (en) | 2016-07-27 | 2016-07-27 | Use digit synchronization logic control circuit's DCDC converter |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106100329B (en) * | 2016-07-27 | 2019-04-09 | 嘉兴市纳杰微电子技术有限公司 | Use the dcdc converter of digital synchronous logic control circuit |
| CN111510133A (en) * | 2020-04-09 | 2020-08-07 | 上海艾为电子技术股份有限公司 | Clock phase control circuit, clock phase control method, power amplification device and audio equipment |
-
2016
- 2016-07-27 CN CN201620796547.1U patent/CN205883049U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106100329B (en) * | 2016-07-27 | 2019-04-09 | 嘉兴市纳杰微电子技术有限公司 | Use the dcdc converter of digital synchronous logic control circuit |
| CN111510133A (en) * | 2020-04-09 | 2020-08-07 | 上海艾为电子技术股份有限公司 | Clock phase control circuit, clock phase control method, power amplification device and audio equipment |
| CN111510133B (en) * | 2020-04-09 | 2023-05-26 | 上海艾为电子技术股份有限公司 | Clock phase control circuit, clock phase control method, power amplifying device and audio equipment |
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