CN104578756B - A kind of DC DC pierce circuits of dual output - Google Patents
A kind of DC DC pierce circuits of dual output Download PDFInfo
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- CN104578756B CN104578756B CN201410826725.6A CN201410826725A CN104578756B CN 104578756 B CN104578756 B CN 104578756B CN 201410826725 A CN201410826725 A CN 201410826725A CN 104578756 B CN104578756 B CN 104578756B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K4/00—Generating pulses having essentially a finite slope or stepped portions
- H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
- H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
- H03K4/48—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
Abstract
The invention discloses a kind of DC DC pierce circuits of dual output, reference voltage V is addedR1During with enabling signal EN, internal oscillator circuit produces two frequency stationary phases with anti-phase square-wave signal V1And V2, the narrow pulse signal V that two-way phase difference is 180 degree is produced through two pulse-generating circuits3And V4, the output signal of this two pulse signals both directly as circuit, the unlatching of trigger switch pipe, and respectively in input voltage VIN, reference voltage VR2In the presence of enable signal EN, the sawtooth signal V that two-way phase difference is 180 degree is produced through sawtooth wave generating circuit5With V6As another output signal of circuit, the RMS current of two-way DC DC inputs is significantly reduced, the interference between two-way output is eliminated；The sawtooth waveforms generation unit of the present invention provides a ramp voltage signal, and the ramp voltage signal controlled with slope low level control and input voltage feed forward enhances the stability of voltage-mode loop.
Description
Technical field
The invention belongs to electronic circuit field, and in particular to a kind of DC-DC pierce circuits of dual output.
Background technology
Due to having the advantages that high conversion efficiency, dc-dc has been widely used in electronic system.With electronics
The development of system, the dc-dc of single-chip integration formula multiple-channel output has the advantage that integrated level is high, system design is succinct,
Hot issue as dc-dc research.But, multiple-channel output dc-dc still face input RMS current it is big,
The key issue interfered between passage etc., dc-dc is intended to high frequency development, and the raising of switching frequency can be compared
The reduction DC-DC of example exports the volume of LC filtering devices, or even realizes that inductance is integrated.
Voltage-mode dc-dc loop need not be to inductive current periodic samples, therefore when avoiding current sample
Between limit switch frequency the problem of raise, more suitable in high switching frequency application.In high-frequency electrical pressing mold dc-dc loop
In design, Compensation Design it can turn into development trend in single chip integrated loop, typical doubleway output dc-dc is shaken
Swing device circuit and produce constant clock signal, it determines the switch periods of converter, by pulse-generating circuit by internal clocking
Signal is converted into the narrow pulse signal of fixed pulse width, the turn-on cycles for opening converter；Sawtooth wave generating circuit is
PWM comparators provide a ramp voltage signal, and it is compared with error amplifier output signal adjusts to produce converter dutycycle
Section.But because the traditional way of the oscillator used in traditional two-way voltage-mode dc-dc is two-way all using same
Oscillator signal and sawtooth signal, so that the RMS current of input is big, interfering between two-way are big, circuit stability
Property is poor.
The content of the invention
It is above-mentioned not enough there is provided a kind of DC-DC pierce circuits of dual output it is an object of the invention to overcome, solve tradition
The RMS current of its input of the pierce circuit of doubleway output dc-dc it is big between two-way the problem of interfering.
In order to achieve the above object, the present invention includes that the internal oscillator unit of constant clock signal can be produced, can be by
Clock signal is converted into circuit structure identical the first burst pulse generation unit of the narrow pulse signal of fixed pulse width and second narrow
Impulse generating unit, and narrow pulse signal can be converted into the sawtooth waveforms of circuit structure identical first production of sawtooth signal
Raw unit and the second sawtooth waveforms generation unit；
The internal oscillator unit connects the first burst pulse generation unit and the second burst pulse generation unit respectively, and inside shakes
Swing unit connection reference voltage VR1With enable signal EN, internal oscillator unit is exported to the constant of the first burst pulse generation unit
Clock signal is 180 degree, respectively V with the phase difference exported to the constant clock signal of the second burst pulse generation unit1With
V2；The output end of first burst pulse generation unit and the second burst pulse generation unit exports narrow pulse signal V respectively3And V4, first
The output end of burst pulse generation unit and the second burst pulse generation unit is also respectively connected with the first sawtooth waveforms generation unit and second
The input of sawtooth waveforms generation unit；
The first sawtooth waveforms generation unit and the second sawtooth waveforms generation unit connection reference voltage VR2, enable signal EN and
Input voltage VIN, the output end of the first sawtooth waveforms generation unit and the second sawtooth waveforms generation unit exports sawtooth signal V respectively5
With sawtooth signal V6, sawtooth signal V5With sawtooth signal V6Phase difference be 180 degree.
The internal oscillator unit has first input end a, the second input b, the first output end c and the second output end d,
Wherein first input end a and the second input b connect reference voltage V respectivelyR1With enable signal EN, the first output end c and second
Output end d difference output voltages V1And V2；
The first burst pulse generation unit has an input e and an Ausgang, wherein input e input electricity
Press V1, its Ausgang output narrow pulse signal V3；Second burst pulse generation unit has an an input n and output end o,
Wherein input n input voltages V2, its output end o output narrow pulse signals V4；
The first sawtooth waveforms generation unit has first input end g, the second input h, the 3rd input j, the 4th defeated
Enter to hold k and output end m, wherein the first burst pulse of first input end g connections generation unit output narrow pulse signal V3, the
Two input h connection reference voltage VsR2, the 3rd input j connections enable signal EN, the 4th input k connection input voltages VIN,
Output end m output sawtooth signals V5；
The second sawtooth waveforms generation unit has first input end p, the second input q, the 3rd input r, the 4th defeated
Enter to hold s and output end t, wherein the second burst pulse of first input end p connections generation unit output narrow pulse signal V4, the
Two input q connection reference voltage VsIN, the 3rd input r connections enable signal EN, the 4th input s connection input voltages VR2,
Output end t output sawtooth signals V6；
The output narrow pulse signal V of the first burst pulse generation unit3A part is transferred to the first sawtooth waveforms and produces list
The first input end g of member, another part is used as output signal, the output narrow pulse signal V of the second burst pulse generation unit4One
Divide the first input end p for being transferred to the second sawtooth waveforms generation unit, another part is used as output signal.
The internal oscillator unit includes first comparator, the second comparator, rest-set flip-flop, the first phase inverter, second anti-
Phase device, the 3rd phase inverter, the 4th phase inverter, current source IR1, current source IR2, the first electric capacity C1, the second electric capacity C2, NMOS tube M101、
NMOS tube M102, PMOS M103, PMOS M104；
The in-phase input end connection reference voltage V of the first comparatorR1, end of oppisite phase passes through the first electric capacity C1It is connected to
Ground, and connect NMOS tube M101Drain electrode and PMOS M103Drain electrode, the output end connection rest-set flip-flop of first comparator
Reset terminal R, power end connection enables signal EN；
The in-phase input end connection reference voltage V of second comparatorR1, inverting input passes through the second electric capacity C2Connection
To ground, and connect NMOS tube M102Drain electrode and PMOS M104Drain electrode, the second comparator output end connection rest-set flip-flop
Put several end S, power end connection enables signal EN；
The input of output end Q the first phase inverters of connection of the rest-set flip-flop, while accessing NMOS tube M102Grid,
The output end of first phase inverter connects the input of the second phase inverter, while connecting NMOS tube M101Grid and output square wave
Signal V1, the square-wave signal V of the output end connection output of the second phase inverter2, NMOS tube M102Source ground, PMOS M104's
Grid connects the output end of the 4th phase inverter, PMOS M104Source electrode connection current source IR2Output end, the 4th phase inverter it is defeated
Enter end connection and enable signal EN, current source IR2Input connection internal electric source VDD；
The NMOS tube M101Source ground, PMOS M103Grid connect the 3rd phase inverter output end, PMOS
M103Source electrode connection current source IR1Output end, current source IR1Input connection internal electric source VDD, the 3rd phase inverter it is defeated
Enter end connection and enable signal EN.
The circuit structure of the first burst pulse generation unit and the second burst pulse generation unit is identical, including the first D
Trigger, the 5th phase inverter, hex inverter, the 7th phase inverter, the 8th phase inverter, the 5th electric capacity C5, the 6th electric capacity C6、NMOS
Pipe M201, PMOS M202, the 4th resistance R4, the 5th resistance R5；
The square-wave signal V that the input end of clock CLK connections of first d type flip flop are produced by internal oscillator unit1Or V2；
The one of output end XQ of input D connections of first d type flip flop, while connecting the input and NMOS tube of hex inverter
M201Grid, the input of another phase inverter of output end Q connections the 5th of the first d type flip flop, the reset terminal of the first d type flip flop
The output feedback end of the phase inverter of RST connections the 8th；
The output end connection narrow pulse signal V of 5th phase inverter3Or V4, the output end connection PMOS of hex inverter
Pipe M202Grid, while passing through the 4th resistance R4With the 5th electric capacity C5Ground is connected to, and passes through the 4th resistance R4Connect NMOS
Pipe M201Drain electrode and the 7th phase inverter input；
The NMOS tube M201Source ground, the output end of the 7th phase inverter passes through the 5th resistance R5With the 6th electric capacity C6Even
Ground is connected to, and passes through the 5th resistance R5It is connected to the input and PMOS M of the 8th phase inverter202Drain electrode, PMOS M202
Source electrode connection internal electric source VDD.
The circuit structure of the first sawtooth waveforms generation unit and the second sawtooth waveforms generation unit is identical, is put including error
Big device, the second d type flip flop, the 9th phase inverter, the 3rd comparator, first resistor R1, second resistance R2, 3rd resistor R3, the 3rd electricity
Hold C3, the 4th electric capacity C4, PMOS M302, PMOS M304, PMOS M306, PMOS M308, PMOS M309, PMOS M310、
NMOS tube M301, NMOS tube M303, NMOS tube M305, NMOS tube M307, NMOS tube M311；
The in-phase input end connection reference voltage V of the error amplifierR2, the inverting input of error amplifier connects it
Output end, while connecting NMOS tube M301, NMOS tube M305With PMOS M302, PMOS M306Source electrode, error amplifier makes
Can end connection enable signal EN；
The input end of clock CLK of second d type flip flop receives narrow pulse signal V3Or V4, input D ends connect the 2nd D
One output end XQ of trigger, reset terminal RST connections enable signal EN, the input of another phase inverter of output end Q connections the 9th
End, while connecting voltage signal V8；
The output end connection voltage signal V of 9th phase inverter7；
The in-phase input end of 3rd comparator passes through second resistance R2It is connected to input voltage VIN, inverting input passes through
First resistor R1Ground connection, while connecting NMOS tube M311Source electrode, the output end connection NMOS tube M of the 3rd comparator311Grid,
Enable termination and enable signal EN；
The NMOS tube M301With PMOS M302Constitute transmission gate TG1, NMOS tube M301With PMOS M302Grid difference
Connect voltage signal V7And V8, NMOS tube M301With PMOS M302Drain electrode all pass through the 3rd electric capacity C3Ground connection；NMOS tube M303With
PMOS M304Constitute transmission gate TG2, NMOS tube M303With PMOS M304Grid connect voltage signal V respectively8And V7, NMOS tube
M303With PMOS M304Drain electrode all connect sawtooth signal V5Or V6, NMOS tube M303With PMOS M304Source electrode all pass through
Three electric capacity C3Ground connection；NMOS tube M305With PMOS M306Constitute transmission gate TG3, NMOS tube M305With PMOS M306Grid difference
Connect voltage signal V8And V7, NMOS tube M305With PMOS M306Drain electrode all pass through the 4th electric capacity C4Ground connection；NMOS tube M307With
PMOS M308Constitute transmission gate TG4, NMOS tube M307With PMOS M308Grid connect voltage signal V respectively7And V8, NMOS tube
M307With PMOS M308Drain electrode all connect sawtooth signal V5Or V6, their source electrode all passes through the 4th electric capacity C4Ground connection；
The PMOS M309With PMOS M310Constitute current mirror, PMOS M309With PMOS M310Source electrode be connected on inside
On power vd D, PMOS M309Drain electrode connection sawtooth signal V5, PMOS M310Drain electrode connection NMOS tube M311Drain electrode.
The circuit structure of the first sawtooth waveforms generation unit and the second sawtooth waveforms generation unit is identical, is put including error
Big device, the second d type flip flop, the 9th phase inverter, NMOS tube M301, NMOS tube M303, NMOS tube M305, NMOS tube M307, PMOS
M302, PMOS M304, PMOS M306, PMOS M308, the 3rd electric capacity C3, the 4th electric capacity C4With current source IR3；
The in-phase input end connection reference voltage V of the error amplifierR2, inverting input connects its output end, simultaneously
Connect NMOS tube M301, NMOS tube M305With PMOS M302, PMOS M306Source electrode, error amplifier Enable Pin connection enable
Signal EN；
The input end of clock CLK input narrow pulse signals V of second d type flip flop3Or V4, the D of input D connections the 2nd touch
One output end XQ of hair device, reset terminal RST connections enable signal EN, the input of another phase inverter of output end Q connections the 9th,
Voltage signal V is connected simultaneously8；
The output end connection voltage signal V of 9th phase inverter7；
The in-phase input end of 3rd comparator passes through second resistance R2It is connected to VIN, inverting input passes through first resistor
R1Ground connection, while connecting NMOS tube M311Source electrode, the output end connection NMOS tube M of the 3rd comparator311Grid, the 3rd compares
The enable termination of device enables signal EN；
The NMOS tube M301With PMOS M302Constitute transmission gate TG1, NMOS tube M301With PMOS M302Grid difference
Connect voltage signal V7And V8, NMOS tube M301With PMOS M302Drain electrode all pass through the 3rd electric capacity C3Ground connection；NMOS tube M303With
PMOS M304Constitute transmission gate TG2, NMOS tube M303With PMOS M304Grid connect voltage signal V respectively8And V7, NMOS tube
M303With PMOS M304Drain electrode all connect sawtooth signal V5Or V6, NMOS tube M303With PMOS M304Source electrode all pass through
Three electric capacity C3Ground connection；NMOS tube M305With PMOS M306Constitute transmission gate TG3, NMOS tube M305With PMOS M306Grid difference
Connect voltage signal V8And V7, NMOS tube M305With PMOS M306Drain electrode all pass through the 4th electric capacity C4Ground connection；NMOS tube M307With
PMOS M308Constitute transmission gate TG4, NMOS tube M307With PMOS M308Grid connect voltage signal V respectively7And V8, NMOS tube
M307With PMOS M308Drain electrode all connect sawtooth signal V5Or V6, NMOS tube M307With PMOS M308Source electrode all pass through
Four electric capacity C4Ground connection；
The current source IR3Positive pole connection internal electric source VDD, negative pole connection sawtooth signal V5Or V6。
The circuit structure of the first burst pulse generation unit and the second burst pulse generation unit is identical, including the first D
Trigger, the 5th phase inverter, hex inverter, NAND gate, the 8th phase inverter, the tenth phase inverter, the 7th electric capacity C7；
The input end of clock CLK of first d type flip flop meets V1Or V2, its input D connects the input of the tenth phase inverter,
Connecting an its output end XQ, the output end XQ of the first d type flip flop connects the input of hex inverter, reset terminal RST simultaneously
The output end of the 8th phase inverter is connect, another output end Q connects the input of the 5th phase inverter；
The output end of 5th phase inverter connects the output narrow pulse signal V of the unit3Or V4；
The output end of the hex inverter passes through the 7th electric capacity C7Ground connection, while connecting an input of NAND gate；
The input of 8th phase inverter connects the output end of NAND gate；
The output end of tenth phase inverter connects another input of NAND gate.
Compared with prior art, the invention has the advantages that：
1st, circuit of the present invention is using two clock signals and ramp signal for differing 180 degree, and 180 degree clock difference is designed with
The RMS current of two-way DC-DC inputs is reduced to effect, the interference between two-way output is eliminated；
2nd, the design of switching frequency of the invention difference can reduce switching current input path, switching node, path
The spring voltage amplitude of upper formation, therefore play a part of interfering between decrease path, improve stability, improve EMI.
3rd, sawtooth waveforms generation unit of the invention provides a ramp voltage signal, with slope low level control and input
The ramp voltage signal of voltage feedforward control enhances the stability of voltage-mode loop.
Further, sawtooth waveforms generation unit circuit of the invention is by narrow pulse signal V3Or V4The sawtooth waveforms production of control
The concrete form of raw circuit, narrow pulse signal V3Or V4It is the narrow pulse signal of oscillator frequency, becomes after d type flip flop is divided
Into square wave, the square-wave signal goes control by transmission gate TG1、TG2、TG3、TG4The through and off of the switching network of composition, wherein TG1With
TG2Same-phase is controlled, TG3With TG4Same-phase is controlled, and two groups of switch alternate conductions give the electric capacity C of electric capacity the 3rd3With the 4th electric capacity C4Fill
Electric discharge, introduces dead band control logic in sawtooth signal RAMP1, switching network driving to produce, can effectively suppress switching signal
The burr interference of generation.
Brief description of the drawings
Fig. 1 is the structured flowchart of the present invention；
Fig. 2 is the internal oscillator element circuit schematic diagram in the embodiment of the present invention 1.
Fig. 3 is burst pulse generation unit circuit theory diagrams in the embodiment of the present invention 1；
Fig. 4 is sawtooth waveforms generation unit circuit theory diagrams in the embodiment of the present invention 1；
Fig. 5 is sawtooth waveforms generation unit circuit theory diagrams in the embodiment of the present invention 2；
Fig. 6 is burst pulse generation unit circuit theory diagrams in the embodiment of the present invention 3.
Embodiment
The present invention will be further described with reference to the accompanying drawings and examples.
Embodiment 1：
Referring to Fig. 1, the present invention includes that the internal oscillator unit of constant clock signal can be produced, and can believe internal clocking
The the first burst pulse generation unit and the second burst pulse generation unit of the narrow pulse signal of fixed pulse width number are converted into, and is produced
The the first sawtooth waveforms generation unit and the second sawtooth waveforms generation unit of the sawtooth signal of two phase difference 180 degrees；
Internal oscillator unit connects the first burst pulse generation unit and the second burst pulse generation unit, internal oscillator list respectively
Member connection reference voltage VR1With enable signal EN, internal oscillator unit exports the constant clock to the first burst pulse generation unit
Signal is 180 degree with the phase difference exported to the constant clock signal of the second burst pulse generation unit, and the first burst pulse is produced
The output end of unit and the second burst pulse generation unit exports narrow pulse signal V respectively3And V4, the first burst pulse generation unit and
The output end of second burst pulse generation unit is also respectively connected with the first sawtooth waveforms generation unit and the second sawtooth waveforms generation unit
Input；
First burst pulse generation unit and the second burst pulse generation unit connection reference voltage VR2, enable signal EN and input
Voltage VIN, the output end of the first burst pulse generation unit and the second burst pulse generation unit exports sawtooth signal V respectively5And saw
Tooth ripple signal V6。
Internal oscillator unit has first input end a, the second input b, the first output end c and the second output end d, wherein
First input end a and the second input b connect reference voltage V respectivelyR1Exported with signal EN, the first output end c and second is enabled
Hold d difference output voltages V1And V2；
First burst pulse generation unit has an input e and an Ausgang, wherein input e input voltages V1,
Its Ausgang output narrow pulse signal V3；Second burst pulse generation unit has an an input n and output end o, wherein
Input n input voltages V2, its output end o output narrow pulse signals V4；
First sawtooth waveforms generation unit has first input end g, the second input h, the 3rd input j, the 4th input k
With an output end m, wherein the first burst pulse of first input end g connections generation unit output narrow pulse signal V3, second is defeated
Enter to hold h connection reference voltage VsR2, the 3rd input j connections enable signal EN, the 4th input k connection input voltages VIN, output
Hold m output sawtooth signals V5；
Second sawtooth waveforms generation unit has first input end p, the second input q, the 3rd input r, the 4th input s
With an output end t, wherein the second burst pulse of first input end p connections generation unit output narrow pulse signal V4, second is defeated
Enter to hold q connection reference voltage VsIN, the 3rd input r connections enable signal EN, the 4th input s connection input voltages VR2, output
Hold t output sawtooth signals V6；
The output narrow pulse signal V of first burst pulse generation unit3A part is transferred to the first sawtooth waveforms generation unit
First input end g, another part is used as output signal, the output narrow pulse signal V of the second burst pulse generation unit4A part is passed
The first input end p of the second sawtooth waveforms generation unit is defeated by, another part is used as output signal.
Referring to Fig. 2, internal oscillator unit includes first comparator 101, the second comparator 102, rest-set flip-flop 103, first
Phase inverter 104, the second phase inverter 105, the 3rd phase inverter 106, the 4th phase inverter 107, current source IR1, current source IR2, first electricity
Hold C1, the second electric capacity C2, NMOS tube M101, NMOS tube M102, PMOS M103, PMOS M104；
The in-phase input end connection reference voltage V of first comparator 101R1, end of oppisite phase passes through the first electric capacity C1It is connected to ground,
And connect NMOS tube M101Drain electrode and PMOS M103Drain electrode, first comparator 101 output end connection rest-set flip-flop 103
Reset terminal R, power end connection enables signal EN；
The in-phase input end connection reference voltage V of second comparator 102R1, inverting input passes through the second electric capacity C2Connection
To ground, and connect NMOS tube M102Drain electrode and PMOS M104Drain electrode, the second comparator 102 output end connection RS triggering
Device 103 puts several end S, and power end connection enables signal EN；
The input of the first phase inverter of output end Q connections 104 of rest-set flip-flop 103, while accessing NMOS tube M102Grid
Pole, the output end of the first phase inverter 104 connects the input of the second phase inverter 105, while connecting NMOS tube M101Grid and defeated
The square-wave signal V gone out1, the square-wave signal V of the output end connection output of the second phase inverter 1052, NMOS tube M102Source ground,
PMOS M104Grid connect the 4th phase inverter 107 output end, PMOS M104Source electrode connection current source IR2Output end,
The input connection of 4th phase inverter 107 enables signal EN, current source IR2Input connection internal electric source VDD；
NMOS tube M101Source ground, PMOS M103Grid connect the 3rd phase inverter 106 output end, PMOS
M103Source electrode connection current source IR1Output end, current source IR1Input connection internal electric source VDD, the 3rd phase inverter 106
Input connection enable signal EN.
Referring to Fig. 3, the circuit structure of the first burst pulse generation unit and the second burst pulse generation unit is identical, including
One d type flip flop 201, the 5th phase inverter 202, hex inverter 203, the 7th phase inverter 207, the 8th phase inverter 205, the 5th electric capacity
C5, the 6th electric capacity C6, NMOS tube M201, PMOS M202, the 4th resistance R4, the 5th resistance R5；
The square-wave signal V that the input end of clock CLK connections of first d type flip flop 201 are produced by internal oscillator unit1Or V2；The
The one of output end XQ of input D connections of one d type flip flop 201, while connecting the input and NMOS of hex inverter 203
Pipe M201Grid, the input of another phase inverter 202 of output end Q connections the 5th of the first d type flip flop 201, the first d type flip flop
The output feedback end of 201 phase inverter 205 of reset terminal RST connections the 8th；
The output end connection narrow pulse signal V of 5th phase inverter 2023Or V4, for the output of the unit, hex inverter
203 output end connection PMOS M202Grid, while passing through the 4th resistance R4With the 5th electric capacity C5Ground is connected to, and is passed through
4th resistance R4Connect NMOS tube M201Drain electrode and the 7th phase inverter 207 input；
NMOS tube M201Source ground, the output end of the 7th phase inverter 207 passes through the 5th resistance R5With the 6th electric capacity C6Even
Ground is connected to, and passes through the 5th resistance R5It is connected to the input and PMOS M of the 8th phase inverter 205202Drain electrode, PMOS
M202Source electrode connection internal electric source VDD.
Referring to Fig. 4, the circuit structure of the first sawtooth waveforms generation unit and the second sawtooth waveforms generation unit is identical, including by mistake
Poor amplifier 301, the second d type flip flop 302, the 9th phase inverter 303, the 3rd comparator 304, first resistor R1, second resistance R2、
3rd resistor R3, the 3rd electric capacity C3, the 4th electric capacity C4, PMOS M302, PMOS M304, PMOS M306, PMOS M308、PMOS
Pipe M309, PMOS M310, NMOS tube M301, NMOS tube M303, NMOS tube M305, NMOS tube M307, NMOS tube M311；
The in-phase input end connection reference voltage V of error amplifier 301R2, the inverting input connection of error amplifier 301
Its output end, while connecting NMOS tube M301, NMOS tube M305With PMOS M302, PMOS M306Source electrode, error amplifier 301
Enable Pin connection enable signal EN, for controlling its working condition；
The input end of clock CLK of second d type flip flop 302 receives narrow pulse signal V3Or V4, input D ends connect the 2nd D and touched
An output end XQ of device 302 is sent out, reset terminal RST connections enable signal EN, another phase inverter 303 of output end Q connections the 9th
Input, while connecting voltage signal V8；
The output end connection voltage signal V of 9th phase inverter 3037；
The in-phase input end of 3rd comparator 304 passes through second resistance R2It is connected to input voltage VIN, inverting input passes through
First resistor R1Ground connection, while connecting NMOS tube M311Source electrode, the output end connection NMOS tube M of the 3rd comparator 304311Grid
Pole, enables termination and enables signal EN, for controlling whether it works；
NMOS tube M301With PMOS M302Constitute transmission gate TG1, NMOS tube M301With PMOS M302Grid connect respectively
Voltage signal V7And V8, NMOS tube M301With PMOS M302Drain electrode all pass through the 3rd electric capacity C3Ground connection；NMOS tube M303And PMOS
Pipe M304Constitute transmission gate TG2, NMOS tube M303With PMOS M304Grid connect voltage signal V respectively8And V7, NMOS tube M303
With PMOS M304Drain electrode all connect sawtooth signal V5, NMOS tube M303With PMOS M304Source electrode all pass through the 3rd electric capacity C3
Ground connection；NMOS tube M305With PMOS M306Constitute transmission gate TG3, NMOS tube M305With PMOS M306Grid connect voltage respectively
Signal V8And V7, NMOS tube M305With PMOS M306Drain electrode all pass through the 4th electric capacity C4Ground connection；NMOS tube M307With PMOS M308
Constitute transmission gate TG4, NMOS tube M307With PMOS M308Grid connect voltage signal V respectively7And V8, NMOS tube M307And PMOS
Pipe M308Drain electrode all connect the output sawtooth signal V of the unit5, their source electrode all passes through the 4th electric capacity C4Ground connection；
PMOS M309With PMOS M310Constitute current mirror, PMOS M309With PMOS M310Source electrode be connected on internal electric source
On VDD, PMOS M309Drain electrode connection sawtooth signal V5, PMOS M310Drain electrode connection NMOS tube M311Drain electrode.
PMOS M309With PMOS M310Current mirror is constituted, their source electrode is connected on internal electric source VDD, and PMOS
M309Drain electrode be connected to sawtooth signal V5On, PMOS M310Drain electrode be connected to NMOS tube M311Source electrode on；By taking phase
The same wide long size of metal-oxide-semiconductor, obtains identical electric current, its current relationship is：
Wherein, ID311For NMOS tube M311On drain current, ID309For PMOS M309Drain current, W/L is metal-oxide-semiconductor
Breadth length ratio.
The pierce circuit of the present embodiment, it uses constant-current charge, the voltage controlled oscillator structure of repid discharge, complete through two
Holosymmetric discharge and recharge timing circuit produces a square-wave signal, and the clock signal of frequency fixation, its signal week are provided for circuit
Phase is the first electric capacity C1With the second electric capacity C2Discharge and recharge time sum.Due to the first electric capacity C1With the second electric capacity C2Discharge and recharge
Circuit structure is symmetrical and parameter is identical, therefore the cycle of half of circuit is just equal to the half of cycle oscillator.Only to the first electricity
Hold C1Half of charge and discharge process derived, it is assumed that the first electric capacity C1Discharge and recharge time sum be TC1, the charging interval is
TC1_ON, discharge time is TC1_OFF, then
TC1=TC1_ON+TC1_OFF
First electric capacity C1Charging interval TC1_ONFor：
Wherein, VR1On the basis of voltage, IR1To flow through PMOS M103Charging current.
First electric capacity C1It is by NMOS tube M101Discharged, the NMOS tube M during discharging101Drain-source voltage all the time
Less than overdrive voltage, therefore it is operated in linear zone.NMOS tube M101A linear resistance can approximately be regarded as, its resistance can
It is written as
First electric capacity C1Pass through NMOS tube M101The discharge time of electric discharge can be represented with equation below
Wherein, VC1_HFor voltage of electric capacity when initial, VC1_LFor through TC1_OFFVoltage after electric discharge.
Embodiment 2：
The internal oscillator unit and burst pulse generation unit of the present embodiment are identical with embodiment 1, tooth ripple are produced single
The circuit of member is changed.
Referring to Fig. 5, the circuit structure of the first sawtooth waveforms generation unit and the second sawtooth waveforms generation unit is identical, including by mistake
Poor amplifier 301, the second d type flip flop 302, the 9th phase inverter 303, NMOS tube M301, NMOS tube M303, NMOS tube M305, NMOS tube
M307, PMOS M302, PMOS M304, PMOS M306, PMOS M308, the 3rd electric capacity C3, the 4th electric capacity C4With current source IR3；
The in-phase input end connection reference voltage V of error amplifier 301R2, inverting input connects its output end, connects simultaneously
Meet NMOS tube M301, NMOS tube M305With PMOS M302, PMOS M306Source electrode, error amplifier 301 Enable Pin connection make
Energy signal EN, for controlling its working condition；
The input CLK input narrow pulse signals V of second d type flip flop 3023Or V4, input D the second d type flip flops of connection
A 302 output end XQ, reset terminal RST connections enable signal EN, the input of another phase inverter 303 of output end Q connections the 9th
End, while connecting voltage signal V8；
The output end connection voltage signal V of 9th phase inverter 3037；
NMOS tube M301With PMOS M302Constitute transmission gate TG1, NMOS tube M301With PMOS M302Grid connect respectively
Voltage signal V7And V8, NMOS tube M301With PMOS M302Drain electrode all pass through the 3rd electric capacity C3Ground connection；NMOS tube M303And PMOS
Pipe M304Constitute transmission gate TG2, NMOS tube M303With PMOS M304Grid connect voltage signal V respectively8And V7, NMOS tube M303
With PMOS M304Drain electrode all connect sawtooth signal V5Or V6, NMOS tube M303With PMOS M304Source electrode all pass through the 3rd electricity
Hold C3Ground connection；NMOS tube M305With PMOS M306Constitute transmission gate TG3, NMOS tube M305With PMOS M306Grid connect respectively
Voltage signal V8And V7, NMOS tube M305With PMOS M306Drain electrode all pass through the 4th electric capacity C4Ground connection；NMOS tube M307And PMOS
Pipe M308Constitute transmission gate TG4, NMOS tube M307With PMOS M308Grid connect voltage signal V respectively7And V8, NMOS tube M307
With PMOS M308Drain electrode all connect sawtooth signal V5Or V6, NMOS tube M307With PMOS M308Source electrode all pass through the 4th electricity
Hold C4Ground connection；
Current source IR3Positive pole connection internal electric source VDD, negative pole connection sawtooth signal V5Or V6。
Narrow pulse signal V3Or V4It is the narrow pulse signal of oscillator frequency, square wave is become after d type flip flop is divided, should
Square-wave signal goes control by transmission gate TG1、TG2、TG3、TG4The through and off of the switching network of composition.Wherein TG1With TG2Same-phase
Control, TG3With TG4Same-phase is controlled, and two groups of switch alternate conductions give the electric capacity C of electric capacity the 3rd3With the 4th electric capacity C4Discharge and recharge, comes
Produce sawtooth signal RAMP1.Dead band control logic is introduced in switching network driving, can effectively suppress the hair of switching signal generation
Thorn interference.
Embodiment 3：
The internal oscillator unit and sawtooth waveforms generation unit of the present embodiment are identical with embodiment 1, and burst pulse is produced
The circuit of unit is changed.
Referring to Fig. 6, the circuit structure of the first burst pulse generation unit and the second burst pulse generation unit is identical, including
One d type flip flop 201, the 5th phase inverter 202, hex inverter 203, NAND gate 204, the 8th phase inverter 205, the tenth phase inverter
206th, the 7th electric capacity C7；
The input end of clock CLK of first d type flip flop 201 meets V1Or V2, its input D connects the input of the tenth phase inverter 206
End, while connecting its an output end XQ, the output end XQ of the first d type flip flop 201 connects the input of hex inverter 203,
Reset terminal RST connects the output end of the 8th phase inverter 205, and another output end Q connects the input of the 5th phase inverter 202；
The output end of 5th phase inverter 202 connects the output narrow pulse signal V of the unit3Or V4；
The output end of hex inverter 203 passes through the 7th electric capacity C7Ground connection, while connecting an input of NAND gate 204
End；
The input of 8th phase inverter 205 connects the output end of NAND gate 204；
The output end of tenth phase inverter 206 connects another input of NAND gate 204.
When circuit is started power up, that is, add reference voltage VR1During with enabling signal EN, internal oscillator circuit produces two frequencies
Rate stationary phase is with anti-phase CLK0 and CLK180, i.e. square-wave signal V1And V2, two-way phase is produced through two pulse-generating circuits
Difference is the narrow pulse signal V of 180 degree3And V4, the output signal of this two pulse signals both directly as circuit, trigger switch pipe
Unlatching, and respectively in input voltage VIN, reference voltage VR2In the presence of enable signal EN, produced through sawtooth wave generating circuit
Raw two-way phase difference is the sawtooth signal V of 180 degree5With V6It is used as another output signal of circuit.
In the design of multichannel dc-dc, differed by being introduced to each road converter clock signal, allow each road converter
High avris switch open successively, so do can play a part of effectively reduction input RMS current.The input of single phase converter
The maximum of RMS current is appeared under 50% duty cycle condition, and is appeared in for the maximum RMS current of converter of two-phase
Under conditions of 25% and 75% dutycycle, its maximum RMS current only has the half of single phase converter.As can be seen here, two-way DC-DC
Converter is designed using 180 degree phase difference, can effectively reduce the RMS current of input.In addition, switching frequency difference design may be used also
With reduce switching current input path, switching node, the spring voltage amplitude that is formed on path, therefore play decrease path
Between interfere, improve stability, improve EMI effect.
Claims (5)
1. a kind of DC-DC pierce circuits of dual output, it is characterised in that：Inside including that can produce constant clock signal shakes
Unit is swung, the burst pulse of circuit structure identical first that clock signal can be converted into the narrow pulse signal of fixed pulse width is produced
Unit and the second burst pulse generation unit, and narrow pulse signal can be converted into the circuit structure identical of sawtooth signal
First sawtooth waveforms generation unit and the second sawtooth waveforms generation unit；
The internal oscillator unit connects the first burst pulse generation unit and the second burst pulse generation unit, internal oscillator list respectively
Member connection reference voltage VR1With enable signal EN, internal oscillator unit exports the constant clock to the first burst pulse generation unit
Signal is 180 degree, respectively V with the phase difference exported to the constant clock signal of the second burst pulse generation unit1And V2；The
The output end of one burst pulse generation unit and the second burst pulse generation unit exports narrow pulse signal V respectively3And V4, the first narrow arteries and veins
The output end for rushing generation unit and the second burst pulse generation unit is also respectively connected with the first sawtooth waveforms generation unit and the second sawtooth
The input of ripple generation unit；
The first sawtooth waveforms generation unit and the second sawtooth waveforms generation unit connection reference voltage VR2, enable signal EN and input
Voltage VIN, the output end of the first sawtooth waveforms generation unit and the second sawtooth waveforms generation unit exports sawtooth signal V respectively5And saw
Tooth ripple signal V6, sawtooth signal V5With sawtooth signal V6Phase difference be 180 degree；
The internal oscillator unit has first input end a, the second input b, the first output end c and the second output end d, wherein
First input end a and the second input b connect reference voltage V respectivelyR1Exported with signal EN, the first output end c and second is enabled
Hold d difference output voltages V1And V2；
The first burst pulse generation unit has an input e and an Ausgang, wherein input e input voltages V1,
Its Ausgang output narrow pulse signal V3；Second burst pulse generation unit has an an input n and output end o, wherein
Input n input voltages V2, its output end o output narrow pulse signals V4；
The first sawtooth waveforms generation unit has first input end g, the second input h, the 3rd input j, the 4th input k
With an output end m, wherein the first burst pulse of first input end g connections generation unit output narrow pulse signal V3, second is defeated
Enter to hold h connection reference voltage VsR2, the 3rd input j connections enable signal EN, the 4th input k connection input voltages VIN, output
Hold m output sawtooth signals V5；
The second sawtooth waveforms generation unit has first input end p, the second input q, the 3rd input r, the 4th input s
With an output end t, wherein the second burst pulse of first input end p connections generation unit output narrow pulse signal V4, second is defeated
Enter to hold q connection reference voltage VsIN, the 3rd input r connections enable signal EN, the 4th input s connection input voltages VR2, output
Hold t output sawtooth signals V6；
The output narrow pulse signal V of the first burst pulse generation unit3A part is transferred to the of the first sawtooth waveforms generation unit
One input g, another part is used as output signal, the output narrow pulse signal V of the second burst pulse generation unit4Part transmission
To the first input end p of the second sawtooth waveforms generation unit, another part is used as output signal；
The circuit structure of the first burst pulse generation unit and the second burst pulse generation unit is identical, is triggered including the first D
Device (201), the 5th phase inverter (202), hex inverter (203), the 7th phase inverter (207), the 8th phase inverter (205), the 5th
Electric capacity C5, the 6th electric capacity C6, NMOS tube M201, PMOS M202, the 4th resistance R4, the 5th resistance R5；
The square-wave signal V that the input end of clock CLK ends connection of first d type flip flop (201) is produced by internal oscillator unit1Or
V2；The one of output end XQ of input D connections of first d type flip flop (201), while connecting the defeated of hex inverter (203)
Enter end and NMOS tube M201Grid, the input of another phase inverter (202) of output end Q connections the 5th of the first d type flip flop (201)
End, the output feedback end of the phase inverter (205) of reset terminal RST connections the 8th of the first d type flip flop (201)；
The output end connection narrow pulse signal V of 5th phase inverter (202)3Or V4, the output end company of hex inverter (203)
Meet PMOS M202Grid, while passing through the 4th resistance R4With the 5th electric capacity C5Ground is connected to, and passes through the 4th resistance R4Even
Meet NMOS tube M201Drain electrode and the 7th phase inverter (207) input；
The NMOS tube M201Source ground, the output end of the 7th phase inverter (207) passes through the 5th resistance R5With the 6th electric capacity C6
Ground is connected to, and passes through the 5th resistance R5It is connected to the input and PMOS M of the 8th phase inverter (205)202Drain electrode,
PMOS M202Source electrode connection internal electric source VDD.
2. a kind of DC-DC pierce circuits of dual output according to claim 1, it is characterised in that：The internal oscillator
Unit includes first comparator (101), the second comparator (102), rest-set flip-flop (103), the first phase inverter (104), second anti-
Phase device (105), the 3rd phase inverter (106), the 4th phase inverter (107), current source IR1, current source IR2, the first electric capacity C1, second electricity
Hold C2, NMOS tube M101, NMOS tube M102, PMOS M103, PMOS M104；
The in-phase input end connection reference voltage V of the first comparator (101)R1, end of oppisite phase passes through the first electric capacity C1It is connected to
Ground, and connect NMOS tube M101Drain electrode and PMOS M103Drain electrode, first comparator (101) output end connection RS triggering
The reset terminal R of device (103), power end connection enables signal EN；
The in-phase input end connection reference voltage V of second comparator (102)R1, inverting input passes through the second electric capacity C2Even
Ground is connected to, and connects NMOS tube M102Drain electrode and PMOS M104Drain electrode, the second comparator (102) output end connection RS
Trigger (103) puts several end S, and power end connection enables signal EN；
The input of output end Q the first phase inverters of connection (104) of the rest-set flip-flop (103), while accessing NMOS tube M102's
Grid, the output end of the first phase inverter (104) connects the input of the second phase inverter (105), while connecting NMOS tube M101Grid
Pole and the square-wave signal V of output1, the square-wave signal V of the output end connection output of the second phase inverter (105)2, NMOS tube M102Source
Pole is grounded, PMOS M104Grid connect the 4th phase inverter (107) output end, PMOS M104Source electrode connection current source IR2
Output end, the 4th phase inverter (107) input connection enable signal EN, current source IR2Input connection internal electric source
VDD；
The NMOS tube M101Source ground, PMOS M103Grid connect the 3rd phase inverter (106) output end, PMOS
M103Source electrode connection current source IR1Output end, current source IR1Input connection internal electric source VDD, the 3rd phase inverter
(106) input connection enables signal EN.
3. a kind of DC-DC pierce circuits of dual output according to claim 1, it is characterised in that：First sawtooth
The circuit structure of ripple generation unit and the second sawtooth waveforms generation unit is identical, is triggered including error amplifier (301), the 2nd D
Device (302), the 9th phase inverter (303), the 3rd comparator (304), first resistor R1, second resistance R2, 3rd resistor R3, the 3rd
Electric capacity C3, the 4th electric capacity C4, PMOS M302, PMOS M304, PMOS M306, PMOS M308, PMOS M309, PMOS M310、
NMOS tube M301, NMOS tube M303, NMOS tube M305, NMOS tube M307, NMOS tube M311；
The in-phase input end connection reference voltage V of the error amplifier (301)R2, the inverting input of error amplifier (301)
Its output end is connected, while connecting NMOS tube M301, NMOS tube M305With PMOS M302, PMOS M306Source electrode, error amplification
The Enable Pin connection of device (301) enables signal EN；
The input end of clock CLK of second d type flip flop (302) receives narrow pulse signal V3Or V4, input D ends connect the 2nd D
One output end XQ of trigger (302), reset terminal RST connections enable signal EN, another phase inverter of output end Q connections the 9th
(303) input, while connecting voltage signal V8；
The output end connection voltage signal V of 9th phase inverter (303)7；
The in-phase input end of 3rd comparator (304) passes through second resistance R2It is connected to input voltage VIN, R3, inverting input
Pass through first resistor R1Ground connection, while connecting NMOS tube M311Source electrode, the 3rd comparator (304) output end connection NMOS tube
M311Grid, enable termination and enable signal EN；
The NMOS tube M301With PMOS M302Constitute transmission gate TG1, NMOS tube M301With PMOS M302Grid connect electricity respectively
Press signal V7And V8, NMOS tube M301With PMOS M302Drain electrode all pass through the 3rd electric capacity C3Ground connection；NMOS tube M303And PMOS
M304Constitute transmission gate TG2, NMOS tube M303With PMOS M304Grid connect voltage signal V respectively8And V7, NMOS tube M303With
PMOS M304Drain electrode all connect sawtooth signal V5Or V6, NMOS tube M303With PMOS M304Source electrode all pass through the 3rd electric capacity
C3Ground connection；NMOS tube M305With PMOS M306Constitute transmission gate TG3, NMOS tube M305With PMOS M306Grid connect electricity respectively
Press signal V8And V7, NMOS tube M305With PMOS M306Drain electrode all pass through the 4th electric capacity C4Ground connection；NMOS tube M307And PMOS
M308Constitute transmission gate TG4, NMOS tube M307With PMOS M308Grid connect voltage signal V respectively7And V8, NMOS tube M307With
PMOS M308Drain electrode all connect sawtooth signal V5Or V6, their source electrode all passes through the 4th electric capacity C4Ground connection；
The PMOS M309With PMOS M310Constitute current mirror, PMOS M309With PMOS M310Source electrode be connected on internal electric source
On VDD, PMOS M309Drain electrode connection sawtooth signal V5, PMOS M310Drain electrode connection NMOS tube M311Drain electrode.
4. a kind of DC-DC pierce circuits of dual output according to claim 1, it is characterised in that：First sawtooth
The circuit structure of ripple generation unit and the second sawtooth waveforms generation unit is identical, is triggered including error amplifier (301), the 2nd D
Device (302), the 9th phase inverter (303), NMOS tube M301, NMOS tube M303, NMOS tube M305, NMOS tube M307, PMOS M302、
PMOS M304, PMOS M306, PMOS M308, the 3rd electric capacity C3, the 4th electric capacity C4With current source IR3；
The in-phase input end connection reference voltage V of the error amplifier (301)R2, inverting input connects its output end, simultaneously
Connect NMOS tube M301, NMOS tube M305With PMOS M302, PMOS M306Source electrode, the Enable Pin of error amplifier (301) connects
Meet enable signal EN；
The input CLK input narrow pulse signals V of second d type flip flop (302)3Or V4, input D the second d type flip flops of connection
(302) an output end XQ, reset terminal RST connections enable signal EN, another phase inverter (303) of output end Q connections the 9th
Input, while connecting voltage signal V8；
The output end connection voltage signal V of 9th phase inverter (303)7；
The NMOS tube M301With PMOS M302Constitute transmission gate TG1, NMOS tube M301With PMOS M302Grid connect electricity respectively
Press signal V7And V8, NMOS tube M301With PMOS M302Drain electrode all pass through the 3rd electric capacity C3Ground connection；NMOS tube M303And PMOS
M304Constitute transmission gate TG2, NMOS tube M303With PMOS M304Grid connect voltage signal V respectively8And V7, NMOS tube M303With
PMOS M304Drain electrode all connect sawtooth signal V5Or V6, NMOS tube M303With PMOS M304Source electrode all pass through the 3rd electric capacity
C3Ground connection；NMOS tube M305With PMOS M306Constitute transmission gate TG3, NMOS tube M305With PMOS M306Grid connect electricity respectively
Press signal V8And V7, NMOS tube M305With PMOS M306Drain electrode all pass through the 4th electric capacity C4Ground connection；NMOS tube M307And PMOS
M308Constitute transmission gate TG4, NMOS tube M307With PMOS M308Grid connect voltage signal V respectively7And V8, NMOS tube M307With
PMOS M308Drain electrode all connect sawtooth signal V5Or V6, NMOS tube M307With PMOS M308Source electrode all pass through the 4th electric capacity
C4Ground connection；
The current source IR3Positive pole connection internal electric source VDD, negative pole connection sawtooth signal V5Or V6。
5. a kind of DC-DC pierce circuits of dual output, it is characterised in that：Inside including that can produce constant clock signal shakes
Unit is swung, the burst pulse of circuit structure identical first that clock signal can be converted into the narrow pulse signal of fixed pulse width is produced
Unit and the second burst pulse generation unit, and narrow pulse signal can be converted into the circuit structure identical of sawtooth signal
First sawtooth waveforms generation unit and the second sawtooth waveforms generation unit；
The internal oscillator unit connects the first burst pulse generation unit and the second burst pulse generation unit, internal oscillator list respectively
Member connection reference voltage VR1 and enable signal EN, internal oscillator unit export to the first burst pulse generation unit it is constant when
Clock signal is 180 degree, respectively V1 and V2 with the phase difference exported to the constant clock signal of the second burst pulse generation unit；
The output end of first burst pulse generation unit and the second burst pulse generation unit exports narrow pulse signal V3 and V4 respectively, and first is narrow
The output end of impulse generating unit and the second burst pulse generation unit is also respectively connected with the first sawtooth waveforms generation unit and the second saw
The input of tooth ripple generation unit；
The first sawtooth waveforms generation unit and the second sawtooth waveforms generation unit connect reference voltage VR2, enable signal EN and defeated
Enter voltage VIN, the output end of the first sawtooth waveforms generation unit and the second sawtooth waveforms generation unit exports sawtooth signal V5 respectively
Phase difference with sawtooth signal V6, sawtooth signal V5 and sawtooth signal V6 is 180 degree；
The internal oscillator unit has first input end a, the second input b, the first output end c and the second output end d, wherein
First input end a and the second input b connect reference voltage VR1 and enable signal EN, the first output end c and the second output respectively
Hold d difference output voltages V1 and V2；
The first burst pulse generation unit have an input e and an Ausgang, wherein input e input voltages V1,
Its Ausgang output narrow pulse signal V3；Second burst pulse generation unit has an an input n and output end o, wherein
Input n input voltage V2, its output end o output narrow pulse signal V4；
The first sawtooth waveforms generation unit has first input end g, the second input h, the 3rd input j, the 4th input k
With an output end m, wherein the first burst pulse of first input end g connections generation unit output narrow pulse signal V3, second is defeated
Enter to hold h connection reference voltages VR2, the 3rd input j connections enable signal EN, and the 4th input k connection input voltage VINs are defeated
Go out to hold m to export sawtooth signal V5；
The second sawtooth waveforms generation unit has first input end p, the second input q, the 3rd input r, the 4th input s
With an output end t, wherein the second burst pulse of first input end p connections generation unit output narrow pulse signal V4, second is defeated
Enter to hold q connection reference voltages VIN, the 3rd input r connections enable signal EN, the 4th input s connections input voltage VR2 is defeated
Go out to hold t to export sawtooth signal V6；
An output narrow pulse signal V3 parts for the first burst pulse generation unit are transferred to the first sawtooth waveforms generation unit
First input end g, another part is passed as output signal, an output narrow pulse signal V4 parts for the second burst pulse generation unit
The first input end p of the second sawtooth waveforms generation unit is defeated by, another part is used as output signal；
The circuit structure of the first burst pulse generation unit and the second burst pulse generation unit is identical, is triggered including the first D
It is device (201), the 5th phase inverter (202), hex inverter (203), NAND gate (204), the 8th phase inverter (205), the tenth anti-phase
Device (206), the 7th electric capacity C7；
The input end of clock CLK of first d type flip flop (201) meets V1 or V2, and its input D connects the input of the tenth phase inverter (206)
End, while connecting its an output end XQ, the output end XQ of the first d type flip flop (201) connects the input of hex inverter (203)
End, reset terminal RST connects the output end of the 8th phase inverter (205), and another output end Q connects the input of the 5th phase inverter (202)；
The output end of 5th phase inverter (202) connects output the narrow pulse signal V3 or V4 of the unit；
The output end of the hex inverter (203) is grounded by the 7th electric capacity C7, while connect NAND gate (204) one is defeated
Enter end；
The output end of the input connection NAND gate (204) of 8th phase inverter (205)；
Another input of the output end connection NAND gate (204) of tenth phase inverter (206).
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| US11799463B2 (en) | 2020-08-14 | 2023-10-24 | Samsung Electronics Co., Ltd. | Duty adjustment circuit, and delay locked loop circuit and semiconductor memory device including the same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US11799463B2 (en) | 2020-08-14 | 2023-10-24 | Samsung Electronics Co., Ltd. | Duty adjustment circuit, and delay locked loop circuit and semiconductor memory device including the same |
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| CN104578756A (en) | 2015-04-29 |
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