CN205787773U

CN205787773U - The data transmission system controlled in real time based on FPGA and ARM

Info

Publication number: CN205787773U
Application number: CN201620658672.6U
Authority: CN
Inventors: 李培乐; 徐汉超; 吴剑锋
Original assignee: Suzhou Hulk System Detects Technology Co Ltd
Current assignee: Suzhou Hulk System Detects Technology Co Ltd
Priority date: 2016-06-28
Filing date: 2016-06-28
Publication date: 2016-12-07
Anticipated expiration: 2026-06-28

Abstract

This utility model provides a kind of data transmission system controlled in real time based on FPGA and ARM, at least includes: power module, I/O control module, FPGA module, ARM control module and host computer；Described FPGA module includes that FPGA processor, off-chip cache module and clock control module, described I/O control module, off-chip cache module are connected with FPGA processor respectively with clock control module；Described ARM control module includes ARM controller and the memorizer being connected with described ARM controller；Described ARM controller is connected with FPGA processor, host computer；Power module is all connected with described I/O control module, FPGA processor and ARM controller.This data transmission system controlled in real time based on FPGA with ARM can complete measured data undistorted, real-time, at a distance with the communicating of host computer, and the control instruction of host computer can be received, it is achieved the remote interaction of duty.

Description

The data transmission system controlled in real time based on FPGA and ARM

Technical field

This utility model relates to a kind of data transmission system, particularly relates to a kind of control in real time based on FPGA and ARM Data transmission system.

Background technology

In data transmission procedure, transmission range is distant, or in order to save hardware resource, often uses serial to lead to Letter, thus needs the data Serial output transmitted by host computer to communication interface.Serioparallel exchange is a weight of FPGA design Wanting skill, it is the conventional means of Data Stream Processing, is also that area exchanges directly embodying of thought with speed.The reality of serioparallel exchange Existing method is varied, according to sequence and the requirement of quantity of data, can select shift register, RAM, SRAM, SDRAM etc. Realize.

In the industry, sometimes system under test (SUT) and host computer have a certain distance, if directly the parallel data measured It is sent to host computer, it will decay and the signal lag problem of data signal occur, it is possible to make signal sequence misplace, thus reach Requirement less than system test.For this reason, it may be necessary to develop the data transmission system that a kind of high speed is real-time, be used for measured data without Distortion, real-time, the remote and communication of host computer, and the control instruction of host computer can be received, it is achieved duty remote Journey is mutual.

Utility model content

The shortcoming of prior art in view of the above, the purpose of this utility model is to provide a kind of based on FPGA and ARM The data transmission system controlled in real time, is used for solving the above-mentioned problems in the prior art.

For achieving the above object and other relevant purposes, this utility model provides following technical scheme:

A kind of data transmission system controlled in real time based on FPGA and ARM, at least includes: power module, I/O control module, FPGA module, ARM control module and host computer；Described FPGA module include FPGA processor, off-chip cache module and time clock Molding block, described I/O control module, off-chip cache module are connected with described FPGA processor respectively with clock control module； Described ARM control module includes ARM controller and the memorizer being connected with described ARM controller；Described ARM controller and FPGA Processor, host computer are connected；Power module is all connected with described I/O control module, FPGA processor and ARM controller.

Preferably, described power module includes that LDO power supply and DCDC power supply, described LDO power supply are connected with FPGA processor； Described DCDC power supply is all connected with described I/O control module and ARM controller.

Preferably, the output voltage of described DCDC power supply is 3.3V.

Preferably, the output voltage of described LDO power supply has 1.2V and 2.5V.

Preferably, real-time for data high-speed is transferred to described host computer by Ethernet interface by described ARM controller.

As it has been described above, the data transmission system controlled in real time based on FPGA and ARM of the present utility model, have following useful Effect:

1) can complete that measured data is undistorted, real-time, the remote and communication of host computer, and host computer can be received Control instruction, it is achieved the remote interaction of duty.

2) speed is fast, low in energy consumption, reliability is high, integrated level is high, pin resource is abundant, clock frequency is high, programmed configurations is clever Live, to be prone to reconstruct, construction cycle short, and design cost is low.

Accompanying drawing explanation

Fig. 1 is shown as the data transmission system schematic diagram controlled in real time based on FPGA and ARM of the present utility model.

Element numbers explanation

1	Power module
		2	I/O control module
3	FPGA processor
		4	Off-chip cache module
5	Clock control module
		6	ARM controller
7	Memorizer
		8	Host computer

Detailed description of the invention

By particular specific embodiment, embodiment of the present utility model being described below, those skilled in the art can be by this Content disclosed by description understands other advantages of the present utility model and effect easily.

Refer to Fig. 1.It should be clear that structure depicted in this specification institute accompanying drawings, ratio, size etc., the most only in order to coordinate Content disclosed in description, understands for those skilled in the art and reads, and being not limited to this utility model can be real The qualifications executed, therefore do not have technical essential meaning, the modification of any structure, the change of proportionate relationship or the tune of size Whole, under not affecting effect that this utility model can be generated by and the purpose that can reach, all should still fall in this utility model institute In the range of the technology contents disclosed can be contained.Meanwhile, in this specification cited as " on ", D score, "left", "right", The term of " middle " and " one " etc., is merely convenient to understanding of narration, and is not used to limit the enforceable scope of this utility model, Being altered or modified of its relativeness, is changing under technology contents without essence, when being also considered as the enforceable category of this utility model.

As it is shown in figure 1, this utility model provides a kind of data transmission system controlled in real time based on FPGA and ARM, at least Including: power module 1, I/O control module 2, FPGA module, ARM control module and host computer 8；Described I/O control module 2, FPGA module is connected with described power module 1 respectively with ARM control module；Described I/O control module 2, FPGA module, ARM Control module and host computer 8 are sequentially connected.Wherein FPGA module is as data pre-processor, completes parallel data to serial data The data prediction task such as conversion；ARM control module, as central processing controller, mainly completes from FPGA processor 3 Read the most preprocessed good data, and complete the real-time Communication for Power task with host computer 8 by Ethernet interface.Described host computer 8 Demodulate all kinds of physical descriptor according to Data Transport Protocol, record and store.Tester completes duty by host computer 8 Remotely control and various information interactive tasks.

With reference to Fig. 1, described FPGA module includes FPGA processor 3, off-chip cache module 4 and clock control module 5, described I/O control module 2, off-chip cache module 4 and clock control module 5 be connected with described FPGA processor 3 respectively；Described ARM Control module includes ARM controller 6 and the memorizer 7 being connected with described ARM controller 6；At described ARM controller 6 and FPGA Reason device 3, host computer 8 are connected；Preferably, real-time for data high-speed is transferred to institute by Ethernet interface by described ARM controller 6 State host computer 8.Described power module 1 is all connected with described I/O control module 2, FPGA processor 3 and ARM controller 6.

With reference to Fig. 1, described power module 1 includes LDO power supply and DCDC power supply, described LDO power supply and FPGA processor 3 phase Even；Described DCDC power supply is all connected with described I/O control module 2 and ARM controller 6.

The output voltage of described DCDC power supply is 3.3V.The output voltage of described LDO power supply has 1.2V and 2.5V.

Described off-chip cache module 4 includes SRAM and SDRMM.

It is undistorted that the data transmission system controlled in real time based on FPGA and ARM of the present utility model can complete measured data , real-time, the remote and communication of host computer 8, and the control instruction of host computer 8 can be received, it is achieved duty long-range Alternately.It addition, the data transmission system speed originally controlled in real time based on FPGA and ARM is fast, low in energy consumption, reliability is high, integrated level High, pin resource abundant, clock frequency high, programmed configurations flexibly, to be prone to reconstruct, construction cycle short, and design cost is low.

Above-described embodiment only illustrative principle of the present utility model and effect thereof are new not for limiting this practicality Type.Above-described embodiment all can be carried out by any person skilled in the art under spirit and the scope of the present utility model Modify or change.Therefore, all art have usually intellectual without departing from the spirit disclosed in this utility model Modify with all equivalences completed under technological thought or change, must be contained by claim of the present utility model.

Claims

1. the data transmission system controlled in real time based on FPGA and ARM, it is characterised in that at least include: power module (1), I/O control module (2), FPGA module, ARM control module and host computer (8)；Described FPGA module includes FPGA processor (3), off-chip cache module (4) and clock control module (5), described I/O control module (2), off-chip cache module (4) and time Clock control module (5) is connected with described FPGA processor (3) respectively；Described ARM control module include ARM controller (6) and The memorizer (7) being connected with described ARM controller (6)；Described ARM controller (6) and FPGA processor (3), host computer (8) phase Even；Power module (1) is all connected with described I/O control module (2), FPGA processor (3) and ARM controller (6).

The data transmission system controlled in real time based on FPGA and ARM the most according to claim 1, it is characterised in that: described Power module (1) includes that LDO power supply and DCDC power supply, described LDO power supply are connected with FPGA processor (3)；Described DCDC power supply All it is connected with described I/O control module (2) and ARM controller (6).

The data transmission system controlled in real time based on FPGA and ARM the most according to claim 2, it is characterised in that: described The output voltage of DCDC power supply is 3.3V.

The data transmission system controlled in real time based on FPGA and ARM the most according to claim 2, it is characterised in that: described The output voltage of LDO power supply has 1.2V and 2.5V.