CN205752160U - A kind of capacitor - Google Patents
A kind of capacitor Download PDFInfo
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- CN205752160U CN205752160U CN201620595840.1U CN201620595840U CN205752160U CN 205752160 U CN205752160 U CN 205752160U CN 201620595840 U CN201620595840 U CN 201620595840U CN 205752160 U CN205752160 U CN 205752160U
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Abstract
The utility model discloses a kind of capacitor, solve and reduce, by the size changing single electric capacity, the method that the difference rate of lead capacitance promotes electric capacity matching precision at present, the problem that IC design is limited, described capacitor are included: along the first electric capacity (C1) and second electric capacity (C2) of the arrangement of axle (a) crossed-symmetrical；First electric capacity (C1) includes 2N+1 the first sub-electric capacity (C11～C1i) being sequentially connected with by first group of metal connecting line (L1), and the second electric capacity (C2) includes 2N+1 the second sub-electric capacity (C21～C2i) being sequentially connected with by second group of metal connecting line (L2)；Wherein, N be positive integer, i be 2N+1；The difference rate of the capacitance sum of sub-electric capacity (C11～C1i) and sub-electric capacity (C21～C2i) is not more than the first preset value, and the difference rate of the parasitic capacitance of first group of metal connecting line (L1) and second group of metal connecting line (L2) is not more than the second preset value.Achieve on the premise of without changing the size of single electric capacity, promote the effect of electric capacity matching precision.
Description
Technical field
This utility model relates to IC Layout technical field, particularly relates to a kind of capacitor.
Background technology
In the manufacture process of integrated circuit, metal, electrolyte and other materials are used such as physical vapour deposition (PVD), chemistry
Vapour deposition is produced on the surface of silicon chip in interior various methods, forms the metal interconnecting wires including between electronic component and element
Structured metal layer, between each layer of structured metal layer again with multiple metal filled through holes be connected so that circuit has the highest
Complexity and current densities.One important indicator of performance of integrated circuits is path delay, i.e. from one be input to one defeated
Go out the required time；The path delay of integrated circuit includes the Interconnect Delay between device time delay and device.Along with work
The reduction of skill node and the increase of number of devices, the time delay of interconnection line proportion in total time delay is increasing.Interconnection line
Time delay depend mainly on the parasitic parameter of interconnection line, such as resistance, electric capacity, inductance etc., the parasitic parameter of interconnection line is by interconnection line
Material, geological information such as width x length x height etc. and interconnection line between parameter distance, just length etc. is determined.
The precision of Analogous Integrated Electronic Circuits and performance typically depend on device matching and obtain.Generally, matching precision gets over Gao Zemo
Precision and the performance of intending integrated circuit are the best.Path delay is to reflect that the precision of Analogous Integrated Electronic Circuits and a key of performance refer to
Mark, it will usually coupling device is set on the integrated, reduces the path delay of integrated circuit；Wherein, coupling device refers to
Special make on the integrated be located proximate to and difference ratio (i.e. matching precision) is two identical device determining constant.
In these coupling devices, matching capacitance is the important coupling device in integrated circuit, but, many mechanism are (such as doping, oxidation
Layer thickness, process deviation, the imperfect flow of electric current, diffusion influence each other, mechanical stress, thermograde) and many other are former
Systematic error because causing all can increase capacitor mismatch error, and then affects electric capacity coupling.
It is inevitable that these manufacture the objective factor in chip processes, and current designer is by optimizing layout design
Reduce its impact.In view of in actual applications device being connected into the resistance of wire and the electric capacity of circuit, electric capacity can be caused
Joining precision relatively low, even can cause system mismatch, layout design personnel realize wire electricity by the size increasing single electric capacity
Appearance minimizes, but this mode inapplicable all design requirements, reason includes: the increase of capacitor size can affect integrated circuit
Area, the increase of capacitor size make the capacitance of this electric capacity do not meet design require or do not reach high-accuracy capacitor
The design requirement joined.
Sum it up, prior art exists, reduce lead capacitance difference rate by the size changing single electric capacity, from
And the method promoting electric capacity matching precision so that the technical problem that IC design is limited.
Utility model content
This utility model, for present in prior art, reduces lead capacitance by the size changing single electric capacity poor
Value rate, thus the method promoting electric capacity matching precision so that the technical problem that IC design is limited, it is provided that a kind of electric capacity
Device, it is achieved that without promoting electric capacity matching precision on the premise of changing the size of single electric capacity, thus do not interfere with integrated electricity
The area on road, also will not change the capacitance of electric capacity so that IC design will not be imitated by the technology that capacitor size is limited
Really.
This utility model provides a kind of capacitor, including:
First electric capacity of symmetry arrangement and the second electric capacity；
Described first electric capacity includes first group of metal connecting line and 2N+1 the first sub-electric capacity, and described second electric capacity includes second
Group metal connecting line and 2N+1 the second sub-electric capacity；Wherein, N is positive integer, and described 2N+1 the first sub-electric capacity is by described first
Group metal connecting line is sequentially connected with, and described 2N+1 the second sub-electric capacity is sequentially connected with by described second group of metal connecting line；Described 2N+
1 the first sub-electric capacity and described 2N+1 the second sub-electric capacity intersect row along the axis of symmetry of described first electric capacity and described second electric capacity
Cloth；
The capacitance of described 2N+1 the first sub-electric capacity and with the capacitance of described 2N+1 the second sub-electric capacity and difference rate little
In equal to the first preset value, the parasitic capacitance capacitance of described first group of metal connecting line is parasitic electric with described second group of metal connecting line
Hold the difference rate of capacitance less than or equal to the second preset value.
Optionally, in described 2N+1 the first sub-electric capacity, arbitrary first sub-electric capacity is appointed in described 2N+1 the second sub-electric capacity
The parameter of one second sub-electric capacity is the most identical with capacitance.
Optionally, described 2N+1 the first sub-electric capacity forms 2N+1 son with described 2N+1 the second sub-electric capacity one_to_one corresponding
Electric capacity pair, described 2N+1 sub-electric capacity stacks gradually arrangement, so that arbitrary first sub-electric capacity is adjacent to according to setting arrangement mode
Electric capacity is the second sub-electric capacity and arbitrary second sub-electric capacity adjacent capacitor is the first sub-electric capacity.
Optionally, two sub-electric capacity of described 2N+1 sub-electric capacity centering arbitrary neighborhood between open circuit, described 2N+1
Open circuit between the arbitrary sub-electric capacity of sub-electric capacity centering the first sub-electric capacity and the second sub-electric capacity to being comprised.
Optionally, described first group of metal connecting line includes that 2N bar the first metal connecting line, described second group of metal connecting line include
2N bar the second metal connecting line；Wherein, described 2N bar the first metal connecting line at least exists two metal connecting lines and uses different layers
, at least there are two metal connecting lines in described 2N bar the second metal connecting line and use the metal of different layers in metal.
The one or more technical schemes provided in this utility model, at least have the following technical effect that or advantage:
Owing to, in this utility model, capacitor includes the first electric capacity and second electric capacity of symmetry arrangement；Described first electricity
Holding and include first group of metal connecting line and 2N+1 the first sub-electric capacity, described second electric capacity includes that second group of metal connecting line and 2N+1 are individual
Second sub-electric capacity；Wherein, N is positive integer, and described 2N+1 the first sub-electric capacity is sequentially connected with by described first group of metal connecting line,
Described 2N+1 the second sub-electric capacity is sequentially connected with by described second group of metal connecting line；Described 2N+1 the first sub-electric capacity is with described
2N+1 the second sub-electric capacity is along described first electric capacity and the axis of symmetry cross arrangement of described second electric capacity；At above-mentioned capacitance structure
On the basis of, capacitance and the capacitance of described 2N+1 the second sub-electric capacity of described 2N+1 the first sub-electric capacity are set, so that described 2N+
The capacitance of 1 the first sub-electric capacity and with the capacitance of described 2N+1 the second sub-electric capacity and difference rate preset less than or equal to first
Value, and rationally selects and arranges first group of metal connecting line and second group of metal connecting line, so that the posting of described first group of metal connecting line
Raw capacitor's capacity is less than or equal to the second preset value with the difference rate of the parasitic capacitance capacitance of described second group of metal connecting line, to realize
Without promoting electric capacity matching precision on the premise of changing the size of single electric capacity, thus do not interfere with integrated circuit area,
Also the capacitance of electric capacity will not be changed so that the technique effect that IC design will not be limited by capacitor size.Effectively
Solve prior art reduces lead capacitance difference rate by the size changing single electric capacity, thus promote electric capacity matching precision
Method so that the technical problem that IC design is limited.
Accompanying drawing explanation
In order to be illustrated more clearly that this utility model embodiment or technical scheme of the prior art, below will be to embodiment
Or the required accompanying drawing used is briefly described in description of the prior art, it should be apparent that, the accompanying drawing in describing below is only
It is embodiment of the present utility model, for those of ordinary skill in the art, on the premise of not paying creative work, also
Other accompanying drawing can be obtained according to the accompanying drawing provided.
The first capacitor arrangement schematic diagram that Fig. 1 provides for this utility model embodiment；
The second capacitor arrangement schematic diagram that Fig. 2 provides for this utility model embodiment；
The laying out pattern method flow diagram of a kind of capacitor that Fig. 3 provides for this utility model embodiment.
Detailed description of the invention
This utility model embodiment, by providing a kind of capacitor, solves present in prior art, single by changing
The size of individual electric capacity reduces lead capacitance difference rate, thus the method promoting electric capacity matching precision so that IC design
Limited technical problem, it is achieved that without promoting electric capacity matching precision on the premise of changing the size of single electric capacity, thus not
The area of integrated circuit can be affected, also will not change the capacitance of electric capacity so that IC design will not be by capacitor size
The technique effect limited.
The technical scheme of this utility model embodiment is for solving above-mentioned technical problem, and general thought is as follows:
This utility model embodiment provides a kind of capacitor, including: the first electric capacity of symmetry arrangement and the second electric capacity；Institute
Stating the first electric capacity and include first group of metal connecting line and 2N+1 the first sub-electric capacity, described second electric capacity includes second group of metal connecting line
With 2N+1 the second sub-electric capacity；Wherein, N is positive integer, and described 2N+1 the first sub-electric capacity is by described first group of metal connecting line
Being sequentially connected with, described 2N+1 the second sub-electric capacity is sequentially connected with by described second group of metal connecting line；Described 2N+1 first son
Electric capacity and described 2N+1 the second sub-electric capacity are along described first electric capacity and the axis of symmetry cross arrangement of described second electric capacity；Described 2N
The capacitance of+1 the first sub-electric capacity and with the capacitance of described 2N+1 the second sub-electric capacity and difference rate preset less than or equal to first
The difference rate of the parasitic capacitance capacitance of value, the parasitic capacitance capacitance of described first group of metal connecting line and described second group of metal connecting line
Less than or equal to the second preset value.
Visible, in this utility model embodiment, by two electric capacity (the i.e. first electric capacity by needing coupling in capacitor
With the second electric capacity) it is respectively divided into sub-electric capacity (i.e. 2N+1 the first sub-electric capacity and 2N that the odd number stacking more than or equal to 3 is arranged
+ 1 the second sub-electric capacity), and by first group of metal connecting line, described 2N+1 the first sub-electric capacity is sequentially connected with, and by the
Described 2N+1 the second sub-electric capacity is sequentially connected with by two groups of metal connecting lines, and makes described 2N+1 the first sub-electric capacity and described 2N+1
Individual second sub-electric capacity is along described first electric capacity and the axis of symmetry cross arrangement of described second electric capacity；Then, at above-mentioned capacitance structure
On the basis of, capacitance and the capacitance of described 2N+1 the second sub-electric capacity of described 2N+1 the first sub-electric capacity are set, so that described 2N+
The capacitance of 1 the first sub-electric capacity and with the capacitance of described 2N+1 the second sub-electric capacity and difference rate preset less than or equal to first
Value, and rationally selects and arranges first group of metal connecting line and second group of metal connecting line, so that the posting of described first group of metal connecting line
Raw capacitor's capacity is less than or equal to the second preset value with the difference rate of the parasitic capacitance capacitance of described second group of metal connecting line, to realize
Without promoting electric capacity matching precision on the premise of changing the size of single electric capacity, thus do not interfere with integrated circuit area,
Also the capacitance of electric capacity will not be changed so that the technique effect that IC design will not be limited by capacitor size.Effectively
Solve prior art reduces lead capacitance difference rate by the size changing single electric capacity, thus promote electric capacity matching precision
Method so that the technical problem that IC design is limited.
In order to be better understood from technique scheme, below in conjunction with Figure of description and specific embodiment to upper
State technical scheme to be described in detail, it should be understood that the specific features in this utility model embodiment and embodiment is to this
The detailed description of application technical scheme rather than the restriction to technical scheme, in the case of not conflicting, this practicality
Technical characteristic in new embodiment and embodiment can be mutually combined.
Embodiment one
Refer to Fig. 1, this utility model embodiment provides a kind of capacitor 1, including:
The first electric capacity C1 and the second electric capacity C2 of symmetry arrangement；
First electric capacity C1 includes first group of metal connecting line L1 and 2N+1 the first sub-electric capacity (C11～C1i), the second electric capacity C2
Including second group of metal connecting line L2 and 2N+1 the second sub-electric capacity (C21～C2i)；Wherein, N is positive integer, and i is equal to 2N+1,2N+
1 the first sub-electric capacity (C11～C1i) is sequentially connected with by first group of metal connecting line L1,2N+1 the second sub-electric capacity (C21～
C2i) it is sequentially connected with by second group of metal connecting line L2；2N+1 the first sub-electric capacity (C11～C1i) and 2N+1 the second sub-electric capacity
(C21～C2i) is along the axis of symmetry a cross arrangement of the first electric capacity C1 and the second electric capacity C2；
The capacitance of 2N+1 the first sub-electric capacity (C11～C1i) and the capacitance of second sub-electric capacity (C21～C2i) individual with 2N+1
The difference rate of sum is less than or equal to the first preset value, the parasitic capacitance capacitance of first group of metal connecting line L1 and second group of metal connecting line L2
The difference rate of parasitic capacitance capacitance less than or equal to the second preset value.
In specific implementation process, in order to improve the first electric capacity C1 and the coupling ratio of the second electric capacity C2,2N+1 first
In sub-electric capacity (C11～C1i), the parameter of the sub-electric capacity of any two first is the most identical with capacitance, 2N+1 the second sub-electric capacity (C21～
C2i) in, the parameter of the sub-electric capacity of any two second is the most identical with capacitance, and appoints in 2N+1 the first sub-electric capacity (C11～C1i)
One first sub-electric capacity is the most identical with parameter and the capacitance of arbitrary second sub-electric capacity in 2N+1 the second sub-electric capacity (C21～C2i).So
And, in actual applications, due to inevitable fabrication error, the sub-electric capacity of any two first, the sub-electric capacity of any two second
Or arbitrary first sub-electric capacity cannot be identical with arbitrary second sub-electric capacity, there will necessarily be little bit different, in the present embodiment,
Need to ensure 2N+1 the first sub-electric capacity (C11～C1i) capacitance and with the capacitance of 2N+1 the second sub-electric capacity (C21～C2i) and
Difference rate less than or equal to the first preset value.Concrete, set 2N+1 the first sub-electric capacity (C11～C1i) and 2N+1 individual second
The capacitance of sub-electric capacity (C21～C2i) and respectively X1, Y1, set described difference rate and exist such as following formula as P1, P1 and X1, Y1
(1) mathematical relationship:
P1=| X1-Y1 |/((X1+Y1)/2) (1)
It addition, introduce resistance and the electric capacity of circuit in actual applications for reducing wire, to improve the first electric capacity further
C1 and the coupling ratio of the second electric capacity C2, the parasitic capacitance capacitance of first group of metal connecting line L1 and posting of second group of metal connecting line L2
The difference rate of raw capacitor's capacity is less than or equal to the second preset value.Concrete, the parasitic capacitance setting first group of metal connecting line L1 is held
The parasitic capacitance capacitance of value and second group of metal connecting line L2 is respectively X2, Y2, sets described difference rate and deposits as P2, P2 and X2, Y2
Such as the mathematical relationship of following formula (2):
P2=| X2-Y2 |/((X2+Y2)/2) (2)
In the present embodiment, described first preset value can value be 0.1%, and described second preset value can value be
0.08%.It should be noted that in specific implementation process, described first preset value and described second preset value can be according to specifically
Depending on design requires, it is not especially limited here.
The parasitic capacitance capacitance introduced with line owing to the actual capacitance of electric capacity is the capacitance of electric capacity own and, i.e. first is electric
Hold the capacitance that actual capacitance is 2N+1 the first sub-electric capacity (C11～C1i) of C1 and add the parasitism of first group of metal connecting line L1
Capacitor's capacity, the actual capacitance of the second electric capacity C2 are the capacitance of 2N+1 the second sub-electric capacity (C21～C2i) and add second group of gold
Belong to the parasitic capacitance capacitance of line L2, when described 2N+1 the first sub-electric capacity (C11～C1i) capacitance and with described 2N+1 the
The difference rate of the capacitance sum of two sub-electric capacity (C21～C2i) is less than or equal to the first preset value, and described first group of metal connecting line L1
When the difference rate of the parasitic capacitance capacitance of parasitic capacitance capacitance and described second group of metal connecting line L2 is less than or equal to the second preset value,
The matching precision of the first electric capacity C1 and the second electric capacity C2 is better than ± 0.1%.
In specific implementation process, referring still to Fig. 1, described 2N+1 the first sub-electric capacity (C11～C1i) and described 2N+1
Individual second sub-electric capacity (C21～C2i) one_to_one corresponding forms 2N+1 sub-electric capacity pair, and described 2N+1 sub-electric capacity is to according to the row of setting
Mode for cloth stacks gradually arrangement, so that arbitrary first sub-electric capacity adjacent capacitor is the second sub-electric capacity and arbitrary second sub-electric capacity phase
Adjacent electric capacity is the first sub-electric capacity.Concrete, the 1st the first sub-electric capacity C11 and the 1st the second sub-electric capacity C21 is correspondingly formed the 1st
Sub-electric capacity pair, and the 1st the first sub-electric capacity C11 and the 1st the second sub-electric capacity C21 is symmetrical about axis of symmetry a；2nd first son
Electric capacity C12 and the 2nd the second sub-electric capacity C22 is correspondingly formed the 2nd sub-electric capacity pair, and the 2nd the first sub-electric capacity C12 and the 2nd
Second sub-electric capacity C22 is symmetrical about axis of symmetry a；...；2N+1 the first sub-electric capacity C1i and 2N+1 the second sub-electric capacity C2i
It is correspondingly formed 2N+1 sub-electric capacity pair, and 2N+1 the first sub-electric capacity C1i and 2N+1 the second sub-electric capacity C2i is about right
Claim axle a symmetrical.Described 2N+1 sub-electric capacity stacks gradually arrangement to according to setting arrangement mode, the first sub-electric capacity of odd-numbered
And the second sub-electric capacity of even-numbered is arranged in the side of axis of symmetry a, the first sub-electric capacity and odd-numbered of even-numbered
The second sub-electric capacity be arranged in the opposite side of axis of symmetry a so that described 2N+1 the first sub-electric capacity (C11～C1i) and described 2N+
1 the second sub-electric capacity (C21～C2i) is along the axis of symmetry a cross arrangement of the first electric capacity C1 and the second electric capacity C2.
Further, for avoiding the first electric capacity C1 and the second electric capacity C2 short circuit, in specific implementation process, described 2N+1 son
Two sub-electric capacity of electric capacity centering arbitrary neighborhood between open circuit, described 2N+1 the arbitrary sub-electric capacity of sub-electric capacity centering is to being comprised
The first sub-electric capacity and the second sub-electric capacity between open circuit.Such as, described 1st sub-electric capacity is to (by the 1st the first sub-electric capacity C11
Be correspondingly formed with the 1st the second sub-electric capacity C21) with described 2nd sub-electric capacity to (by the 2nd the first sub-electric capacity C12 and the 2nd
Second sub-electric capacity C22 is correspondingly formed) open circuit, and the 1st the first sub-electric capacity C11 and the 1st the second sub-electric capacity C21 open circuit, the 2nd
First sub-electric capacity C12 and the 2nd the second sub-electric capacity C22 open circuit；...；Described 2N sub-electric capacity is to (by 2N first son electricity
Hold and be correspondingly formed with 2N the second sub-electric capacity) with described 2N+1 sub-electric capacity to (by 2N+1 the first sub-electric capacity and the
2N+1 the second sub-electric capacity is correspondingly formed) open circuit, and 2N the first sub-electric capacity second sub-electric capacity open circuit individual with 2N, 2N+1
Individual first sub-electric capacity and 2N+1 the second sub-electric capacity open circuit.
In specific implementation process, first group of metal connecting line L1 includes 2N bar the first metal connecting line, second group of metal connecting line
L2 includes 2N bar the second metal connecting line；Wherein, any bar the first metal connecting line and the shape size of any bar the second metal connecting line
Identical, described 2N bar the first metal connecting line at least exists two metal connecting lines and uses the metal of different layers, described 2N bar
Second metal connecting line at least exists two metal connecting lines and uses the metal of different layers, use the metal connecting line of different layers metal
Unit-area capacitance capacitance is different.Concrete, referring still to 2N bar the first metal connecting line bag of Fig. 1, first group of metal connecting line L1
Include: connect the 1st the first sub-electric capacity C11 and the metal connecting line L11 of the 2nd the first sub-electric capacity C12, connect the 2nd first son electricity
Hold C12 and the metal connecting line L12 of the 3rd the first sub-electric capacity C13 ..., connect 2N the first sub-electric capacity (being not drawn in Fig. 1)
Metal connecting line (being not drawn in Fig. 1) with 2N+1 the first sub-electric capacity (being not drawn in Fig. 1)；Same, second group of metal is even
2N article of second metal connecting line of line L2 includes: connect the metal of the 1st the second sub-electric capacity C21 and the 2nd the second sub-electric capacity C22 even
Line L21, connects the 2nd the second sub-electric capacity C22 and the metal connecting line L22 of the 3rd the second sub-electric capacity C23 ..., connect 2N
The metal connecting line of the second sub-electric capacity (being not drawn in Fig. 1) and 2N+1 the second sub-electric capacity (being not drawn in Fig. 1) (is not drawn in Fig. 1
Go out).
Below as a example by N value is 1, refer to Fig. 2, the first electric capacity C1 and the second electric capacity C2 all comprises three straton electric capacity,
Concrete, the first electric capacity C1 includes three the first sub-electric capacity (C11, C12, C13) that stacking is arranged, and the second electric capacity C2 includes stacking
Three the second sub-electric capacity (C21, C22, C23) arranged, three the first sub-electric capacity (C11, C12, C13) and three the second sub-electric capacity
The parameter of (C21, C22, C23) is the most identical with capacitance, to ensure the capacitance of the first electric capacity C1 own and the of the second electric capacity C2 own
The difference rate of capacitance is less than or equal to described first preset value.
Referring still to Fig. 2, the upper left corner A2 of the lower right corner A1 and the first sub-electric capacity C12 of the first sub-electric capacity C11 passes through metal
Line L11 connects, and the upper right corner A4 of the lower left corner A3 and the first sub-electric capacity C13 of the first sub-electric capacity C12 is by metal connecting line L12 even
Connecing, the upper right corner B2 of the lower left corner B1 and the second sub-electric capacity C22 of the second sub-electric capacity C21 is connected by metal connecting line L21, the second son
The upper left corner B4 of the lower right corner B3 of electric capacity C22 and the second sub-electric capacity C23 is connected by metal connecting line L22.For avoiding the first electric capacity
C1 and the second electric capacity C2 short circuit, metal connecting line L11 and metal connecting line L21 is the metal of different layers, and metal connecting line L12 is with metal even
Line L22 is the metal of different layers.It addition, metal connecting line L11 and metal connecting line L22 belongs to similar layer or with layer metal, i.e. metal
The parasitic capacitance capacitance of line L11 and metal connecting line L22 is essentially identical, and metal connecting line L12 belongs to similar layer with metal connecting line L21
Or parasitic capacitance capacitance with layer metal, i.e. metal connecting line L12 and metal connecting line L21 is essentially identical, to ensure the first electric capacity C1
The difference of the parasitic capacitance capacitance that the introduced parasitic capacitance capacitance of middle metal connecting line is introduced with metal connecting line in the second electric capacity C2
Value rate is less than or equal to described second preset value.
Sum it up, in this utility model embodiment, by two electric capacity (i.e. first by needing coupling in capacitor
Electric capacity and the second electric capacity) it is respectively divided into sub-electric capacity (i.e. 2N+1 the first sub-electric capacity that the odd number stacking more than or equal to 3 is arranged
With 2N+1 the second sub-electric capacity), and by first group of metal connecting line, described 2N+1 the first sub-electric capacity is sequentially connected with, Yi Jitong
Cross second group of metal connecting line to be sequentially connected with by described 2N+1 the second sub-electric capacity, and make described 2N+1 the first sub-electric capacity with described
2N+1 the second sub-electric capacity is along described first electric capacity and the axis of symmetry cross arrangement of described second electric capacity；Then, at above-mentioned electric capacity
On architecture basics, capacitance and the capacitance of described 2N+1 the second sub-electric capacity of described 2N+1 the first sub-electric capacity is set, so that institute
State 2N+1 the first sub-electric capacity capacitance and with the capacitance of described 2N+1 the second sub-electric capacity and difference rate less than or equal to first
Preset value, and rationally select and arrange first group of metal connecting line and second group of metal connecting line, so that described first group of metal connecting line
The difference rate of parasitic capacitance capacitance of parasitic capacitance capacitance and described second group of metal connecting line less than or equal to the second preset value, with
Realize without promoting electric capacity matching precision on the premise of changing the size of single electric capacity, thus do not interfere with the face of integrated circuit
Amass, also will not change the capacitance of electric capacity so that the technique effect that IC design will not be limited by capacitor size.Effectively
Ground solves to reduce lead capacitance difference rate by the size changing single electric capacity in prior art, thus promotes electric capacity coupling essence
The method of degree so that the technical problem that IC design is limited.
Embodiment two
Conceive based on same utility model, refer to Fig. 3, present invention also provides the laying out pattern side of a kind of capacitor
Method, comprises the steps:
S1, respectively stacking arrange 2N+1 the first sub-electric capacity and 2N+1 the second sub-electric capacity, and make described 2N+1 first
Sub-electric capacity and described 2N+1 the second sub-capacitive cross symmetry arrangement, wherein, N is positive integer；
S2, it is sequentially connected with described 2N+1 the first sub-electric capacity by first group of metal connecting line, to form the first electric capacity；And
It is sequentially connected with described 2N+1 the second sub-electric capacity, to form the second electric capacity by second group of metal connecting line；Wherein, described 2N+1
The capacitance of the first sub-electric capacity and with the capacitance of described 2N+1 the second sub-electric capacity and difference rate less than or equal to the first preset value, institute
The difference rate of the parasitic capacitance capacitance and the parasitic capacitance capacitance of described second group of metal connecting line of stating first group of metal connecting line is less than
Equal to the second preset value.
Wherein, in described 2N+1 the first sub-electric capacity, arbitrary first sub-electric capacity is arbitrary with described 2N+1 the second sub-electric capacity
The parameter of the second sub-electric capacity is the most identical with capacitance.
In specific implementation process, described 2N+1 the first sub-electric capacity and described 2N+1 the second sub-electric capacity one_to_one corresponding shape
2N+1 sub-electric capacity pair, described 2N+1 sub-electric capacity is become to stack gradually arrangement to according to setting arrangement mode, so that arbitrary first
Sub-electric capacity adjacent capacitor is the second sub-electric capacity and arbitrary second sub-electric capacity adjacent capacitor is the first sub-electric capacity.
Further, two sub-electric capacity of described 2N+1 sub-electric capacity centering arbitrary neighborhood between open circuit, described 2N+1
Open circuit between the arbitrary sub-electric capacity of sub-electric capacity centering the first sub-electric capacity and the second sub-electric capacity to being comprised.
In specific implementation process, described first group of metal connecting line includes 2N bar the first metal connecting line, described second group of gold
Belong to line and include 2N bar the second metal connecting line；Wherein, at least there are two metal connecting lines in described 2N bar the first metal connecting line to adopt
With the metal of different layers, described 2N bar the second metal connecting line at least exists two metal connecting lines and uses the metal of different layers.
As described above, above-mentioned laying out pattern method is used for generating above-mentioned capacitor, so, this laying out pattern method
Consistent with one or more embodiments of above-mentioned capacitor, repeat the most one by one at this.
Although having been described for preferred embodiment of the present utility model, but those skilled in the art once knowing substantially
Creative concept, then can make other change and amendment to these embodiments.So, claims are intended to be construed to bag
Include preferred embodiment and fall into all changes and the amendment of this utility model scope.
Obviously, those skilled in the art can carry out various change and modification without deviating from this practicality to this utility model
Novel spirit and scope.So, if of the present utility model these amendment and modification belong to this utility model claim and
Within the scope of its equivalent technologies, then this utility model is also intended to comprise these change and modification.
Claims (5)
1. a capacitor, it is characterised in that including:
First electric capacity (C1) of symmetry arrangement and the second electric capacity (C2)；
Described first electric capacity (C1) includes first group of metal connecting line (L1) and 2N+1 the first sub-electric capacity (C11～C1i), described the
Two electric capacity (C2) include second group of metal connecting line (L2) and 2N+1 the second sub-electric capacity (C21～C2i)；Wherein, N is positive integer, i
It is sequentially connected with by described first group of metal connecting line (L1) for 2N+1, described 2N+1 the first sub-electric capacity (C11～C1i), described
2N+1 the second sub-electric capacity (C21～C2i) is sequentially connected with by described second group of metal connecting line (L2)；Described 2N+1 first son
Electric capacity (C11～C1i) and described 2N+1 the second sub-electric capacity (C21～C2i) are along described first electric capacity (C1) and described second electricity
Hold axis of symmetry (a) cross arrangement of (C2)；
The capacitance of described 2N+1 the first sub-electric capacity (C11～C1i) and with described 2N+1 the second sub-electric capacity (C21～C2i)
The difference rate of capacitance sum is less than or equal to the first preset value, the parasitic capacitance capacitance of described first group of metal connecting line (L1) and described the
The difference rate of the parasitic capacitance capacitance of two groups of metal connecting lines (L2) is less than or equal to the second preset value.
2. capacitor as claimed in claim 1, it is characterised in that arbitrary in described 2N+1 the first sub-electric capacity (C11～C1i)
First sub-electric capacity is the most identical with parameter and the capacitance of arbitrary second sub-electric capacity in described 2N+1 the second sub-electric capacity (C21～C2i).
3. capacitor as claimed in claim 1, it is characterised in that described 2N+1 the first sub-electric capacity (C11～C1i) is with described
2N+1 the second sub-electric capacity (C21～C2i) one_to_one corresponding forms 2N+1 sub-electric capacity pair, and described 2N+1 sub-electric capacity is to according to setting
Determine arrangement mode and stack gradually arrangement, so that arbitrary first sub-electric capacity adjacent capacitor is the second sub-electric capacity and arbitrary second son electricity
Holding adjacent capacitor is the first sub-electric capacity.
4. capacitor as claimed in claim 3, it is characterised in that two sons of described 2N+1 sub-electric capacity centering arbitrary neighborhood
Electric capacity between open circuit, described 2N+1 the arbitrary sub-electric capacity of sub-electric capacity centering the first sub-electric capacity to being comprised and the second sub-electric capacity
Between open circuit.
5. the capacitor as described in claim as arbitrary in Claims 1 to 4, it is characterised in that described first group of metal connecting line (L1) bag
Including 2N bar the first metal connecting line, described second group of metal connecting line (L2) includes 2N bar the second metal connecting line；Wherein, described 2N article
One metal connecting line at least exists two metal connecting lines and uses the metal of different layers, described 2N bar the second metal connecting line is at least deposited
The metal of different layers is used at two metal connecting lines.
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| CN105932015A (en) * | 2016-06-16 | 2016-09-07 | 武汉芯泰科技有限公司 | Capacitor and layout method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105932015A (en) * | 2016-06-16 | 2016-09-07 | 武汉芯泰科技有限公司 | Capacitor and layout method thereof |
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