CN101110417A - Capacitor group structure and method for reducing capacitance variation amount between capacitors - Google Patents
Capacitor group structure and method for reducing capacitance variation amount between capacitors Download PDFInfo
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- CN101110417A CN101110417A CNA2006101061652A CN200610106165A CN101110417A CN 101110417 A CN101110417 A CN 101110417A CN A2006101061652 A CNA2006101061652 A CN A2006101061652A CN 200610106165 A CN200610106165 A CN 200610106165A CN 101110417 A CN101110417 A CN 101110417A
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Abstract
A capacitor module structure comprises at least two capacitors in a same position of a substrate. Wherein, these two capacitors are provided as a first capacitor and a second capacitor. The first capacitor is composed of a plurality of first capacitance units mutually connected in parallel and the second capacitor is composed of a plurality of second capacitance units mutually connected in parallel. In addition, the first and the second capacitance units are staggered and crossed to form an array.
Description
Technical field
The present invention relates to a kind of structure of integrated circuit component, and particularly relate to a kind of structure of capacitor group and the method that reduces the electric capacity amount of variability (capacitance variation) between the capacitor.
Background technology
Capacitor is one of circuit element main in the integrated circuit (integrated circuit).At present, to be used for the capacitor of logic simulation element be metal-insulator-metal (metal-insulator-metal, MIM) capacitor and metal-oxide layer-metal (metal-oxide-metal, MOM) capacitor etc. to industry.Wherein, the technology of MOM capacitor can be integrated with general interconnecting process, and does not need extra photomask; MIM capacitor then needs extra photomask and Patternized technique in manufacturing process, so cost is higher.
Yet, no matter be the influence (for example: the wearing and tearing of machinery equipment, the factors such as consumption of material) that the technology of MIM capacitor or MOM capacitor all can be subjected to some variance factors, the capacitance that causes each capacitor is inconsistent and produce relative variability degree (relative variation), makes product usefulness reduce.Capacitance relative variability degree between the capacitor generally comprises two parts, i.e. part (local) the electric capacity amount of variability of short distance (short-range) and long comprehensive (global) electric capacity amount of variability apart from (long-range).For instance, after the measurement of two capacitors in the same crystalline substance side via capacitance comparison (match), can find its capacitance and inequality, and have so-called not matching (mismatch) problem.For short-range two capacitors, capacitance relative variability degree therebetween is mainly from the localized capacitance amount of variability.
The localized capacitance amount of variability can reduce by increasing capacitor area usually, and its reason is described as follows with Fig. 7, and the capacitance of its illustration short distance inner capacitor is with the variation of position.Among Fig. 7, the localized capacitance amount of variability between a, b two positions is Δ C, and it is the difference of the capacitance of a, b two positions; A, B two interregional localized capacitance amounts of variability are Δ C ', and it is the difference of the condenser paper average in the condenser paper average of a-quadrant and B zone, and Δ C ' is less than Δ C.From Fig. 7 obviously as can be known, increase capacitor area and can effectively reduce the localized capacitance amount of variability.For MIM capacitor, the area that increases capacitor can effectively reduce the localized capacitance amount of variability; But, increase the area of capacitor and can't effectively reduce the localized capacitance amount of variability the MOM capacitor.And along with the area increase of capacitor, the comprehensive electric capacity amount of variability between the capacitor also can increase, and can improve the difficulty of making the consistent product of usefulness (performance).
In sum, for having the integrated circuit (IC) products of capacitor, the statistical variation or dispersion amount of its condenser capacitance value is considerable to its quality.Therefore, how can reduce the electric capacity amount of variability between the capacitor of made, become the task of top priority of present integrated circuit technology.
Summary of the invention
Purpose of the present invention is exactly in the structure that a kind of capacitor group is provided, and can reduce the electric capacity amount of variability between the capacitor, to improve the usefulness of product.
Another object of the present invention provides a kind of method that reduces the electric capacity amount of variability between the capacitor, localized capacitance amount of variability between the capacitor is more effectively reduced with the increase of capacitor area, make comprehensive electric capacity amount of variability be lower than prior art gained person simultaneously.
The structure of a kind of capacitor group proposed by the invention comprises at least two capacitors that are disposed at same position on the substrate, and this two capacitor is first capacitor and second capacitor.Wherein, first capacitor comprises a plurality of first capacitor cells that are connected in parallel to each other, and second capacitor comprises a plurality of second capacitor cells that are connected in parallel to each other, and these first capacitor cells and second capacitor cell are staggered to an array.
According to embodiments of the invention, above-mentioned first capacitor cell and second capacitor cell for example are only to line up two-dimensional array on a plane, and what this plane can be with substrate is surperficial parallel or vertical.。
According to embodiments of the invention, above-mentioned first capacitor cell and second capacitor cell also can be arranged in cubical array.Wherein, first and second capacitor cell can only be staggered on a plane that is made of two dimension directions.This moment, the mode of first capacitor cell and second capacitor cell arrangement for example was: the identical capacitor cell of repeated arrangement on the direction vertical with substrate surface, and the one the second capacitor cells that are staggered on the horizontal plane parallel with substrate surface; Or with the parallel horizontal direction of substrate surface on the identical capacitor cell of repeated arrangement, and the one the second capacitor cells that on the vertical vertical plane of horizontal direction therewith, are staggered.In addition, first capacitor cell also can all be staggered on three coordinate planes of corresponding above-mentioned cubical array with second capacitor cell.Three dimension directions of this cubical array can be orthogonal, comprises a vertical direction and with substrate surface parallel two horizontal directions vertical with substrate surface.
Described according to embodiments of the invention, the first above-mentioned capacitor cell can be all identical with the quantity of second capacitor cell and capacitance.In addition, first and second capacitor for example is metal-oxide layer-metal (MOM) capacitor, or metal-insulator-metal (MIM) capacitor.
Moreover in the structure of the capacitor group of the invention described above, each first capacitor cell for example comprises first electrode, second electrode and dielectric material therebetween, and each second capacitor cell for example comprises third electrode, the 4th electrode and dielectric material therebetween.First electrode of all first capacitor cells is electrically connected to each other, and second electrode is electrically connected to each other; The third electrode of all second capacitor cells is electrically connected to each other, and the 4th electrode is electrically connected to each other.In addition, when above-mentioned the one the second capacitors were metal-oxide layer-metal capacitor, each first, second, third, fourth electrode for example all was pectination.
The present invention proposes a kind of method that reduces the electric capacity amount of variability between the capacitor in addition, at least two capacitors that will comprise first capacitor and second capacitor are formed on the same position on the substrate, its method comprises formation a plurality of first capacitor cells that are connected in parallel to each other and a plurality of second capacitor cells that are connected in parallel to each other, to constitute first capacitor and second capacitor respectively, wherein first capacitor cell is all identical with the quantity and the capacitance of second capacitor cell, and first capacitor cell and second capacitor cell are staggered to an array.
Described according to embodiments of the invention, the first above-mentioned capacitor unit and second capacitor unit for example are only to line up two-dimensional array on a plane, and what this plane can be with substrate is surperficial parallel or vertical.
According to embodiments of the invention, above-mentioned first capacitor cell and second capacitor cell also can be arranged in cubical array.Wherein, first and second capacitor cell can only be staggered on a plane that is made of two dimension directions.This moment, the mode of first capacitor cell and second capacitor cell arrangement for example was: the identical capacitor cell of repeated arrangement on the direction vertical with substrate surface, and the one the second capacitor cells that are staggered on the horizontal plane parallel with substrate surface; Or with the parallel horizontal direction of substrate surface on the identical capacitor cell of repeated arrangement, and the one the second capacitor cells that on the vertical vertical plane of horizontal direction therewith, are staggered.In addition, first capacitor cell also can all be staggered on three coordinate planes of corresponding above-mentioned cubical array with second capacitor cell.Three dimension directions of this cubical array can be orthogonal, comprises a vertical direction and with substrate surface parallel two horizontal directions vertical with substrate surface.
In addition, first and second capacitor for example is metal-oxide layer-metal (MOM) capacitor, or metal-insulator-metal (MIM) capacitor.
In some embodiment, each first capacitor cell comprises first electrode, second electrode and dielectric material therebetween, and each second capacitor cell comprises third electrode, the 4th electrode and dielectric material therebetween.First electrode of all first capacitor cells is electrically connected to each other, and second electrode is electrically connected to each other; The third electrode of all second capacitor cells is electrically connected to each other, and the 4th electrode is electrically connected to each other.In addition, when first capacitor and second capacitor all during metal-oxide layer-metal capacitor, each first, second, third, fourth electrode for example all is pectination.
The present invention is cut apart (partition) separately with at least two capacitors and is become a plurality of capacitor cells, and the capacitor cell of each capacitor is staggered to two dimension or three-dimensional netted (mesh) structure, to reduce relative variability degree between the capacitor (contain localized capacitance amount of variability with electric capacity amount of variability) comprehensively.Therefore, the present invention can effectively prevent the electric capacity mismatch problem between the capacitor, and makes the usefulness of product more tend to consistent.
For above and other objects of the present invention, feature and advantage can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.
Description of drawings
Fig. 1～3 illustrate the structure of the capacitor group of the present invention three embodiment.
Fig. 4 A～4D illustrates four examples of capacitor cell structure of the present invention.
Fig. 5 illustrates in the capacitor group of electrode shape of the capacitor cell arrangement mode of adopting Fig. 2 and Fig. 4 A, with an example of the connected mode between the capacitor cell of one deck.
Fig. 6 A～6B illustrates in the capacitor group of electrode shape of the capacitor cell arrangement mode of adopting Fig. 2 and Fig. 4 A, an example of the connected mode between two layers the capacitor cell.
The capacitance of Fig. 7 illustration short distance inner capacitor is with the variation of position.
Fig. 8 illustration length is apart from the variation with the position of the capacitance of inner capacitor.
The simple symbol explanation
10: substrate
100,200,300: the capacitor group
102,102 ', 602a, 602b, 602c, 602d, 602e, 602f, 602g, 602h: first capacitor cell
104,104 ', 604a, 604b, 604c, 604d, 604e, 604f, 604g, 604h: second capacitor cell
106,106 ', 106 ", 108,108 ', 108 ": the dotted line of expression electrically connect
402,404,406,408: metal-oxide layer-metal capacitance unit
402a, 402c, 502,504,506,508,510,512,514,5 16,606,608,610,612,614,616,618,620,622,624,626,628,630,632,634,636: electrode
402b: oxide layer
802,804: curve
Embodiment
The basic conception of the electric capacity amount of variability between the reduction capacitor of the present invention is, first capacitor of capacitor group is cut apart a plurality of first capacitor cells that (partition) becomes to be connected in parallel to each other, second capacitor is divided into a plurality of second capacitor cells that are connected in parallel to each other, and makes first capacitor cell and second capacitor unit be staggered to an array.In a preferred embodiment, first capacitor is identical with the capacitance of second capacitor, and first capacitor cell is identical with the quantity of second capacitor cell, and the capacitance of each capacitor cell is all identical.
Please refer to Fig. 8, its illustration length is apart from the variation (curve 802) with the position of the capacitance of inner capacitor, and the length of the corresponding electric capacity amount of variability comprehensively of curve 804 expressions is apart from capacitance variation trend.At X
1, X
2Between two positions, the relative variability degree that is caused by the short distance capacitance variations is Δ C
1, it is the difference of L1 and L2; And by long be Δ C apart from the relative variability degree that capacitance variations caused
2, it is the difference of G1 and G2.By among the figure as can be known, Δ C
2Less than Δ C
1, that is be reduce the distance (be equal to and dwindle area) comprehensive electric capacity amount of variability is reduced.Therefore, when first and second capacitor with the capacitor group was divided into a plurality of first and second capacitor cell respectively, it can reduce the comprehensive electric capacity amount of variability between each capacitor.
In addition, though following each embodiment all is that the capacitor group of being formed with two identical capacitors of capacitance is that example is done explanation, but the rest may be inferred, capacitor group of the present invention can also be made up of the capacitance identical capacitor more than two, as long as suitable line design is arranged so that each capacitor cell of same capacitor is in parallel.
The structure of the capacitor group of various embodiments of the present invention below is described.Fig. 1 illustrates the structure of the capacitor group of one embodiment of the invention.
Please refer to Fig. 1, the structure of the capacitor group 100 of present embodiment comprises a plurality of first capacitor cells 102 and a plurality of second capacitor cells 104, is disposed on the substrate 10.The quantity of first capacitor cell 102 and second capacitor cell 104 and the capacitance of each capacitor cell are all identical, and first capacitor unit 102 is connected in parallel to each other into first capacitor, and second capacitor cell 104 is connected in parallel to each other into second capacitor.In this embodiment, first capacitor cell 102 and second capacitor cell 104 all are staggered on three coordinate planes of cubical array, this three-dimensional plane can be XY, XZ, YZ plane shown in Figure 1, wherein X, Y direction are two the surperficial parallel horizontal directions with substrate 10, the Z direction then is the direction with the Surface Vertical of substrate 10, and X, Y, Z three parts quadrature towards each other.In addition, the mode that first capacitor cell 102 is electrically connected to each other can be shown in dotted line 106, and the mode that second capacitor cell 104 is electrically connected to each other can be shown in dotted line 108.
Fig. 2 illustrates the structure of the capacitor group of another embodiment of the present invention.In this embodiment, first capacitor cell 102 and the mode that second capacitor cell 104 is arranged be with the Z direction of the Surface Vertical of substrate 10 on repeat the identical capacitor cell of storehouse, and with the surperficial parallel XY plane of substrate 10 on be staggered first capacitor cell 102 and second capacitor cell 104.In addition, the mode that first capacitor cell 102 is electrically connected to each other can be shown in dotted line 106 ', and the mode that second capacitor unit 104 is electrically connected to each other can be shown in dotted line 108 '.
Fig. 3 illustrates the structure of the capacitor group of further embodiment of this invention.In this embodiment, first capacitor unit 102 and the mode that second capacitor unit 104 is arranged be with a surperficial parallel horizontal direction (as directions X or the Y direction) capacitor cell that repeated arrangement is identical of substrate 10, and on the vertical vertical plane (as YZ plane or XZ plane) of horizontal direction therewith, be staggered.In addition, the mode that first capacitor cell 102 is electrically connected to each other can be as dotted line 106 " shown in, and the mode that second capacitor cell 104 is electrically connected to each other can be as dotted line 108 " shown in.
The various embodiments described above all are to be example with 4 first capacitor cells and 4 second capacitor cells 2 * 2 * 2 cubical arraies that form that are staggered, and solid netted (mesh) structure of capacitor group of the present invention is described.Yet the rest may be inferred, and the structure of capacitor group of the present invention can for example be N also
1* N
2* N
3Cubical array, N wherein
1, N
2, N
3For more than or equal to 2 integer, but be not 2 simultaneously.
Certainly, the structure of capacitor group of the present invention also can be only on a plane, be staggered the one the second capacitor cells and two-dimensional array, i.e. M
1* M
2(M
1, M
2〉=2) array, wherein this plane can be parallel with substrate surface or vertical.The two-dimensional array of arranging on the plane parallel with substrate surface for example is 4 the first/the second arrays that capacitor cell is lined up in the simple layer among Fig. 1 or Fig. 2, and the two-dimensional array of arranging on the plane vertical with substrate surface then for example is 4 the first/the second arrays that capacitor cell is lined up on the same XZ plane among Fig. 3.
In addition, first capacitor and second capacitor for example are metal-oxide layer-metal (MOM) capacitors, or metal-insulator-metal (MIM) capacitor.First capacitor cell 102 among the embodiment can be made up of first electrode, second electrode and dielectric material therebetween, and second capacitor cell 104 can be made up of third electrode, the 4th electrode and dielectric material therebetween.Wherein, first electrode, second electrode, third electrode and the 4th electrode for example are metal levels, and dielectric material for example is silica or other insulating material.
With first capacitor and second capacitor is that the situation of MOM capacitor is an example, and its first/two capacitor cell 102/104 for example is the MOM capacitor cell 402,404,406 or 408 shown in Fig. 4 A～4D, or the MOM capacitor cell of other electrode shape.Wherein, MOM capacitor cell 402 comprises the electrode 402a of pectination, another electrode 402c of pectination and oxide layer 402b therebetween, and MOM capacitor cell 404,406,408 comprises two electrodes of shape complementarity and oxide layer therebetween equally.The present invention does not do special qualification to the electrode number of plies, area and the capacitance of above-mentioned MOM capacitor cell, and it is decided on design requirement and desired capacitance.
To be example with the electrode shape of capacitor cell arrangement mode shown in Figure 2 and the capacitor cell shown in Fig. 4 A hereinafter, how explanation will make first capacitor cell be connected in parallel to each other, and second capacitor cell is connected in parallel to each other.Please refer to Fig. 5, it illustrates in this example the top view with 4 capacitor cells of one deck.As shown in Figure 5, first capacitor cell 102,102 ' that the diagonal angle is arranged is connected in parallel to each other, its connected mode is that the electrode 502 of first capacitor cell 102 is connected with the electrode 508 of first capacitor cell 102 ', and the electrode 504 of first capacitor cell 102 is connected with the electrode 506 of first capacitor cell 102 '; Being all second capacitor cell of arranging at the diagonal angle 104,104 ' is connected in parallel to each other, its connected mode is that the electrode 510 of second capacitor cell 104 is connected with the electrode 516 of second capacitor cell 104 ', and the electrode 514 of the electrode 512 of second capacitor cell 104 and second capacitor cell 104 '.Line between line between first capacitor cell 102 and 102 ' and second capacitor cell 104,104 ' is staggered herein, its formation method is as being produced on the line between first capacitor cell 102 and 102 ' (or second capacitor cell 104 and 104 ') same one deck of the one the second capacitor cells, and the line between second capacitor cell 104 and 104 ' (or first capacitor cell 102 and 102 ') is produced on the following one deck or the last layer of the one the second capacitor cells.
In another embodiment of the electrode shape of the capacitor cell of the capacitor cell arrangement mode that adopts Fig. 2 and Fig. 4 A, the connected mode between the one the second capacitor cells is as follows.Please refer to Fig. 6 A and Fig. 6 B, it illustrates in this example the top view of two layers capacitor cell.As shown in Figure 6A, superstructure comprises the first capacitor cell 602a, 602c, 602b, the 602d that is the diagonal angle arrangement in twos, and is the second capacitor cell 604c, 604a, 604d, 604b that the diagonal angle is arranged in twos.The first capacitor cell 602a, 602b, 602c, 602d are connected in parallel to each other, and its connected mode is: the electrode 606 of the first capacitor cell 602a is connected with the electrode 614 of the first adjacent capacitor cell 602c, and 608 at another electrode is connected with another electrode 616 of the latter; The electrode 610 of the first capacitor cell 602b is connected with the electrode 618 of the first adjacent capacitor cell 602d, and 612 at another electrode is connected with another electrode 620 of the latter; And the non-conterminous first capacitor cell 602a is connected by the lead outside these 8 capacitor cells that detour with 612 with 602b electrode 608 separately, and the non-conterminous first capacitor cell 602c also is connected by the lead outside these 8 capacitor cells that detour with 618 with 602d electrode 614 separately.Shown in Fig. 6 B, understructure comprises and is the first capacitor cell 602e, 602g, 602f, the 602h that arranges at the diagonal angle in twos and is the second capacitor cell 604g, 604e, 604h, the 604f that the diagonal angle is arranged in twos.The second capacitor cell 604e, 604f, 604g, 604h are connected in parallel to each other, and its connected mode is: the electrode 622 of the second capacitor cell 604e is connected with the electrode 630 of the second adjacent capacitor cell 604g, and 624 at another electrode is connected with another electrode 632 of the latter; The electrode 626 of the second capacitor cell 604f is connected with the electrode 634 of the second adjacent capacitor cell 604h, and 628 at another electrode is connected with another electrode 636 of the latter; And the non-conterminous second capacitor cell 604e is connected by the lead outside these 8 capacitor cells that detour with 628 with 604f electrode 624 separately, and the non-conterminous second capacitor cell 604g also is connected by the lead outside these 8 capacitor cells that detour with 634 with 604h electrode 630 separately.Simultaneously, the first capacitor cell 602a on upper strata, 602b, 602c, 602d connect the first capacitor cell 602e, 602f, 602g, the 602h of lower floor respectively with metal plug (not illustrating), and the second capacitor cell 604a on upper strata, 604b, 604c, 604d connect the second capacitor cell 604e, 604f, 604g, the 604h of lower floor respectively with metal plug (not illustrating).Each to the capacitor cell that links to each other up and down in, two electrodes of upper strata capacitor cell connect the counter electrode of lower floor's capacitor cell respectively with metal plug.
In sum, because the capacitor in the capacitor group of the present invention is to be composed in parallel by the less capacitor cell of the area that is split to form, so compare down with the existing capacitor of the identical gross area of tool, the comprehensive electric capacity amount of variability between its capacitor can effectively reduce.In addition, because the present invention is staggered to two dimension or three-dimensional network structure with a plurality of capacitor cells, therefore can reduce localized capacitance amount of variability and comprehensive electric capacity amount of variability between the capacitor simultaneously, can avoid the unmatched problem of electric capacity thus, and improve the consistency of product usefulness.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (26)
1. the structure of a capacitor group, wherein, this structure comprises at least two capacitors that are disposed at same position on the substrate, this two capacitor comprises:
First capacitor comprises a plurality of first capacitor cells that are connected in parallel to each other; And
Second capacitor comprises a plurality of second capacitor cells that are connected in parallel to each other,
Wherein those first capacitor cells and those second capacitor cells are staggered to an array.
2. the structure of capacitor group as claimed in claim 1, wherein, this array is for arranging two-dimensional array in the plane.
3. the structure of capacitor group as claimed in claim 2, wherein, this plane is surperficial parallel or vertical with this substrate.
4. the structure of capacitor group as claimed in claim 1, wherein, this array is a cubical array.
5. the structure of capacitor group as claimed in claim 4, wherein, those first capacitor cells and those second capacitor cells only are staggered on the plane that is made of two dimension directions.
6. the structure of capacitor group as claimed in claim 5, wherein, those first capacitor cells comprise with the mode that those second capacitor cells are arranged: with the direction of the Surface Vertical of this substrate on the identical capacitor cell of repeated arrangement, and with the surperficial parallel horizontal plane of this substrate on be staggered those first capacitor cells and those second capacitor cells.
7. the structure of capacitor group as claimed in claim 5, wherein, those first capacitor cells comprise with the mode that those second capacitor cells are arranged: with the surperficial parallel horizontal direction of this substrate on the identical capacitor cell of repeated arrangement, and on the vertical plane vertical, be staggered those first capacitor cells and those second capacitor cells with this horizontal direction.
8. the structure of capacitor group as claimed in claim 4, wherein, those first capacitor cells and those second capacitor cells are to should all being staggered on three coordinate planes of cubical array.
9. the structure of capacitor group as claimed in claim 8, wherein, three dimension directions of this cubical array are orthogonal, comprise with a vertical direction of the Surface Vertical of this substrate and with the two surperficial parallel horizontal directions of this substrate.
10. the structure of capacitor group as claimed in claim 1, wherein, those first capacitor cells are all identical with the quantity and the capacitance of those second capacitor cells.
11. the structure of capacitor group as claimed in claim 1, wherein, this first capacitor and this second capacitor are metal-oxide layer-metal capacitor, or metal-insulating layer-metal capacitor.
12. the structure of capacitor group as claimed in claim 1, wherein,
Each first capacitor cell comprises first electrode, second electrode and is disposed at this first electrode and this second interelectrode dielectric material;
Each second capacitor cell comprises third electrode, the 4th electrode and is disposed at this third electrode and the 4th interelectrode this dielectric material;
Those first electrodes of those first capacitor cells are electrically connected to each other, and those second electrodes are electrically connected to each other; And
Those third electrodes of those second capacitor cells are electrically connected to each other, and those the 4th electrodes are electrically connected to each other.
13. the structure of capacitor group as claimed in claim 12, wherein, this first capacitor and this second capacitor are metal-oxide layer-metal capacitor, and respectively this first, second, third, fourth electrode all is pectination.
14. a method that reduces the electric capacity amount of variability between the capacitor comprises:
At least two capacitors that will comprise first capacitor and second capacitor are formed on the same position on the substrate, and its method comprises:
A plurality of first capacitor cells that formation is connected in parallel to each other and a plurality of second capacitor cells that are connected in parallel to each other, to constitute this first capacitor and this second capacitor respectively, wherein, those first capacitor cells are all identical with the quantity and the capacitance of those second capacitor cells, and are staggered to an array.
15. the method for the electric capacity amount of variability between the reduction capacitor as claimed in claim 14, wherein, this array is for arranging two-dimensional array in the plane.
16. the method for the electric capacity amount of variability between the reduction capacitor as claimed in claim 15, wherein, this plane is surperficial parallel or vertical with this substrate.
17. the method for the electric capacity amount of variability between the reduction capacitor as claimed in claim 14, wherein, this array is a cubical array.
18. the method for the electric capacity amount of variability between the reduction capacitor as claimed in claim 17, wherein, a little first capacitor cells and those second capacitor cells only are staggered on the plane that is made of two dimension directions.
19. the method for the electric capacity amount of variability between the reduction capacitor as claimed in claim 18, wherein, those first capacitor cells comprise with the mode that those second capacitor cells are arranged: with the direction of the Surface Vertical of this substrate on the identical capacitor cell of repeated arrangement, and with the surperficial parallel horizontal plane of this substrate on be staggered those first capacitor cells and those second capacitor cells.
20. the method for the electric capacity amount of variability between the reduction capacitor as claimed in claim 18, wherein, those first capacitor cells comprise with the mode that those second capacitor cells are arranged: with the surperficial parallel horizontal direction of this substrate on the identical capacitor cell of repeated arrangement, and on the vertical plane vertical, be staggered those first capacitor cells and those second capacitor cells with this horizontal direction.
21. the method for the electric capacity amount of variability between the reduction capacitor as claimed in claim 17, wherein, those first capacitor cells and those second capacitor cells are to should all being staggered on three coordinate planes of cubical array.
22. the method for the electric capacity amount of variability between the reduction capacitor as claimed in claim 21, wherein, three dimension directions of this cubical array are orthogonal, comprise with a vertical direction of the Surface Vertical of this substrate and with the two surperficial parallel horizontal directions of this substrate.
23. the method for the electric capacity amount of variability between the reduction capacitor as claimed in claim 14, wherein, this first capacitor and this second capacitor comprise metal-oxide layer-metal capacitor.
24. the method for the electric capacity amount of variability between the reduction capacitor as claimed in claim 14, wherein, this first capacitor and this second capacitor comprise metal-insulating layer-metal capacitor.
25. the method for the electric capacity amount of variability between the reduction capacitor as claimed in claim 14, wherein,
Each first capacitor cell comprises first electrode, second electrode and is disposed at this first electrode and this second interelectrode dielectric material;
Each second capacitor cell comprises third electrode, the 4th electrode and is disposed at this third electrode and the 4th interelectrode this dielectric material;
Those first electrodes of those first capacitor cells are electrically connected to each other, and those second electrodes are electrically connected to each other; And
Those third electrodes of those second capacitor cells are electrically connected to each other, and those the 4th electrodes are electrically connected to each other.
26. the method for the electric capacity amount of variability between the reduction capacitor as claimed in claim 25, wherein, this first capacitor and this second capacitor are metal-oxide layer-metal capacitor, and respectively this first, second, third, fourth electrode all is pectination.
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| CNB2006101061652A CN100490146C (en) | 2006-07-20 | 2006-07-20 | Capacitor group structure and method for reducing capacitance variation amount between capacitors |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102437176A (en) * | 2011-08-17 | 2012-05-02 | 上海华力微电子有限公司 | Process for increasing capacitance density of integrated circuit |
| CN102543949A (en) * | 2009-06-03 | 2012-07-04 | 联发科技股份有限公司 | Capacitor |
| CN102881565A (en) * | 2012-10-22 | 2013-01-16 | 上海集成电路研发中心有限公司 | Method for forming metal-oxide-metal (MOM) capacitor |
| CN107579083A (en) * | 2017-09-30 | 2018-01-12 | 京东方科技集团股份有限公司 | Array base palte and preparation method and display device |
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2006
- 2006-07-20 CN CNB2006101061652A patent/CN100490146C/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543949A (en) * | 2009-06-03 | 2012-07-04 | 联发科技股份有限公司 | Capacitor |
| CN102543949B (en) * | 2009-06-03 | 2014-11-19 | 联发科技股份有限公司 | Capacitor |
| CN102437176A (en) * | 2011-08-17 | 2012-05-02 | 上海华力微电子有限公司 | Process for increasing capacitance density of integrated circuit |
| CN102437176B (en) * | 2011-08-17 | 2014-04-02 | 上海华力微电子有限公司 | Process for increasing capacitance density of integrated circuit |
| CN102881565A (en) * | 2012-10-22 | 2013-01-16 | 上海集成电路研发中心有限公司 | Method for forming metal-oxide-metal (MOM) capacitor |
| CN107579083A (en) * | 2017-09-30 | 2018-01-12 | 京东方科技集团股份有限公司 | Array base palte and preparation method and display device |
| CN107579083B (en) * | 2017-09-30 | 2024-06-11 | 京东方科技集团股份有限公司 | Array substrate, preparation method and display device |
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