CN205720647U - A kind of ultrasound emission communication channel delay control module - Google Patents

Abstract

The utility model relates to a kind of ultrasound emission communication channel delay control module, including block RAM, several passages, high-voltage pulse form module and probe in peripheral control unit PC, delay parameter read-write bus, FPGA piece, also include a counter and several passages several comparators corresponding, wherein in FPGA piece block RAM by delay parameter t_iLoad to an input of several passages several comparators corresponding, simultaneously by delay parameter t_iMaximum and minimum of a value load to a counter as the count range counting up, the real-time counting value of counter loads to another input of several comparators, the real-time counting value of counter and delay parameter value are compared by several comparators, when numerical value is equal, each communication channel delay time arrives, and comparator output enables its respective channel of level triggers.The utility model reduces the FPGA resource taking, and improves cost performance.

Description

A kind of ultrasound emission communication channel delay control module

Technical field

The utility model relates to ultrasonic phased array technology field, especially a kind of ultrasound emission communication channel delay control module.

Background technology

Ultrasonic system includes ultrasonic probe 1, T/R change-over switch 2, ultrasonic reception 3, receives Beam synthesis 4, signal transacting with Image shows 5, launches driving 6, and transmitted waveform produces 7, and emission delay controls 8, controls scanning 9.Such as Fig. 1 ultrasonic system block diagram. Emission delay control 8 control transmitted waveform produces 7, forms high-voltage pulse, incentive probe 1 through level conversion, and probe 1 is by electric energy It is converted into acoustical energy emission to go out.The echo impulse receiving is converted into electric energy by probe 1, through ultrasonic reception 3, receives wave beam and closes Becoming 4, then carrying out signal transacting again, image shows.

The supersonic beam making probe launch converges convergence in the range of certain depth and is referred to as focus ultrasonic.Due to ultrasonic system Being multichannel, after commencing signal is handed down to emission delay control module by scan control module, emission delay controls First module need to be focused processing, to increase the signal to noise ratio of echo-signal so that it is penetration power and echo strength strengthen, Ke Yigai Kind detectivity, resolving power also will be greatly enhanced.Focusing is divided into Acoustic focusing and electron focusing.One probe is come Say, for improving its detection performance, one of which or two kinds of combinations can be used.

Electron focusing is to be realized by controlling the electronic delay of passage, applies phased-array technique, each battle array to linear array probe Unit provides the excitation according to conic section rule time delay, makes sound field district composite wave front become conic section concave surface, thus realizes ripple Bundle focuses on, and this type of focusing is electron focusing.

If Fig. 2 is traditional ultrasound emission communication channel delay control module block diagram.When ultrasonic system starts, peripheral control unit PC 10 by the focusing delay parameter t of scanning probe type selected by user_iIt is loaded in FPGA piece by delay parameter read-write bus 11 Block RAM 12, in FPGA piece, 32 delay parameters are loaded into 32 counters corresponding to 32 transmission channels 13 by block RAM 12 The input of 14, counter 14, using delay parameter as count maximum, starts counting up from collaborative count value, when counting reaches The delay parameter time, trigger the waveform generation module of its respective channel, produce transmitted waveform, enter each transmitting height through level translation Pressure pulse shaping module 15, incentive probe 16, form the launching beam focusing on.

Each transmission channel of traditional transmitter module uses a delay counter, and delays time to control module is according to master clock Control delay counter counts, and when count value reaches the delay parameter of regulation, trigger port launches enable, 32 passages Then need 32 delay counters, take substantial amounts of spatial cache, occupy the substantial amounts of internal resource of FPGA, improve system This, greatly reduce the cost performance of system, and in high accuracy time delay module, the spatial cache shared by 32 counters is bigger.

Utility model content

The technical problems to be solved in the utility model is to overcome existing defect, provides a kind of ultrasound emission communication channel delay control Molding block, reduces the FPGA resource taking, improves cost performance.

In order to solve above-mentioned technical problem, the utility model provides following technical scheme:

A kind of ultrasound emission communication channel delay control module of the utility model, including the read-write of peripheral control unit PC, delay parameter Block RAM in bus, FPGA piece, several passages, high-voltage pulse form module and probe, also include a counter and several Passage several comparators corresponding, peripheral control unit PC is by the delay parameter t of selected scanning probe type_iPass through delay parameter Read-write bus is loaded into block RAM in FPGA piece, and in FPGA piece, block RAM is by delay parameter t_iIf loading corresponding to several passages One input of dry comparator, simultaneously by delay parameter t_iMaximum and minimum of a value load to a counter conduct The count range counting up, the real-time counting value of counter loads to another input of several comparators, several ratios Comparing the real-time counting value of counter and delay parameter value compared with device, when numerical value is equal, each communication channel delay time arrives, than Enable the waveform generation module of its respective channel of level triggers compared with device output, produce transmitted waveform, enter each height through level translation Pressure pulse shaping module, incentive probe, form the launching beam focusing on.

Further, the delay parameter of each passage is:

$t_i=\left\{\begin{array}{cc}\frac{f}{c}-\frac{\sqrt{f^2+{(id/2)}^2}}{c}+t_0& i=-1,0,1\\ \frac{f}{c}-\frac{\sqrt{f^2+{\left(\right(i-1/2)*d)}^2}}{c}+t_0& i=-\frac{n}{2}...-3,-2,2,3...\frac{n}{2}\end{array}\right.$

Wherein, participating in launching array number is n, and array element centre-to-centre spacing is d, and the distance launching focus to array element is f, and c is ultrasonic Spread speed 1540m/s of ripple, the maximum of the scope of delay parameter is t₀, minimum of a value is t_n/2。

The beneficial effects of the utility model: comparator is replaced counter, count merely with a counter, compare The instantaneous value of counter is compared by device with delay parameter value, just triggers respective channel once reach this value, therefore, reduces The FPGA resource taking, improves cost performance.

Brief description

Fig. 1 is ultrasonic system block diagram；

Fig. 2 is traditional ultrasound emission communication channel delay control module block diagram；

Fig. 3 is the linear array delay and focusing schematic diagram of preferred embodiment of the present utility model；

Fig. 4 is the ultrasound emission communication channel delay control module block diagram of preferred embodiments of the present utility model.

Detailed description of the invention

Embodiment cited by the utility model, is only intended to help and understands the utility model, should not be construed as to this reality With the restriction of novel protected scope, for those skilled in the art, without departing from the utility model thought On the premise of, the utility model can also be made improvements and modifications, these improve and modification also falls into the utility model right In claimed scope.

Assuming there are 128 array elements, the system of 32 passages, the focus of its transmitting focusing can be by arranging to each passage Different time delays realizes, such as Fig. 3 linear array delay and focusing schematic diagram.In order to realize focusing on, the array element farthest from array element center is first It is first energized and produce ultrasound emission, then ultrasonic according still further to the order delay emission close toward array element center.For simplicity, Diagram only draws 4 array elements, and 0 array element only makes reference, and owing to launching the symmetry of array element, only calculates the lower half of center array element here Limit array element, with t launch time of center array element₀For the reference time, the launch time of its following i-th array element has for center array element There is τ_i(τ_i≤ 0) time delay.Assuming that participating in launching array number is n, array element centre-to-centre spacing is d, and the distance launching focus to array element is f, can Obtain the driving pulse delay time of the i-th array element.

In so 32 passages, the delay parameter of each passage is:

$t_i=\left\{\begin{array}{cc}\frac{f}{c}-\frac{\sqrt{f^2+{(id/2)}^2}}{c}+t_0& i=-1,0,1\\ \frac{f}{c}-\frac{\sqrt{f^2+{\left(\right(i-1/2)*d)}^2}}{c}+t_0& i=-\frac{n}{2}...-3,-2,2,3...\frac{n}{2}\end{array}\right.$

Wherein c is spread speed 1540m/s of ultrasonic wave, maximum t of the scope of delay parameter_maxFor t₀, minimum of a value t_minFor t_n/2。

If Fig. 4 is a kind of ultrasound emission communication channel delay control module block diagram of the utility model.Including peripheral control unit PC 10th, in delay parameter read-write bus the 11st, FPGA piece, block RAM the 12nd, 32 passage the 13rd, counter the 14th, high-voltage pulses form mould The 15th, block pops one's head in 16 and 32 comparators 17, and peripheral control unit PC 10 is by the delay parameter t of selected probe 16 scan types_iPass through Delay parameter read-write bus 11 is loaded into block RAM 12 in FPGA piece, and in FPGA piece, block RAM 12 is by delay parameter t_iLoad to 32 The A input of corresponding 32 comparators 17 of individual passage 13, simultaneously by delay parameter t_iMaximum t_maxAnd minimum of a value t_min Load to counter 14 as the count range counting up.The real-time counting value of counter 14 loads to the B of 32 comparators 17 Input, when the value of A input is equal with the value of B input, each communication channel delay time arrives, and comparator 17 output enables level Trigger the waveform generation module of its respective channel, produce transmitted waveform, enter each high-voltage pulse through level translation and form module 15, Incentive probe 16, forms the launching beam focusing on.

32 comparators 17 are replaced 32 counters by the utility model, count just with a counter 14, The instantaneous value of counter 14 and delay parameter value are compared by 32 comparators 17, just trigger transmission channel once reach this value 13, this reduces the FPGA resource taking, improve cost performance.

Claims (2)

1. a ultrasound emission communication channel delay control module, including peripheral control unit PC (10), delay parameter read-write bus (11), In FPGA piece, block RAM (12), several passages (13), high-voltage pulse form module (15) and probe (16), it is characterised in that: also Including a counter (14) and several passages several comparators corresponding (17), peripheral control unit PC (10) is by selected spy The delay parameter t of head (16) scan type_iIt is loaded into block RAM (12) in FPGA piece by delay parameter read-write bus (11), In FPGA piece, block RAM (12) is by delay parameter t_iLoad to one of several passages (13) several comparators corresponding (17) Input, simultaneously by delay parameter t_iMaximum and minimum of a value load to a counter (14) as the counting counting up Scope, the real-time counting value of counter (14) loads to another input of several comparators (17), several comparators (17) the real-time counting value of counter (14) is compared with delay parameter value, each communication channel delay time when numerical value is equal Arriving, comparator (17) output enables the waveform generation module of its respective channel of level triggers, produces transmitted waveform, through level translation Enter each high-voltage pulse and form module (15), incentive probe (16), form the launching beam focusing on.

2. ultrasound emission communication channel delay control module according to claim 1, it is characterised in that: the time delay of described each passage Parameter is:

$t_i=\left\{\begin{array}{cc}\frac{f}{c}-\frac{\sqrt{f^2+{(id/2)}^2}}{c}+t_0& i=-1,0,1\\ \frac{f}{c}-\frac{\sqrt{f^2+{\left(\right(i-1/2)*d)}^2}}{c}+t_0& i=-\frac{n}{2}...-3,-2,2,3...\frac{n}{2}\end{array}\right.$

Wherein, participating in launching array number is n, and array element centre-to-centre spacing is d, and the distance launching focus to array element is f, and c is ultrasonic wave Spread speed 1540m/s, the maximum of the scope of delay parameter is t₀, minimum of a value is t_n/2。