CN105866767A - Ultrasonic emission channel time-delay control module - Google Patents

Abstract

The invention relates to an ultrasonic emission channel time-delay control module. The ultrasonic emission channel time-delay control module comprises an external controller PC, a time-delay parameter reading-writing bus, an FPGA chip internal block RAM, a plurality of channels, a high-voltage pulse forming module and a probe, and further comprises a counter and a plurality of comparers corresponding to the channels, wherein the FPGA chip internal block RAM loads a time-delay parameter ti to one input end of the comparers corresponding to the channels, and simultaneously loads a maximum value and a minimum value of the time-delay parameter ti to the counter to form a counting range of the counter; a real-time counting value of the counter is loaded to the other input end of the comparers; the comparers compare the real-time counting value of the counter with a time-delay parameter value, and if the real-time counting value of the counter is equal to the time-delay parameter value, the time-delay time of each channel is up, and the comparers output enabling levels to trigger the corresponding channels. According to the ultrasonic emission channel time-delay control module, occupied FPGA resources are reduced, and the cost performance of a system is improved.

Description

A kind of ultrasound emission communication channel delay control module

Technical field

The present invention relates to ultrasonic phased array technology field, especially a kind of ultrasound emission communication channel delay control module.

Background technology

Ultrasonic system includes ultrasonic probe 1, T/R permutator 2, ultrasonic reception 3, receives Beam synthesis 4, signal processing with Image shows 5, launches driving 6, and transmitted waveform produces 7, and emission delay controls 8, controls scanning 9.Such as Fig. 1 ultrasonic system Block diagram.Emission delay controls 8 control transmitted waveforms and produces 7, forms high-voltage pulse, incentive probe 1, probe through level conversion 1 converts electric energy to acoustical energy emission goes out.The echo impulse received is converted into electric energy by probe 1, through ultrasonic reception 3, connects Receiving Beam synthesis 4, carry out signal processing the most again, image shows.

The ultrasonic beam making probe launch converges convergence referred to as focus ultrasonic in the range of certain depth.Owing to ultrasonic system is manifold Road, after commencing signal is handed down to emission delay control module by scan control module, emission delay control module needs head First it is focused processing, to increase the signal to noise ratio of echo-signal so that it is penetration power and echo strength strengthen, detection spirit can be improved Sensitivity, resolving power also will be greatly enhanced.Focusing is divided into Acoustic focusing and electron focusing.For one is popped one's head in, for changing Its detection performance kind, can use one of which or two kinds of combinations.

Electron focusing is that array element each to linear array probe provides by controlling the realization of the electronic delay of passage, applying phased-array technique According to the excitation of conic section rule time delay, make sound field district composite wave front become conic section concave surface, thus realize wave beam and focus on, This type of focusing is electron focusing.

If Fig. 2 is traditional ultrasound emission communication channel delay control module block diagram.When ultrasonic system starts, peripheral control unit PC 10 By the focusing delay parameter t of scanning probe type selected by user_iIt is loaded into block in FPGA sheet by delay parameter read-write bus 11 In RAM 12, FPGA sheet, 32 delay parameters are loaded into 32 meters corresponding to 32 transmission channels 13 by block RAM 12 The input of number device 14, enumerator 14, using delay parameter as count maximum, starts counting up from collaborative count value, works as meter Count to reach the delay parameter time, trigger the waveform generation module of its respective channel, produce transmitted waveform, enter through level translation each Launch high-voltage pulse and form module 15, incentive probe 16, form the launching beam focused on.

The each transmission channel of traditional transmitter module uses a delay counter, and delays time to control module controls to prolong according to master clock Hour counter counts, and when count value arrives the delay parameter of regulation, trigger port launches enable, and 32 passages then need 32 delay counters, take substantial amounts of spatial cache, occupy the substantial amounts of internal resource of FPGA, improve system cost, Greatly reducing the cost performance of system, in high accuracy time delay module, the spatial cache shared by 32 enumerators is bigger.

Summary of the invention

The technical problem to be solved in the present invention is to overcome existing defect, it is provided that a kind of ultrasound emission communication channel delay control module, fall The low FPGA resource taken, improves cost performance.

In order to solve above-mentioned technical problem, the invention provides following technical scheme:

One ultrasound emission communication channel delay control module of the present invention, including peripheral control unit PC, delay parameter read-write bus, FPGA In sheet, block RAM, several passages, high-voltage pulse form module and probe, also include that an enumerator is corresponding with several passages Several comparators, peripheral control unit PC is by the delay parameter t of selected scanning probe type_iAdded by delay parameter read-write bus Being downloaded to block RAM in FPGA sheet, in FPGA sheet, block RAM is by delay parameter t_iLoad to corresponding several of several passages One input of comparator, simultaneously by delay parameter t_iMaximum and minima load to an enumerator as counting up Count range, the real-time counting value of enumerator loads to another input of several comparators, and several comparators will meter The real-time counting value of number device compares with delay parameter value, and when numerical value is equal, each communication channel delay time arrives, and comparator output makes The waveform generation module of energy its respective channel of level triggers, produces transmitted waveform, enters each high-voltage pulse through level translation and forms mould Block, incentive probe, form the launching beam focused on.

Further, the delay parameter of each passage is:

$t_i=\left\{\begin{array}{cc}\frac{f}{c}-\frac{\sqrt{f^2+{(id/2)}^2}}{c}+t_0& i=-1,0,1\\ \frac{f}{c}-\frac{\sqrt{f^2+{\left(\right(i-1/2)*d)}^2}}{c}+t_0& i=-\frac{n}{2}...-3,-2,2,3...\frac{n}{2}\end{array}\right.$

Wherein, participating in launching array number is n, and array element centre-to-centre spacing is d, launch focus to the distance of array element be f, c be ultrasound wave Spread speed 1540m/s, the maximum of the scope of delay parameter is t₀, minima is t_n/2。

Beneficial effects of the present invention: comparator is replaced enumerator, counts merely with an enumerator, and comparator will counting The instantaneous value of device compares with delay parameter value, just trigger respective channel once reach this value, therefore, reduces and takies FPGA resource, improves cost performance.

Accompanying drawing explanation

Fig. 1 is ultrasonic system block diagram；

Fig. 2 is traditional ultrasound emission communication channel delay control module block diagram；

Fig. 3 is the linear array delay and focusing schematic diagram of the preferred embodiments of the present invention；

Fig. 4 is the ultrasound emission communication channel delay control module block diagram of the preferred embodiments of the present invention.

Detailed description of the invention

Embodiment cited by the present invention, is only intended to help and understands the present invention, should not be construed as the limit to scope Fixed, for those skilled in the art, without departing from the inventive concept of the premise, it is also possible to the present invention Making improvements and modifications, these improve and modification also falls in the range of the claims in the present invention protection.

Assuming there are 128 array elements, the system of 32 passages, the focus of its transmitting focusing can be by arranging difference to each passage Time delay realize, such as Fig. 3 linear array delay and focusing schematic diagram.In order to realize focus on, the array element farthest from array element center first by Excitation produces ultrasound emission, then ultrasonic according still further to the order delay emission close toward array element center.For simplicity, it is illustrated that Only drawing 4 array elements, 0 array element only makes reference, and owing to launching the symmetry of array element, the most only calculates lower one side of something of center array element Array element, with t launch time of center array element₀For the reference time, the launch time of its following i-th array element center array element is had τ_i(τ_i≤ 0) time delay.Assuming that participating in launching array number is n, array element centre-to-centre spacing is d, and the distance of transmitting focus to array element is f, can Obtain the driving pulse delay time of the i-th array element.

In so 32 passages, the delay parameter of each passage is:

$t_i=\left\{\begin{array}{cc}\frac{f}{c}-\frac{\sqrt{f^2+{(id/2)}^2}}{c}+t_0& i=-1,0,1\\ \frac{f}{c}-\frac{\sqrt{f^2+{\left(\right(i-1/2)*d)}^2}}{c}+t_0& i=-\frac{n}{2}...-3,-2,2,3...\frac{n}{2}\end{array}\right.$

Wherein c is spread speed 1540m/s of ultrasound wave, the maximum t of the scope of delay parameter_maxFor t₀, minima t_minFor t_n/2。

If Fig. 4 is one ultrasound emission communication channel delay control module block diagram of the present invention.Including peripheral control unit PC 10, time delay ginseng In number read-write bus 11, FPGA sheet, block RAM 13, enumerator 14 of 12,32 passages, high-voltage pulse form module 15,16 and 32 comparators 17 of probe, peripheral control unit PC 10 is by the delay parameter t of selected probe 16 scan type_iPass through Delay parameter read-write bus 11 is loaded into block RAM 12 in FPGA sheet, and in FPGA sheet, block RAM 12 is by delay parameter t_iAdd Carry to the A input of 32 comparators 17 of 32 passage 13 correspondences, simultaneously by delay parameter t_iMaximum t_maxAnd Minima t_minLoad to enumerator 14 as the count range counted up.The real-time counting value of enumerator 14 loads to 32 ratios The B input of relatively device 17, when the value of A input is equal with the value of B input, each communication channel delay time arrives, comparator 17 outputs enable the waveform generation module of its respective channel of level triggers, produce transmitted waveform, enter each high-tension pulse through level translation Punching forms module 15, incentive probe 16, forms the launching beam focused on.

32 comparators 17 are replaced 32 enumerators by the present invention, count just with an enumerator 14,32 ratios The instantaneous value of enumerator 14 is compared by relatively device 17 with delay parameter value, just triggers transmission channel 13 once reach this value, this Sample just reduces the FPGA resource taken, and improves cost performance.

Claims (2)

1. a ultrasound emission communication channel delay control module, including peripheral control unit PC (10), delay parameter read-write bus (11), In FPGA sheet, block RAM (12), several passages (13), high-voltage pulse form module (15) and probe (16), and it is special Levy and be: also include several comparators (17) that an enumerator (14) is corresponding with several passages, peripheral control unit PC (10) by the delay parameter t of selected probe (16) scan type_iIt is loaded into FPGA by delay parameter read-write bus (11) Block RAM (12) in sheet, in FPGA sheet, block RAM (12) is by delay parameter t_iLoad to several passages (13) correspondence One input of several comparators (17), simultaneously by delay parameter t_iMaximum and minima load to a counting Device (14) loads to several comparators (17) as the count range counted up, the real-time counting value of enumerator (14) Another input, the real-time counting value of enumerator (14) is compared by several comparators (17) with delay parameter value, When numerical value is equal, each communication channel delay time arrives, and comparator (17) output enables the waveform of its respective channel of level triggers and produces mould Block, produces transmitted waveform, enters each high-voltage pulse through level translation and forms module (15), incentive probe (16), is formed and focus on Launching beam.

Ultrasound emission communication channel delay control module the most according to claim 1, it is characterised in that: the time delay of described each passage Parameter is:

$t_i=\left\{\begin{array}{cc}\frac{f}{c}-\frac{\sqrt{f^2+{(id/2)}^2}}{c}+t_0& i=-1,0,1\\ \frac{f}{c}-\frac{\sqrt{f^2+{\left(\right(i-1/2)*d)}^2}}{c}+t_0& i=-\frac{n}{2}...-3,-2,2,3...\frac{n}{2}\end{array}\right.$

Wherein, participating in launching array number is n, and array element centre-to-centre spacing is d, launch focus to the distance of array element be f, c be ultrasound wave Spread speed 1540m/s, the maximum of the scope of delay parameter is t₀, minima is t_n/2。