CN101865998A - Delay parameter real-time computation and production line type multi-beam synthesis method - Google Patents

Abstract

The invention discloses a delay parameter real-time computation and production line multi-beam synthesis method and a delay parameter real-time computation and production line multi-beam synthesis device. A delay parameter computation unit adopts two multipliers, three adders and a square root extraction arithmetic unit, and compared with a conventional scheme, saves one multiplier; and if each programmable field gate array (PFGA) processes 16 signal channels, 16 multipliers can be saved. Therefore, multi-beam technology can be realized with lower cost. The method is characterized in that: delay parameter real-time computation and a production line operation way are adopted, which can effectively reduce resource occupation and a parameter memory space. Simultaneously, the delay parameter computation device provided by the invention can conveniently change the structure of a computation circuit by mode control to make the computation circuit used for different probes.

Description

The multi-beam synthesis method of calculating in real time of a kind of delay parameter and streamline

Technical field

The present invention relates to a kind of multi-beam synthesis method, relate in particular to the multi-beam synthesis method of calculating in real time of a kind of delay parameter and streamline, this method can be applied to various types of probes.

Background technology

Along with ultrasonic clinical diagnose equipment is more and more higher to requirement quick, real time imagery, the multi-beam imaging becomes the necessary means that improves ultrasonic scan speed.In traditional single beam was synthetic, frame frequency was received the restriction of ultrasonic propagation velocity and scan depths, can't satisfy the requirement that high quality graphic shows.

Multibeam technique can form the M bar and effectively receive the acoustic beam signal in the pulsatile once emission process simultaneously, therefore makes frame frequency improve M doubly.The application of multibeam technique can perhaps obtain higher image scanning line density so that improve frame frequency under the equal line density of same system under equal frame frequency.Therefore multibeam technique has great important for improving picture frame frequency and quality.

Because the important value of multibeam technique in ultrasonic image-forming system all has a lot of design proposal and patents about multi-beam both at home and abroad.This patent is a kind of improvement that provides on existing patent 201010133657.7 bases, by the improvement of this patent, make FPGA realize can saves valuable multiplier resources.

Characteristics of this invention are, the parameter of calculating time-delay is divided into two classes, the one, need real-time parameters calculated, and the 2nd, do not need real-time parameters calculated.In calculating, time-delay will not need real-time parameters calculated to be classified as input parameter, to reduce the workload of real-time calculating as far as possible.

Another characteristics are, the computing module that the computing module relevant with the wave beam sequence number and wave beam sequence number is irrelevant separates, and the switching by two switches makes the delay parameter unit can be applied to convex array probe, linear array probe and phased array probe.This time-delay computing unit has adopted The pipeline design, and the delay parameter of M wave beam is calculated in computing unit with pipeline system, then same road echo data storage unit is read, to realize the time-delay of each wave beam.Significantly reduced the consumption of resource among the FPGA.

In the multiple-beam system design, the memory space of delay parameter is very big, is widely adopted so calculate delay parameter in real time.Real-time operation is had relatively high expectations to hardware resource, so we need find a kind of favorable method that can real-time operation can save hardware resource again.Each delay parameter computing unit has adopted three multipliers, an extraction of square root arithmetical unit, two totalizers and a subtracter in patent 201010133657.7.In FPGA realized, multiplier was a Limited resources very, reduces multiplier and will make that resource occupation reduces greatly, and it is more easy to make that FPGA realizes.

Summary of the invention

The technical problem to be solved in the present invention provides the multi-beam synthesis method of calculating in real time of a kind of delay parameter and streamline, and the present invention is at the patent of having applied for (number of patent application: 201010133657.7) provided a kind of improved delay calculating method on the basis.This method through optimizing, has drawn a kind of simple more, use resource scheme still less on the basis of original method, the present invention solves the problems of the technologies described above the technical scheme that is adopted to be:

The multi-beam synthesis method of calculating in real time of a kind of delay parameter and streamline, it has a multi-beam synthesizer at least, a multi-beam synthesizer is accepted the ultrasonic echo of a passage, and the ultrasonic echo of a passage has the wave beam of M different scanning angle or scanning position, may further comprise the steps:

A. each multi-beam synthesizer writes two-port RAM or three port rams with the number of echoes word line set signal respectively;

B. basis is worked as the array element parameter of prepass correspondence and the delay parameter that focal position parameter timesharing calculates M road wave beam in the same passage, is converted into the address of reading of RAM again; The delay parameter computing formula is: ${\mathrm{\&lambda;}}_i=\sqrt{{(L+X)}^2+({\mathrm{<figure-callout\; id="2"\; label="K"\; filenames="HSA00000130406700011.png,HSA00000130406700024.png"\; state="\{\{state\}\}">K</figure-callout>}}_2+K_3)\&CenterDot;Y}$

Time-delay table is shown: ${\mathrm{\&tau;}}_i=\frac{(L-{\mathrm{\&lambda;}}_i)}{c}$

Time-delay is converted into sampling pulse unit: $n_i=\frac{(L-{\mathrm{\&lambda;}}_i)}{c}{F}_s$

Input parameter form at the difference probe:

Probe	??K 2	??K 3	??X	??Y
					Protruding battle array	??L	??R	??0	??2R(1-cos(θ i-θ r))
Linear array	??0	??1	??0	??(x i-x r) 2
					Phased array	??L	??0	??x i	??-2x i(1+sinθ r)

Wherein: λ _i---radius-of-curvature, L---focal length, the θ that be the sound path from array element i to focal point F, R _r---receive angle, the θ of the emission of line and aperture center _i---angle, the x of i array element and aperture center emission _i---spacing, the x at center, i array element range aperture _r---receiving distance, the c of line and aperture center---velocity of sound is approximately 1540m/s in tissue,

C. in the time of a write cycle time,, produce the time delayed signal output of M road according to the address is read the process time-delay in turn from RAM the echo data of reading that calculates;

D. the M road time delayed signal output timesharing that produces in the same passage passed through an interpolating unit and a weighted units;

E. first wave beam that all multi-beam synthesizers are produced is superposed to the first synthetic wave beam,

Second wave beam that all multi-beam synthesizers are produced is superposed to the second synthetic wave beam,

……

M the wave beam that all multi-beam synthesizers are produced is superposed to the synthetic wave beam of M,

Finishing of the wave beam overlap-add operation timesharing of an above-mentioned M wave beam at same sum unit pipeline system;

F. Shu Chu M road beam signal still passes past next stage sum unit or carries out signal Processing and Flame Image Process in the mode of time-sharing multiplex.

The read frequency of described two-port RAM or three port rams is M times of write frequency.

Patent 201010133657.7 is scheme and the pipeline system work of adopting delay parameter to calculate in real time, by pattern control and input parameter configuration, makes the delay parameter design cell go for protruding battle array, linear array and phased array probe.But three multipliers in the calculating of delay unit, have been adopted, subtracter of two totalizers and the computing of an extraction of square root.The present invention provides improved delay parameter computing method on patent 201010133657.7 bases, delay parameter computing unit of the present invention has adopted two multipliers, three totalizers and the computing of an extraction of square root, reduced by a multiplier than it original scheme, handle at every FPGA under the situation of 16 signalling channels, can save 16 multipliers, therefore, can realize multibeam technique with lower cost.

The present invention adopts delay parameter to calculate in real time and the pipelining mode, can effectively reduce the memory space of resource occupation and minimizing parameter.Delay parameter calculation element simultaneously proposed by the invention makes it to be used in different types of probe by the structure that pattern control can change counting circuit very easily.

Description of drawings

The synthetic synoptic diagram of multi-beam that Fig. 1 calculates in real time for delay parameter of the present invention;

The geometric figure synoptic diagram that Fig. 2 calculates for convex array probe time-delay of the present invention;

The geometric figure synoptic diagram that Fig. 3 calculates for linear array probe time-delay of the present invention;

The geometric figure synoptic diagram that Fig. 4 calculates for phased array probe time-delay of the present invention;

Fig. 5 is a delay parameter computing unit synoptic diagram of the present invention;

Fig. 6 adopts four wave beam delay parameter computing unit synoptic diagram of parallel mode for the present invention;

Fig. 7 adopts four wave beam delay parameter computing unit synoptic diagram of pipeline system for the present invention;

Fig. 8 is delay time four beam synthesizer synoptic diagram of computing unit of the present invention;

The multiple-beam system block diagram that Fig. 9 calculates for the real-time delay parameter of the present invention.

Embodiment

With embodiment the present invention is described in further detail with reference to the accompanying drawings below:

Fig. 1 is the dynamic delay circuit diagram of echoed signal.Through road echoed signal behind AFE (analog front end) 200 and the analog to digital converter 300, by every straight processing unit 400, the filtering low frequency component, under the control of writing controller 500, produce linear write address then by counter, echoed signal is write the dual port RAM 501 that is used for storing echoed signal continuously, then by read-out controller 502 according to the address of reading that the output amount of delay of time-delay computing unit 600 produces RAM, read echoed signal through time-delay.Read the address and comprise integral part and fraction part, integral part is as the address of reading of RAM, and fraction part is as the interpolation coefficient as read output signal, to realize that delay precision is higher than the integer sampling period.Adopt 2 binary fractions in this programme, the process interpolating unit is to obtain the delay precision in 1/4th sampling periods.The interpolation coefficient of interpolating unit 700 is provided by read-out controller 502.

The emphasis of present embodiment is exactly the design of time-delay computing unit 600.The time-delay computing unit 600 be according to when the prepass correspondence first parameter is fallen and the focal position parameter calculates amount of delay in real time, be used for controlling the read operation of dual port RAM 501 and the interpolation arithmetic of back.Synthetic for the wave beam on M road, being calculated by delay parameter computing unit 600 of the delay parameter timesharing on M road read the echo data through having delayed time then successively from dual port RAM 501.It is synthetic to carry out wave beam after echo data carries out interpolating unit 700 and weighted units 800 computings again, and the echoed signal of each passage is superposeed.In said process, reading into the synthetic echoed signal afterwards of wave beam from dual port RAM 501 all is to transmit with the form of time-sharing multiplex, when needs, by the 1-M divider one tunnel echoed signal is divided into M road echoed signal again, can reduces the occupancy of hardware resource so to greatest extent.

The realization of computing unit the most important thing is in the multi-beam synthetic schemes of present embodiment to delay time.Fig. 2, Fig. 3, Fig. 4 have provided the geometric representation that the delay parameter of respectively popping one's head in calculates.In the focusing algorithm of multi-beam, FPGA need calculate i array element and arrive the sound path l that receives focal point F _i,

L at the difference probe _iComputing formula as follows:

Protruding battle array: ${\mathrm{\&lambda;}}_i=\sqrt{{(R+L)}^2+R^2-2(R+L)R\cos ({\mathrm{\&theta;}}_i-{\mathrm{\&theta;}}_r)}$

Linear array: ${\mathrm{\&lambda;}}_i=\sqrt{{\mathrm{<figure-callout\; id="2"\; label="L"\; filenames="HSA00000130406700011.png,HSA00000130406700024.png"\; state="\{\{state\}\}">L</figure-callout>}}^2+{(x_i-x_r)}^2}$

Phased array: ${\mathrm{\&lambda;}}_i=\sqrt{{x_i}^2+L^2-2x_{i}L\sin {\mathrm{\&theta;}}_r}$

Time-delay table is shown: ${\mathrm{\&tau;}}_i=\frac{(L-{\mathrm{\&lambda;}}_i)}{c}$

Time-delay is converted into sampling pulse unit: $n_i=\frac{(L-{\mathrm{\&lambda;}}_i)}{c}{F}_s$

Annotate:

1) R---radius-of-curvature

2) L---focal length

3) θ _r---receive the angle of line and aperture center emission line

4) θ _i---the angle of convex array probe i array element and aperture center emission line

5) x _i---the spacing at linear array or center, phased array probe i array element range aperture

6) x _r---linear array probe receives the distance of line and aperture center

7) c---the velocity of sound is approximately 1540m/s in tissue

At above-mentioned three computing formula, we can construct a general calculation formula:

$l_i=\sqrt{{(L+X)}^2+(K_2+K_3)\&CenterDot;Y}$

According to this general calculation formula, we only need input parameter K ₂, K ₃, X, the Y sound paths that just can finish different probes calculate, these computing method need the computing of an extraction of square root, two multipliers and three totalizers, thereby the FPGA that more helps scheme realizes.Circuit structure shown in Fig. 5 can be used for calculating the sound path λ of convex array probe, linear array probe and phased array probe _iThe corresponding focal length of input parameter L among Fig. 5.Input parameter K ₂, K ₃, X, Y have different forms according to probe kind difference.Table 1 has provided the input parameter form at the difference probe.

Table 1: the input parameter form of different probes

Probe	??K 2	??K 3	??X	??Y
					Protruding battle array	??L	??R	??0	??2R(1-cos(θ i-θ r))
Linear array	??0	??1	??0	??(x i-x r) 2
					Phased array	??L	??0	??x i	??-2x i(1+sinθ r)

Four parameter K in the table 1 ₂, K ₃, X, Y be input parameter, according to the difference of probe kind, four input parameters are carried out corresponding configuration, thereby draw the sound path of various probes.Have only parameter Y relevant in the scheme of Fig. 5, when adopting pipeline system work, only need Y to switch the time-sharing multiplex that just can support different beams according to different beams with wave beam.The unit of all input quantities in the table 1 all is a length, so actual computation will be quantified as unit pulse, also promptly with the recurrence interval number as unit.Specific algorithm is that all input quantities are multiplied by quantizing factor F _s/ c.Here F _sBe sample frequency, c is the velocity of sound.In order to guarantee computational accuracy, all amounts all keep 3 binary fractions.

Fig. 6 has provided the block diagram of the four wave beam delay parameters calculating Parallel Implementation mode of improvement project.Have only among Fig. 6 the delay parameter output of 601, four wave beams of a public part corresponding respectively module 602,603,604,605.Four parameter Y that the wave beam position angle is relevant ₁, Y ₂, Y ₃, Y ₄Input to 601,602,603,604 respectively.

Fig. 7 has provided the block diagram of the four wave beam delay parameters calculating pipeline work of improvement project.A public part 601 and a wave beam calculating section 602 are arranged, the parameter Y relevant among Fig. 7 with wave beam ₁, Y ₂, Y ₃, Y ₄Input to module 602 by Port Multiplier 606.It is 4 times that input parameter L changes that Port Multiplier is selected the switching frequency of signal Y-SEL.Clock signal C K and Y-SEL have same frequency.Can calculate delay parameter to four road wave beams respectively for each focal length value like this.

Fig. 8 has provided the block diagram of four beam synthesizers of an application drawing 7.In the figure, 100 pairs of sampling pulses of ripple counter are counted, and have write down the distance that ultrasound wave is advanced, so be called ripple counter.The output of row wave technology device is as the address that writes of dual port RAM 200.Because that as long as the capacity of dual port RAM holds the maximum address difference that writes and read is just much of that, so the capacity of general dual port RAM only need get 256 to 512.Write the address and read address auto-folder when counting to the end and be equivalent to an annular storage queue to starting point.Here our degree of depth of getting RAM is 512, so the write address of dual port RAM 200 only need connect low 9 of ripple counter 100.The echo data rf_datai of input according to write the address continuous write dual port RAM 200.The output L of ripple counter.

Expression as the degree of depth is driven into delay parameter computing unit 300 simultaneously.Delay unit is being squeezed under the pulse L_load effect, with the expression focal length amount L squeeze into, the frequency of L_load be the delay parameter computing unit clock calc_clk 1/4th.Also promptly under same focal length L, respectively the time-delay of four wave beams is calculated once.The input parameter K of time-delay computing unit ₂, K ₃, X do not change with the switching of wave beam.The output parameter Y relevant with wave beam is labeled as Y respectively for four wave beams ₁, Y ₂, Y ₃, Y ₄Under the control of 4-1 Port Multiplier 310, switch.Selection by the beam selection signal beam_sel controlled variable of ripple counter 100 output.At parameter Y ₁-Y ₄In turn in the process of input, delay parameter computing unit 300 calculates the delay parameter of each wave beam with pipeline system, and delay parameter is squeezed into the registers group 330 of back in turn, and each register is expressed as delay1 delay4 respectively.2-4 code translator 320 decoding beam_sel, four tunnel control outputs of generation are selected delay1-delay4.The value of delay1 delay4 is latched into latch 340 by last negative edge of squeezing into pulse, and purpose is to remain unchanged in the cycle a focal length variations for the value that keeps delay1delay4.The value Input Address computing unit 350 of delay1 delay4 calculates corresponding RAM in conjunction with focal length L and reads the address.In a write cycle, address calculation 350 must be respectively calculated each wave beam and is read the address once and read data from dual port RAM.Therefore, the frequency of read pulse rd_clk is to write four times of pulse wr_clk.If wr_clk is 40MHz, then rd_clk is 160MHz.Squeezed into register 210 to 240 in turn from the data that dual port RAM 200 is read.Because the needs of interpolation have also kept historical data in register 250 to 280.The historical data that keeps is not limited to have only two-stage.Exponent number difference according to interpolation algorithm can keep multistage.Such as 6 rank interpolation, keep 6 continuous output datas.The data of reading output to the interpolation and the weighted units 500 of pipeline system by 4-1 Port Multiplier 400.The interpolation coefficient of interpolation weighted units is provided by address calculation 350.What weighted data wt can calculate arrives, also can calculated in advance good, is stored in the external storage, reads in from external storage in real time in the reception process.Because it is very fast that the variation of weighted value does not need, change 64 times such as the sweep trace of 25cm, therefore, preserve weighted value and can't take too many storage resources.The data of coming out from interpolation weighted calculation unit 500 have been through time-delay and four wave beam echo datas time-sharing multiplex.These data are sent to the sum unit 600 of pipeline system work and the output of other N-1 unit sue for peace together, obtain the four beam data output of time-sharing multiplex at last.

Fig. 9 has provided a synthetic B ultrasonic system chart of four wave beams that calculates in real time based on delay parameter.Array energy transducer 10 among Fig. 9 is 128 array elements.Beam synthesizer 60 1 has 64 passages.Emission has the pulse signal of time-delay to radiating circuit 50 to one group of specific array element (become and activate array element) under the control of controller 70, to realize focusing on emission.The gating that activates the echoed signal process analog switch 20 of array element is sent to T/R switch 30.The effect of T/R switch 30 is that the high-voltage signal of isolating emission avoids causing the amplifying circuit saturation jamming of back.Be sent to analog front circuit 40 through the simulating signal of T/R switch 30 and amplify and handle, AFE (analog front end) has comprised prime amplifier, temporal gain control amplifier (TGC) and adc circuit.Be converted to digital signal through amplifying signal and be sent to beam synthesizer 60.Beam synthesizer is one and has comprised 64 tunnel as shown in Figure 8 circuit structures.Beam synthesizer 60 is delayed time 64 road input signals.Four tunnel beam data through time-delay are exported on each road, and four circuit-switched data are sent to sum unit 61 with the form of time-division multiplex.Sum unit 61 is synthesized four tunnel beam data with pipeline system.Beam data after its four of being output as time-division multiplex synthesize.This data stream branches into four the tunnel through divider (DEMUX) 80.Be sent to four tunnel quadrature demodulation unit 81 to 84 and signal processing unit 85 to 89 respectively.Four sweep traces of Xing Chenging are given digital scan converter (DSC) 90 at last.Digital scan converter 90 is converted to the raster data with rectangular coordinate with scan-line data, and is sent to image buffer memory 92 by read-write controller 91.Under the control of controller 70, notice host computer 73 is by pci bus reads image data and demonstration.Control data is also by passing to controller 70 under the pci bus.Being used for focusing on the time-delay parameters calculated is stored at parameter storage 71.Before each scanning beginning, controller 70 is sent to the synthetic passage of each wave beam with all parameters, and sends control timing and control synthetic the carrying out of whole wave beam.With the example among Fig. 9, can keep under the nondecreasing condition of image line density, the frame frequency of B ultrasonic system is improved 4 times.This will improve the image quality of B ultrasonic for locomotive organ in the human body such as heart greatly.

Those skilled in the art do not break away from essence of the present invention and spirit, can there be the various deformation scheme to realize the present invention, the above only is the preferable feasible embodiment of the present invention, be not so limit to interest field of the present invention, the equivalent structure that all utilizations instructions of the present invention and accompanying drawing content are done changes, and all is contained within the interest field of the present invention.

Claims (2)

1. a delay parameter calculates and the multi-beam synthesis method of streamline in real time, it has a multi-beam synthesizer at least, a multi-beam synthesizer is accepted the ultrasonic echo of a passage, the ultrasonic echo of a passage has the wave beam of M different scanning angle or scanning position, it is characterized in that may further comprise the steps:

A. each multi-beam synthesizer writes two-port RAM or three port rams with the number of echoes word line set signal respectively;

B. basis is worked as the array element parameter of prepass correspondence and the delay parameter that focal position parameter timesharing calculates M road wave beam in the same passage, is converted into the address of reading of RAM again; The delay parameter computing formula is:

Time-delay table is shown:

Time-delay is converted into sampling pulse unit:

Input parameter form at the difference probe:

Probe ??K ₂ ??K ₃ ??X ??Y Protruding battle array ??L ??R ??0 ??2R(1-cos(θ _i-θ _r)) Linear array ??0 ??1 ??0 ??(x _i-x _r) ² Phased array ??L ??0 ??x _i ??-2x _i(1+sinθ _r)

Wherein: λ _i---convex array probe radius-of-curvature, L---focal length, the θ that be the sound path from array element i to focal point F, R _r---receive angle, the θ of line and aperture center emission line _i---angle, the x of i array element and aperture center emission line _i---spacing, the x at center, i array element central point range aperture _r---linear array probe receives distance, the c of line and aperture center---velocity of sound is approximately 1540m/s in tissue;

C. in the time of a write cycle time,, produce the time delayed signal output of M road according to the address is read the process time-delay in turn from RAM the echo data of reading that calculates;

D. the M road time delayed signal output timesharing that produces in the same passage passed through an interpolating unit and a weighted units;

E. first wave beam that all multi-beam synthesizers are produced is superposed to the first synthetic wave beam,

Second wave beam that all multi-beam synthesizers are produced is superposed to the second synthetic wave beam,

M the wave beam that all multi-beam synthesizers are produced is superposed to the synthetic wave beam of M,

……

Finishing of the wave beam overlap-add operation timesharing of an above-mentioned M wave beam at same sum unit pipeline system;

F. Shu Chu M road beam signal still passes past next stage sum unit or carries out signal Processing and Flame Image Process in the mode of time-sharing multiplex.

2. the multi-beam synthesis method of a kind of delay parameter according to claim 1 calculating in real time and streamline is characterized in that: the read frequency of described two-port RAM or three port rams is M times of write frequency.

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