CN205645810U - 集成电子器件 - Google Patents

集成电子器件 Download PDF

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CN205645810U
CN205645810U CN201520949560.1U CN201520949560U CN205645810U CN 205645810 U CN205645810 U CN 205645810U CN 201520949560 U CN201520949560 U CN 201520949560U CN 205645810 U CN205645810 U CN 205645810U
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S·保利洛
G·塔利亚布埃
S·D·马里亚尼
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STMicroelectronics SRL
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    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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Abstract

为了制造集成电子器件(5)，第一材料的保护层(20)形成在具有不平坦表面(6)的主体(3,6)上方；第二材料的介电层(22)形成在保护层上方，第二材料相对于第一材料可被选择性地蚀刻；第三材料的中间层(23)形成在第一介电层上方，第三材料相对于第二材料可被选择性地蚀刻；第四材料的第二介电层(24)形成在中间层上方，第四材料相对于第三材料可被选择性地蚀刻；通孔(35)形成为穿过第二介电层、中间层、第一介电层和保护层；以及导电材料的电接触件(4)形成在通孔中。

Description

集成电子器件
技术领域
本实用新型涉及半导体技术，尤其集成电子器件。
背景技术
如所知道的，在电子部件(尤其是非常小尺寸的CMOS器件，诸如栅极宽度小于0.18μm的器件)的制造中，频繁使用无边界(borderless)接触技术。该技术包括在操作区域上方沉积通常为氮化硅的保护层(其还用作蚀刻停止)，并且在沉积被平面化的金属前介电层(例如，USG(非掺杂硅玻璃)和BPSG(硼磷硅玻璃))之前扩散器件。因此，通过在介电层中和保护层中形成通孔然后沉积互连导电层来获取穿过绝缘层的接触件。具体地，通过使用光刻胶掩膜顺次且选择性地首先蚀刻介电层，蚀刻自动停止在保护层上，然后蚀刻保护层来形成通孔(例如，参见US 6890815)。
尽管被广泛使用，但所描述的工艺不总是最佳的。实际上，如果集成器件不是平面的而是突出或凹陷结构和区域，则衬底的表面具有不可忽略的层级差异，因此介电层在各个区域中具有明显不同的厚度；即，在衬底的突出区域较薄且在凹陷区域较厚。
在一些情况下，介电层的厚度差甚至可以相当可观，从200nm至甚至2μm。
于是，蚀刻介电质的较厚区域比较厚区域需要更多的时间。因此，为了确保较厚区域中介电层的完全去除，即使在完全局部去除之后在薄区域中继续介电质的蚀刻。在这些区域中，如果现有的层级差异较大，例如大于300nm，尽管相对于氮化物对介电质具有蚀刻选择性，但保护层仍然会受到损伤。
这种损伤是不利地，在这些区域中，在用于完成接触件的通孔 的随后蚀刻保护层期间，会发生下方区域不期望的过蚀刻，这导致最终器件的电特性的劣化，例如由于场氧化物的过度蚀刻而导致部件的各个区域的短路。
上述问题尤其困扰新摩尔定律器件，其特征在于栅极宽度小于0.18μm，有时利用结构的三维以尽可能地减小尺寸。
通常，所讨论的问题还会困扰其他器件，其由于缺乏金属前介电层下方的多个结构的平坦型，所以具有不同厚度的介电层。
为了解决该问题，已知将保护层的厚度增加使其在介电层的蚀刻期间不被显著去除的值，甚至在介电层较薄的区域中。然而，增加保护层的厚度是不利的并且至今为止是不期望的，因为该层的厚度影响器件的电特性。事实上，氮化物保护层的厚度确定MOS晶体管的栅极区域上的应力，影响其电特性。另一方面，修改电部件以限制这种影响不是总可以的并且任何情况下都是成本较高的。
实用新型内容
本实用新型的目的在于提供一种克服现有技术缺陷的制造工艺。
根据本实用新型，提供了一种用于制造集成电子器件的工艺以及由此获得的微集成电子器件。
根据一个实施例，一种集成电子器件，包括：主体(3,6)，具有不平坦的表面；第一材料的保护层(20)，位于主体(3,6)上；第二材料的第一介电层(22)，位于保护层上，第二材料相对于第一材料是选择性地可蚀刻的；第三材料的中间层(23)，位于第一介电层上，第三材料相对于第二材料是选择性地可蚀刻的；第四材料的第二介电层(24)，位于中间层上，第四材料相对于第三材料是选择性地可蚀刻的；通孔(35)，延伸穿过第二介电层、中间层、第一介电层和保护层；以及电接触区域(40)，位于通孔中。
根据一个实施例，集成电子器件(5)是MOS晶体管。
根据一个实施例，第一材料和第三材料是在氮化硅和氮氧化物 之间选择的，以及第二材料和第四材料是氧化硅。
根据一个实施例，保护层(20)是无边界接触保护层。
根据一个实施例，保护层(20)、第一介电层(22)、以及中间层(23)具有均匀的厚度，并且第二介电层(24)是平坦的。
根据一个实施例，中间层(23)具有被包括在10和400nm之间的厚度，例如在20和100nm之间。
根据一个实施例，在接触件具有不同层级的器件中，介电层被划分为两个部分：第一(底)层，位于保护层上方，其不是平整的；以及第二(顶)层，其是平整的以具有平坦表面。在第一和第二介电层之间插入中间层，其中中间层具有不同材料且相对于第一和第二介电层(它们彼此相同)具有不同的蚀刻选择性。中间层(例如，氮化硅)具有与衬底上的层级差异相关的厚度。
用于限定接触件的蚀刻工艺具有各种步骤。初始地，以相对于中间层的材料具有选择性的方式来蚀刻第二介电层。蚀刻自动终止于中间层。由于厚度差异而导致中间层的可能过蚀刻不会产生问题，因为对其的可能损伤对最终的器件不具有影响。然后，进行中间层的蚀刻、第一介电层的蚀刻以及随后保护层的蚀刻。由此执行这些底层的蚀刻而不产生任何问题，因为它们具有均匀的厚度。
以这种方式，中间层的厚度能够补偿由于平面化介电层(第二介电层)的差异厚度而引起的各种理论蚀刻时间。中间层、第一介电层和保护层的后续蚀刻可以在均匀的厚度上进行，因此不存在过蚀刻的任何风险。
附图说明
为了更好地理解本实用新型，现在仅参照附图通过非限制实例描述优选实施例，其中：
图1至图5示出了集成电子器件的顺序制造步骤中穿过晶圆截取的截面。
具体实施方式
图1示出了集成电子部件5(这里为CMOS晶体管，也可以是MOS晶体管，其具有使用无边界接触解决方案的绝缘栅区域6)的半导体材料的晶圆1。在该图中，各个区域没有按比例绘制。
晶圆1包括衬底3(例如，硅)，其可以设置有硅化物部分(未示出)并具有不平坦的顶面4。金属前绝缘结构10在衬底3上方延伸。
衬底3容纳操作区域(未示出，例如注入和/或扩散)以及可能的绝缘区域(也未示出)，它们与绝缘栅区域6一起形成CMOS晶体管5。
如所提到的，衬底3的顶面4是不平坦的并具有处于不同层级的区域。详细地，在所示实例中，顶面4包括第一部分15，其处于第一层级L1(例如，相对于衬底3的底面11进行测量)在绝缘栅区域6下方延伸。衬底3的顶面4的第二部分16被布置为在第一表面部分15旁边，经由圆角部分17与其接合，并且被布置为处于低于第一层级L1的第二层级L2。
于是，在第一层级L1和第二层级L2之间存在层级差异ΔL，其通常在200nm和2μm之间，例如300nm。
通过绝缘栅区域6的顶面形成又一层级差异(从金属前绝缘结构10可以看出)。该层级差异(在平坦结构中可忽略)由于通常小于250nm，这里将其增加至层级差异ΔL，进一步增加了与金属前绝缘结构10的顶面的最小距离处的接触点与最大距离处的接触点(这里为衬底3的顶面4的第二部分16)之间的垂直距离。
金属前绝缘结构10包括直接形成在表面4上的堆叠层，包括保护层20、第一绝缘层22、中间层23和第二绝缘层24。
保护层20以共形方式沉积在表面4上并由此跟随层级差异。其通常为氮化硅，例如使用LPCVD(低压化学气相沉积)技术来沉积，其通常具有小于100nm(例如20nn)的近似均匀的厚度。
第一绝缘层22通常为氧化硅，例如使用LPCVD技术或APCVD (大气压化学气相沉积)技术沉积的USG(未掺杂硅玻璃)或BPSG(硼-磷硅玻璃)。此外，第一绝缘层22具有近似均匀的厚度，并且其厚度可以选择具有足够的自由度，例如其可以在200和400nm之间。
中间层23通常为氮化硅或者一些其他材料，其可以相对于第一绝缘层22的材料选择性地被蚀刻；例如其可以为氮氧化物。中间层23例如使用LPCVD技术来沉积，并且具有近似均匀的厚度，其被设计为用作蚀刻停止(如以下详细解释的)。例如，中间层23的厚度可以包括在10和400nm之间，尤其在20和100nm之间。
第二绝缘层24通常为使用LPCVD技术或APCVD技术沉积的USG或BOSG。在沉积该层之后，例如经由CMP(化学机械抛光)对其进行平面化，使其顶面25基本平坦并且平行于衬底3的底面11。例如，在平面化之后，第二绝缘层24可以在第一表面部分15上方具有最小厚度，包括在100和800nm之间。
掩膜30(例如，光刻胶掩膜(图2))光刻地形成在图1的结构上。掩膜30覆盖金属前绝缘结构10的顶面25并具有开口31，其中将提供用于接触件的通孔。然后，例如使用BCl3来执行第一等离子体蚀刻，使得选择性地去除开口31下方的第二绝缘层24的部分。
即使上述蚀刻对中间层23的材料具有非常大的选择性，但层级差ΔL的存在会引起中间层23的过蚀刻，尤其在第一表面部分15上方，其中第二绝缘层24较薄。然而，基于估计的过蚀刻研究中间层23的厚度以不被完全去除。
然后(图3)，适当保持掩膜30，执行中间层23的第二等离子体蚀刻。由于相对于第一介电层22的材料的蚀刻选择性以及还由于第二蚀刻在所有点中去除中间层23的材料的近似均匀的厚度，该蚀刻完全去除开口31下方的中间层23的部分，停止于第一介电层22。
接下来(图4)，例如类似于第一蚀刻执行第三等离子蚀刻，用于去除开口31下方的第一介电层22并停止于保护层20。此外，对基本均匀的厚度进行第三蚀刻，其等于第一介电层22的厚度，因此 不具有任何危害。
最后，例如类似于第二蚀刻，执行第四等离子体蚀刻，用于去除保护层20。此外，对基本均匀的厚度进行第四蚀刻，其等于保护层20的厚度，因此不具有任何危害。以这种方式，完成穿过绝缘结构10的通孔35的形成。
接下来，制造接触件。为此，以已知方式，在通孔35内沉积金属材料(例如，钨)用于填充通孔。然后，在绝缘结构10上，沉积和图案化金属层(例如，铝或铜层)。由此得到通孔35中的金属接触区域40以及金属线41。如果设想工艺，则可以以已知方式形成其他金属。
如所描述的，由此得到的工艺和器件具有许多优势。
经由两个介电层22、23(由可选择性蚀刻的层分离)形成绝缘层防止对衬底上方的无边界保护层的任何损伤。得到该结果而不放弃无边界工艺并且不需要适应无边界保护层的厚度(尤其不需要增加该厚度)，因此该工艺不要求任何设计修改来适应器件的各个区域和部件的几何或电参数，因为中间层的厚度不对它们具有任何影响。
根据所使用的工艺，第一和第二介电层22、24的厚度不是关键的，并且中间层23可以布置为与保护层20具有任何距离，这对设计者不具有任何特定的约束。
最后，明显的是，在不背离在权利要求中限定的本实用新型的范围的情况下，可以对本文描述和示出的工艺和器件进行修改和变化。例如，中间层可以由不同材料(例如，氮氧化物)或一些其他材料(针对蚀刻具有选择性的期望特性)制成。

Claims (6)

1.一种集成电子器件，其特征在于包括：
主体(3,6)，具有不平坦的表面；
第一材料的保护层(20)，位于所述主体(3,6)上；
第二材料的第一介电层(22)，位于所述保护层上，所述第二材料相对于所述第一材料是选择性地可蚀刻的；
第三材料的中间层(23)，位于所述第一介电层上，所述第三材料相对于所述第二材料是选择性地可蚀刻的；
第四材料的第二介电层(24)，位于所述中间层上，所述第四材料相对于所述第三材料是选择性地可蚀刻的；
通孔(35)，延伸穿过所述第二介电层、所述中间层、所述第一介电层和所述保护层；以及
电接触区域(40)，位于所述通孔中。
2.根据权利要求1所述的器件，其特征在于所述集成电子器件(5)是MOS晶体管。
3.根据权利要求1或2所述的器件，其特征在于所述第一材料和所述第三材料是在氮化硅和氮氧化物之间选择的，以及所述第二材料和所述第四材料是氧化硅。
4.根据权利要求1或2所述的器件，其特征在于所述保护层(20)是无边界接触保护层。
5.根据权利要求1或2所述的器件，其特征在于所述保护层(20)、所述第一介电层(22)、以及所述中间层(23)具有均匀的厚度，并且所述第二介电层(24)是平坦的。
6.根据权利要求1或2所述的器件，其特征在于所述中间层(23)具有被包括在10和400nm之间的厚度，例如在20和100nm之间。
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