CN205594397U - Adjustable 555 o'clock base overlength delay circuit - Google Patents
Adjustable 555 o'clock base overlength delay circuit Download PDFInfo
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- CN205594397U CN205594397U CN201620428707.7U CN201620428707U CN205594397U CN 205594397 U CN205594397 U CN 205594397U CN 201620428707 U CN201620428707 U CN 201620428707U CN 205594397 U CN205594397 U CN 205594397U
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Abstract
Adjustable 555 o'clock base overlength delay circuit belongs to delay circuit technical field. The utility model relates to a solve present NE555 delay circuit the delay time influenced by resistance and capacitance, as if wanting to reach the problem that long -time time delay can influence the circuit stability. Connect reset button S between NE555 time base chip's 6 pins and 1 pin, reset button S and electric capacity C1 are parallelly connected mutually, and diode D1's positive pole is connected to NE555 time base chip's 1 pin, and diode D1's negative pole is connected to NE555 time base chip's 3 pins, and relay KM and diode D1 connect in parallel mutually, connecting resistance R1 between NE555 time base chip's 6 pins and 4 pins, potentiometre D2 connects between NE555 time base chip's 8 pins and 5 pins, and NE555 time base chip's 5 pins are connecting resistance R2's one end simultaneously, another termination power ground of resistance R2. The utility model relates to a delay circuit.
Description
Technical field
This utility model relates to base ultra-delay circuit during scalable 555, belongs to delay circuit technical field.
Background technology
Traditional NE555 delay circuit cannot realize long-time timing, reason be NE555 delay time T be connected
Resistance R is relevant with capacitance C, T=1.1*R*C, if wanting that reaching long-time time delay must increase resistance and electric capacity
Numerical value, but resistance and the excessive stability affecting circuit of capacitance, so traditional NE555 delay circuit is very
Difficult time delay was more than 30 minutes.
Summary of the invention
This utility model purpose is that the delay time in order to solve existing NE555 delay circuit is by resistance and capacitance
Impact, if wanting to reach the problem that long-time time delay can affect circuit stability, it is provided that during a kind of scalable 555, base overlength is prolonged
Time circuit.
Base ultra-delay circuit during scalable 555 described in the utility model, it includes base chip during NE555, and it also includes
Resistance R1, resistance R2, electric capacity C1, diode D1, potentiometer D2, relay K M and SR S,
During NE555,2 pins and 6 pins of base chip link together, 6 pins of base chip and 1 pin during NE555
Between connect SR S, SR S be in parallel with electric capacity C1, during NE555,1 pin of base chip connects two poles
The anode of pipe D1, during NE555,3 pins of base chip connect the negative electrode of diode D1, relay K M and diode
D1 is in parallel, and during NE555,1 pin of base chip connects power supply ground；
Resistance R1,4 pins and 8 of base chip during NE555 are connected between 6 pins and 4 pins of base chip during NE555
Pin links together, and is simultaneously connected with+12V power supply, potentiometer D2 be connected to base chip during NE555 8 pins and
Between 5 pins, during NE555,5 pins of base chip are simultaneously connected with one end of resistance R2, another termination electricity of resistance R2
Seedbed.
During NE555, base chip is NE555 time-base integrated circuit.
Electric capacity C1 is electrolysis condenser.
Advantage of the present utility model: this utility model simple in construction, cost is extremely low.It is on the basis of existing NE555 circuit,
Add the peripheral components of necessity, especially only by increasing a potentiometer and a resistance, enable circuit delay to increase
On the basis of about 1 hour, it is ensured that the stability in the large of circuit.
Accompanying drawing explanation
The circuit theory diagrams of base ultra-delay circuit when Fig. 1 is scalable 555 described in the utility model.
Detailed description of the invention
Detailed description of the invention one: present embodiment is described below in conjunction with Fig. 1, described in present embodiment, during scalable 555, base surpasses
Long-time-delay circuit, it includes base chip 1 during NE555, and it also includes resistance R1, resistance R2, electric capacity C1, diode
D1, potentiometer D2, relay K M and SR S,
During NE555,2 pins and 6 pins of base chip 1 link together, 6 pins and 1 of base chip 1 during NE555
Connecting SR S, SR S between pin to be in parallel with electric capacity C1, during NE555,1 pin of base chip 1 is even
Connect the anode of diode D1, during NE555 base chip 13 pins connect diode D1 negative electrode, relay K M with
Diode D1 is in parallel, and during NE555,1 pin of base chip 1 connects power supply ground；
Resistance R1,4 pins of base chip 1 during NE555 are connected between 6 pins and 4 pins of base chip 1 during NE555
Linking together with 8 pins, and be simultaneously connected with+12V power supply, potentiometer D2 is connected to during NE555 the 8 of base chip 1
Between pin and 5 pins, during NE555,5 pins of base chip 1 are simultaneously connected with one end of resistance R2, and resistance R2's is another
One termination power ground.
Detailed description of the invention two: embodiment one is described further by present embodiment, during NE555, base chip 1 is
NE555 time-base integrated circuit.
Detailed description of the invention two: embodiment one or two is described further by present embodiment, electric capacity C1 is electrochemical capacitor
Device.
Operation principle: this utility model adds a potentiometer D2 when NE555 at 5 pins of base chip 1, and goes here and there
Join a fixed value resistance R2, regulated the voltage of 5 pins by dividing potential drop so that the timing of circuit has extended.Work as circuit
After energising, the power supply of+12V is charged to electric capacity C1 by resistance R1 so that the current potential of 6 pins constantly raises, when 6 draw
When the current potential of foot is raised to the current potential of 5 pins, circuit reset timing terminates.Due to potentiometer D2 on 5 pin strings,
Make 5 pin voltage scalable even can reach identical with input voltage, therefore can improve 5 pin voltage values.5
Pin voltage improves base chip 1 threshold voltage when making NE555 and increases, thus the charging interval of electric capacity C1 be greatly prolonged.
Again by regulator potentiometer D2 so that D2 Yu R2 shares voltage, regulate the voltage of 5 pins so that chip valve threshold
Threshold voltage changes, and can regulate timing with this.When 2, when 6 pin voltage are less than 5 pin, the 3 high electricity of pin output
Flat, then the coil of relay K M obtains electric, and relay normally open contact closes, trigger relay action.When 2,6 pin voltage
During higher than 5 pin, 3 pin output voltage are 0.Relay K M coil losing electricity, relay normally open contact disconnects.Diode
D1 plays protection chip and the effect of relay coil.Because coil may cause counter electromotive force, this circuit than general connection,
As unsettled in 5 pins or by small capacitances ground connection connection, it is provided with the timing of longer time and can regulate.Timing start or
Reclocking, presses SR S so that electric capacity C1 discharges, circuit set.In this utility model, resistance R1 and
Resistance R2 all selects RTX 1/4W type carbon film resistor, relay K M can according to electrical equipment need select.
Claims (3)
1. base ultra-delay circuit during scalable 555, it includes base chip (1) during NE555, it is characterised in that
It also includes resistance R1, resistance R2, electric capacity C1, diode D1, potentiometer D2, relay K M and SR S,
During NE555,2 pins and 6 pins of base chip (1) link together, 6 pins of base chip (1) during NE555
With 1 connect SR S, SR S between pin and be in parallel with electric capacity C1, during NE555 the 1 of base chip (1)
Pin connects the anode of diode D1, and during NE555,3 pins of base chip (1) connect the negative electrode of diode D1, relay
Device KM is in parallel with diode D1, and during NE555,1 pin of base chip (1) connects power supply ground；
Resistance R1 is connected between 6 pins and 4 pins of base chip (1), during NE555 the 4 of base chip (1) during NE555
Pin and 8 pins link together, and are simultaneously connected with+12V power supply, and potentiometer D2 is connected to base chip (1) during NE555
8 pins and 5 pins between, during NE555,5 pins of base chip (1) are simultaneously connected with one end of resistance R2, resistance R2
Another termination power ground.
Base ultra-delay circuit during scalable 555 the most according to claim 1, it is characterised in that base core during NE555
Sheet (1) is NE555 time-base integrated circuit.
Base ultra-delay circuit during scalable 555 the most according to claim 1, it is characterised in that electric capacity C1 is electricity
Electrolysis condenser.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620428707.7U CN205594397U (en) | 2016-05-12 | 2016-05-12 | Adjustable 555 o'clock base overlength delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620428707.7U CN205594397U (en) | 2016-05-12 | 2016-05-12 | Adjustable 555 o'clock base overlength delay circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205594397U true CN205594397U (en) | 2016-09-21 |
Family
ID=56931634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620428707.7U Expired - Fee Related CN205594397U (en) | 2016-05-12 | 2016-05-12 | Adjustable 555 o'clock base overlength delay circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205594397U (en) |
-
2016
- 2016-05-12 CN CN201620428707.7U patent/CN205594397U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160921 Termination date: 20170512 |