CN205542815U - Ibc solar battery - Google Patents
Ibc solar battery Download PDFInfo
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- CN205542815U CN205542815U CN201620143393.6U CN201620143393U CN205542815U CN 205542815 U CN205542815 U CN 205542815U CN 201620143393 U CN201620143393 U CN 201620143393U CN 205542815 U CN205542815 U CN 205542815U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
Abstract
The utility model relates to a IBC solar battery and manufacturing method. This method includes: carry out the making herbs into wool processing with the first surface of N type silicon chip, polish its second surface, form boron doping source layer on the second surface, put into the thermal oxide stove with it and react, form p+ emitter layer and the borosilicate glass layer that stacks gradually on the second surface, form oxygen ambient silica layer on the first surface, adopt laser to get rid of the location's of second surface borosilicate glass and p+ projecting pole, put into phosphorus source diffusion furnace with N type silicon chip, form a n++ surface region on the second surface, form n+ surface layer and phosphorus silicon glass layer in proper order on the first surface, adopt laser to separate a p+ projecting pole and a n++ surface region on the second surface, get rid of borosilicate glass and phosphorus silicon glass, form the passivation layer on the surface respectively at N type silicon chip, on second passivation antireflection film layer respectively the preparation just, the negative electrode. Above -mentioned IBC solar battery and manufacturing method, simplifying processing flow and step.
Description
Technical field
This utility model relates to technical field of solar cells, particularly relates to a kind of IBC solar cell.
Background technology
Solar cell is a kind of optoelectronic semiconductor thin slice utilizing the sunlight direct generation of electricity, wherein, IBC
(Interdigitated back contact, back of the body knot) solar cell is high due to its conversion efficiency, the highest conversion
Efficiency is more than 24%, and therefore, IBC solar cell is always the important directions of solar cell research.
In the preparation technology of IBC solar cell, the step of most critical is boron diffusion and patterned formation.
Usually, boron diffusion uses Boron tribromide to be that boron source is diffused in tubular diffusion furnace.This diffusion way
For Double side diffusion, the tow sides at silicon chip all form p+ layer.Thus also need to before carrying out phosphorus diffusion later
Remove the p+ layer in front, additionally, the compactness of Pyrex layer that this diffusion way is formed is not enough to make
The barrier layer of reverse side when spreading for phosphorus, also needs to carry out mask in phosphorus diffusion process.Therefore, this diffusion
The technics comparing that mode causes IBC solar cell to be prepared is complicated.
Utility model content
Based on this, it is necessary to for the problem of the preparation technology how simplifying IBC solar cell, it is provided that a kind of
IBC solar cell.
A kind of IBC solar cell, including:
N-type silicon chip, described N-type silicon chip has matte and burnishing surface, and the matte side of described N-type silicon chip includes
N+ surface field layer, described n+ surface field layer is formed on described matte,
The burnishing surface side of described N-type silicon chip includes p+ emitter region, n++ surface field region and isolation area
Territory, described p+ emitter region is formed on described burnishing surface, and described area of isolation is launched with described p+ respectively
Territory, polar region and described n++ surface field region are adjacent, and described area of isolation extends in described N-type silicon chip,
The described top surface in n++ surface field region flushes with the burnishing surface of described N-type silicon chip, and described n++ table
Face field areas extends in described N-type silicon chip；
First passivated reflection reducing penetrates film layer and the second passivated reflection reducing penetrates film layer, and described first passivated reflection reducing penetrates film layer position
On described n+ surface field layer, described second passivated reflection reducing is penetrated film layer and is covered described p+ emitter region, described
N++ surface field region and described area of isolation；And
Anelectrode and negative electrode, described anelectrode and described negative electrode are respectively positioned on described second passivated reflection reducing and penetrate film
On layer, and described anelectrode extends to described p+ emitter region, and it extends to described p+ emitter region
Top surface, described negative electrode is to described n++ surface field region, and it extends to place, described n++ surface
The top surface in territory.
Above-mentioned IBC solar cell.
Wherein in an embodiment, the diffused sheet resistance of described n+ surface field layer is 80-300 Ω/sq.
Wherein in an embodiment, the degree of depth of described area of isolation is more than the degree of depth in described n++ surface field region.
Wherein in an embodiment, the degree of depth of described area of isolation is 1 micron to 40 microns.
Wherein in an embodiment, the width of described area of isolation is 1 micron to 100 microns.
Wherein in an embodiment, the diffused sheet resistance in described n++ surface field region is 20-80 Ω/sq.
Wherein in an embodiment, the matte of described N-type silicon chip is pyramid shape.
Wherein in an embodiment, described first passivated reflection reducing penetrates film layer and described second passivated reflection reducing penetrates film
The thickness of layer is 5 nanometer-15 nanometers.
Wherein in an embodiment, described first passivated reflection reducing penetrates film layer and described second passivated reflection reducing penetrates film
Layer is membranous layer of silicon oxide.
Wherein in an embodiment, also include the first silicon nitride layer and the second silicon nitride layer, described first nitrogen
SiClx layer is positioned at described first passivated reflection reducing and penetrates on film layer, and described second silicon nitride layer is positioned at described second passivation
On antireflection film layer.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the manufacture method of the IBC solar cell of an embodiment；
Fig. 2 is the structural representation after the N-type silicon chip making herbs into wool of an embodiment and polishing；
Fig. 3 is the structural representation after forming boron dopant source layer on the second surface of N-type silicon chip shown in Fig. 2；
Fig. 4 is that N-type silicon chip shown in Fig. 3 carries out the structural representation after reacting and spreading in oxidation furnace；
Fig. 5 is the structural representation after the second surface of N-type silicon chip carries out laser treatment shown in Fig. 4；
Fig. 6 is N-type silicon chip structural representation after phosphorus source diffusion furnace is diffused shown in Fig. 5；
Fig. 7 is the structural representation after the second surface of N-type silicon chip carries out laser treatment shown in Fig. 6；
Fig. 8 is the structural representation after N-type silicon chip shown in Fig. 7 removes Pyrex and phosphorosilicate glass；
Fig. 9 is that N-type silicon chip shown in Fig. 8 forms the structural representation after passivated reflection reducing penetrates film layer；
Figure 10 is the structural representation of the IBC solar cell that N-type silicon chip shown in Fig. 9 obtains after carrying out electrode preparation
Figure.
Detailed description of the invention
As it is shown in figure 1, the manufacture method of the IBC solar cell of an embodiment, including step:
S1: the first surface of N-type silicon chip is carried out making herbs into wool process, and the second surface of N-type silicon chip is carried out
Polishing.
Specifically, in this embodiment, first surface and the second surface of N-type silicon chip is respectively N-type silicon chip
Front and back.
Use flocking additive the first surface of N-type silicon chip is carried out texturing process, flocking additive be water,
The mixed solution of isopropanol, alkali and additive, wherein, alkali is sodium hydroxide, potassium hydroxide or tetramethyl
Ammonium hydroxide.In mass ratio, the content of each component in flocking additive is: sodium hydroxide 0.1%～3%,
Isopropanol 2%～10%, additive 0.01%～2%, remaining is water.In mass ratio, each component of additive
Content is: glucose, sodium gluconate or potassium gluconate 0.001%～3%, polyoxyethylene ether 100ppb～
8000ppb, sodium lactate or sodium citrate 0.001%～2%, propylene glycol 0.001%～2%, sodium silicate
0.01%～6%, sodium carbonate or sodium bicarbonate 0.001%～2%, remaining is water.
Specifically, N-type silicon chip is suspended on the solution of flocking additive, wherein, the first of N-type silicon chip
Surface contacts with flocking additive, thus the first surface of N-type silicon chip is carried out texturing process.
The second surface of N-type silicon chip is processed by shot blasting by the mode using chemical polishing.Use chemical polishing
When the second surface of N-type silicon chip is processed by shot blasting, utilize chemical reagent that silicon chip surface carries out chemistry rotten
Erosion, is polished.Wherein, chemical reagent is acid or alkali, and such as, acid is the mixing of Fluohydric acid. and nitric acid
Solution, alkali is sodium hydroxide, potassium hydroxide or organic base.
In the present embodiment, flocking additive is: the mass ratio of alkali, isopropanol, additive and water is
2.5:10:0.5:87.N-type silicon chip 110 is suspended in flocking additive, the first surface of N-type silicon chip 110
With flocking additive haptoreaction, controlling reaction temperature is 80 DEG C, and the response time is 20min so that N-type
The first surface of silicon chip 110 is the suede structure of Pyramid, as shown in Figure 2.Use chemical polishing
The second surface of N-type silicon chip 110 is polished by mode, and the chemical reagent used is sodium hydroxide, instead
It is 10 minutes-20 minutes between Ying Shi, as shown in Figure 2.
It should be noted that can also use the mode of mechanical polishing that the second surface of N-type silicon chip is thrown
Optical processing.
S2: form boron dopant source layer on the second surface of N-type silicon chip, and N-type silicon chip is put into thermal oxide
Stove is carried out react and spread, the second surface of N-type silicon chip is formed the p+ emitter layer that stacks gradually and
Pyrex layer, forms silicon oxide layer on the first surface of N-type silicon chip.
Specifically, by the method for spin coating spin coating boron source on the second surface of N-type silicon chip 110.Wherein,
Boron source is liquid boron source.Liquid boron source is the solution of boron-containing compound.Preferably, the solution of boron-containing compound
The oxide that effective ingredient is boron.Preferably, liquid boron source is the mixed solution of boron oxide and silicon oxide.
For boron oxide in the mixed solution of boron oxide and silicon oxide and the mass ratio of silicon oxide, it is not limiting as.
After boron source is uniformly spun to the second surface of N-type silicon chip 110, boron source is dried, dried
Cheng Zhong, solvent therein is vaporized completely or decomposes, and forms solid-state on the second surface of N-type silicon chip 110
Boron dopant source layer 120, as shown in Figure 3.Specifically, the mode of zone heating, heating temperature are used during drying
Degree is for 50-300 DEG C, and heat time heating time is 10 seconds-60 seconds.The thickness of the boron dopant source layer formed is 100 to receive
Rice-2000 nanometers.
It should be noted that on the second surface of N-type silicon chip 110 before spin coating boron source, it is also possible to first exist
One layer of precursor liquid of the second surface spin coating of N-type silicon chip 110, the solvent in this precursor liquid and the solvent in boron source
For similar solvent, thus the when of being more favorable for spin coating, boron source can be evenly distributed.
After the second surface of N-type silicon chip 110 forms boron dopant source layer 120, N-type silicon chip 110 is put
Entering and carry out in thermal oxidation furnace reacting and spreading, the boron source in boron dopant source layer 120 carries out oxide-diffused.
Specifically, the N-type silicon chip 110 that second surface is formed with boron dopant source layer 120 is inserted thermal oxide
In the groove of the quartz boat of stove.Wherein, each groove is only inserted a piece of N-type silicon chip 110, thus not only
Ensure the uniformity of diffusion of the second surface of N-type silicon chip 110, it is ensured that the first of N-type silicon chip 110
The uniformity of the thickness of the oxide layer that surface oxidation reaction in oxygen atmosphere is formed.
When N-type silicon chip 110 put into thermal oxidation furnace advance time, under oxygen atmosphere, boron-dopped layer 120
React with the silicon of the second surface of N-type silicon chip 110, form Pyrex layer 130, as shown in Figure 4.
Boron source in Pyrex layer 130 is diffused to the second surface of N-type silicon chip 110, obtains p+ emitter stage
Layer 140.Thus on the second surface of N-type silicon chip 110, sequentially form p+ emitter layer 140 and borosilicate glass
Glass layer 130.
Meanwhile, under oxygen effect, silicon and oxidation on the first surface of N-type silicon chip 110 react,
The first surface of N-type silicon chip 110 is formed silicon oxide layer 150.The thickness of silicon oxide layer 150 is 1 to receive
Rice-15 nanometers.
N-type silicon chip 110 is put in thermal oxidation furnace the condition carrying out reacting and spreading is: the temperature of thermal oxidation furnace
Degree is for 900-1000 DEG C, and the overall time that N-type silicon chip is reacted in thermal oxidation furnace is 90-180 minute, wherein,
The propelling time is 30-60 minute.It should be noted that according to the difference spreading square resistance needed for technique
Adjust temperature and the time of propelling, the diffusion square resistance sizes formed and temperature and propelling time correlation.
In the present embodiment, the temperature of thermal oxidation furnace is 960 DEG C, when the propelling time is 45 minutes, is formed
Diffusion square resistance be 65 Ω/sq.
Furthermore, it is necessary to explanation is, it is also possible to be after boron dopant source layer 120 carries out oxide-diffused, in heat
Oxidation furnace continues be passed through dry oxygen, carry out the oxidation of 30 minutes-60 minutes so that in N-type silicon chip 110
Silicon oxide layer 150 is formed on first surface.
S3: the specific region of second surface is carried out laser treatment, removes Pyrex and the institute of specific region
State p+ emitter stage.
Specifically, use the first laser parameter, the specific region of the second surface of N-type silicon chip 110 is carried out
Laser treatment, removes the Pyrex under this specific region correspondence and p+ emitter stage, thus on second surface between
Pyrex and p+ emitter stage it is dispersed with, as shown in Figure 5 every ground.Thus on second surface, only have subregion
Covered by p+ emitter stage and Pyrex successively, between adjacent p+ emitter stage and Pyrex, form groove,
The bottom surface of groove is second surface.It should be noted that the specific region on second surface is according to actual IBC
The structure of solar cell determines, this specific region is determined in advance.
Wherein, the first laser parameter is: optical maser wavelength is 500-550nm；Pattern is pulse mode or quasi-continuous
Pattern；Spot diameter is 1-500 micron.It should be noted that spot diameter is according to adjacent p+ emitter stage
With the width of formed groove determines between Pyrex.
Additionally, be not limiting as laser pulse width, it can be tens psecs, it is also possible to hundreds of psec.
Preferably, using wavelength is the green glow psec of 515 nanometers or 532 nanometers or short nanosecoud pulse laser
Carry out laser treatment.Thus ensure to remove the p+ emitter stage of the specific region on second surface and Pyrex
Meanwhile, the substrate of N-type silicon chip 110 will not be produced excessive damage.It should be noted that can also adopt
Use ultraviolet picosecond laser instrument.
In the present embodiment, the green ray picosecond laser device using wavelength to be 515 nanometers carries out laser treatment, swashs
The pulsewidth of light device is less than 10 psecs, thus ensures to remove p+ emitter stage and the boron of the specific region on second surface
While silica glass, the substrate of N-type silicon chip 110 will not be produced excessive damage.
Use laser technology localized region to process, utilize the spy such as heat effect and precise pattern of laser
Point, in the case of N-type silicon chip surface not being caused damage, removes p+ emitter stage and the borosilicate of specific region
Glass, thus avoid using the modes such as photoetching that the surface of N-type silicon chip is patterned process, use laser
Technology, simplifies the technological process that IBC solar energy makes.
S4: N-type silicon chip put in phosphorus source diffusion furnace, forms the n++ table stacked gradually on the specific area
Face field areas and phosphorosilicate glass region, sequentially form n+ surface field layer and phosphorosilicate glass layer on the first surface.
Specifically, the N-type silicon chip 110 after carrying out laser treatment in step S3 is put in phosphorus source diffusion furnace,
Carry out phosphorus diffusion.Diffusion conditions is: the temperature of diffusion furnace is 750-900 DEG C, and N-type silicon chip is at phosphorus source diffusion furnace
In overall time of being diffused be 60-129 minute, wherein, diffusion time is 20-60 minute.Thus phosphorus
Source is diffused in diffusion furnace.From step S3, the second surface upper part region of N-type silicon chip 110
Covered by p+ emitter stage and Pyrex successively, thus due to the barrier effect of Pyrex, these region phosphorus
Source diffusion is not entered.And covered by p+ emitter stage and Pyrex the most successively on the second surface of N-type silicon chip 110
The silicon on the surface with these regions of the region of lid, phosphorus source and N-type silicon chip 110 reacts, and forms phosphorus silicon
Glassy zone 111, meanwhile, phosphorosilicate glass region 111, to the diffusion inside of N-type silicon chip 110, forms n++
Surface field region 160, as shown in Figure 6.
As shown in Figure 6, simultaneously as be formed with silicon oxide layer 150 on the first surface of N-type silicon chip 110,
Thus silicon oxide layer 150 and phosphorus source react, form phosphorosilicate glass layer 170.Meanwhile, phosphorosilicate glass layer
Phosphorus source in 170 spreads to the first surface of N-type silicon chip 110, thus at the first table of N-type silicon chip 110
N+ surface field layer 180 is formed on face.Due to the existence of silicon oxide layer 150 on first surface, so that oxygen
Phosphorus source in the phosphorosilicate glass layer 170 that SiClx layer 150 and phosphorus source are formed after reacting be diffused time
Waiting, silicon oxide layer 150 still functions as the effect that part stops so that in same phosphorus diffusion process, the
On two surfaces, the diffused sheet resistance in formed n++ surface field region is less than the n+ surface field formed on first surface
The diffused sheet resistance of layer 180.On second surface, the diffused sheet resistance in formed n++ surface field region is 20-80 Ω/sq,
The diffused sheet resistance of the n+ surface field layer 180 formed on first surface is 80-300 Ω/sq.
In the present embodiment, the phosphorus source being passed through in diffusion furnace is phosphorus oxychloride.
S5: second surface is carried out laser treatment, separates the p+ emitter stage on second surface and n++ surface field
Region.
Specifically, as it is shown in fig. 7, use the second laser parameter, laser is used to be sent out by the p+ on second surface
Emitter-base bandgap grading and n++ surface field region 160 separate, between adjacent p+ emitter stage and n++ surface field region 160
Form area of isolation 190, thus avoid occurring the phenomenon of electric leakage.P+ emitter stage and n++ surface field region 160
Constitute doped layer.Wherein, the second laser parameter is: optical maser wavelength is 500-1100nm；Pattern is pulse mode
Formula or quasi-continuous pattern；Spot diameter is 1-100 micron.Wherein, spot diameter is according to the isolation area formed
The width in territory 190 determines.
In the present embodiment, the degree of depth of the area of isolation 190 formed be 1 micron to 40 microns, formed
The width of area of isolation 190 be 1 micron to 100 microns.It should be noted that the isolation area formed
Width on the cross section in territory 190 can be unequal, from the second surface of N-type silicon chip 110 to N-type silicon
On the direction of the inside of sheet 110, the width in the cross section of area of isolation 190 can be more and more less.
Additionally, in order to improve electrical property, the degree of depth of area of isolation 190 is greater than n++ surface field region 160
The degree of depth.
S6: remove the phosphorosilicate glass layer on first surface and the Pyrex on second surface and phosphorosilicate glass.
Specifically, from step S2 and step S4, the p+ emitter stage on the subregion of second surface
The above Pyrex that are coated with, and the above of n++ surface field region formed on second surface is coated with phosphorus
Silica glass, and it is coated with phosphorosilicate glass layer 170 on the n+ surface field layer 180 on first surface.In order to prevent
Phosphorosilicate glass and the Pyrex impact on the electrical property of IBC solar cell, need to remove phosphorosilicate glass and boron
Silica glass.
By RCA standard cleaning method, SPM (H2SO4、H2O2And H2The mixed solution of O), hydrogen fluorine
Acid and the mixed solution of ozone, hydrochloric acid and the chemical cleaning method such as the mixed solution of Fluohydric acid. or Fluohydric acid., remove
Pyrex and phosphorosilicate glass, as shown in Figure 8, and to the first surface of N-type silicon chip 110 and second surface
It is dried.
In the present embodiment, N-type silicon chip 110 is put in groove-type cleaning machine and is carried out, the chemistry of employing
Reagent is Fluohydric acid..
It should be noted that step S5 and step S6 can be exchanged, can first remove Pyrex and phosphorus silicon
Glass, then use the mode of laser the p+ emitter stage on second surface and n++ surface field region 160 to be separated.
S7: formed respectively on doped layer and n+ surface field layer the first passivated reflection reducing penetrate film layer and second passivation subtract
Reflective coating.
Specifically, in the present embodiment, in order to by the first surface of N-type silicon chip 110 and the electricity of second surface
Lotus saturated fall, doped layer and n+ surface field layer 180 form the first passivated reflection reducing respectively and penetrate film layer 210 He
Second passivated reflection reducing penetrates film layer 220, and the first passivated reflection reducing is penetrated film layer 210 and is positioned at n+ surface field layer 180, and second
Passivated reflection reducing is penetrated film layer 220 and is covered p+ emitter region, n++ surface field region 160 and area of isolation 190,
As shown in Figure 9.
In the present embodiment, in the groove of the quartz boat that N-type silicon chip 110 is inserted oxidation furnace, carry out dry oxidation,
The temperature of thermal oxidation furnace is 900-1000 DEG C, and the propelling time is 10-60 minute.Thus form the first passivated reflection reducing
Penetrate film layer 210 and the second passivated reflection reducing penetrates film layer 220.First passivated reflection reducing penetrates film layer 210 and the second passivation subtracts
Reflective coating 220 is silicon oxide layer, and its thickness is 5 nanometer-15 nanometers.
S8: penetrate at the second passivated reflection reducing and prepare positive and negative electrode on film layer respectively.
Specifically, in the present embodiment, by silk screen printing or induction electric plating method, subtract in the second passivation
Form anelectrode 230 and negative electrode 240 on reflective coating 220 respectively, and be sintered, such as Figure 10
Shown in.
Referring again to Figure 10, anelectrode 230 extends to p+ emitter region, and it extends to p+ emitter region
Top surface, negative electrode 240 is to n++ surface field region 160, and it extends to n++ surface field region 160
Top surface, anelectrode 230 becomes interdigitated arrangement with negative electrode 240.Gate line electrode is some, grid
Line electrode is distributed in the second passivated reflection reducing respectively and penetrates on film 220, in order to draw the electric current formed.Gate line electrode
Specifically include main gate line electrode and secondary gate line electrode.Wherein, the radical of positive and negative main gate line electrode is respectively 1-5
Root, width is 0.5mm-2.5mm；The radical of secondary gate line electrode is 50-150 root, and width is 30um
-150um。
It should be noted that in another embodiment, between step S7 and step S8, also include step
Rapid: to penetrate film layer 210 and the second passivated reflection reducing is penetrated and formed the first nitrogen on film layer 220 respectively at the first passivated reflection reducing
SiClx layer and the second silicon nitride layer.
Specifically, by plasma enhanced chemical vapor deposition method or atomic layer deposition method, in the first passivation
Form the first silicon nitride layer on antireflection film layer 210, and penetrate at the second passivated reflection reducing and on film layer 220, form the
Nitride silicon layer.This first silicon nitride layer and the second silicon nitride layer are silicon dioxide, silicon nitride, titanium dioxide
The monofilm that titanium or aluminium oxide are formed, or be that silicon dioxide, silicon nitride, titanium dioxide and aluminium oxide are appointed
What two or more multilayer film formed, the thickness of the first silicon nitride layer is 65 nanometer-80 nanometers,
The thickness of the second silicon nitride layer is 80 nanometer-150 nanometers.Preferably, the first silicon nitride layer and the second silicon nitride
Layer is silicon nitride layer, thus is passivated further, reduces reflection.
Below in conjunction with specific embodiment, the manufacture method of IBC solar cell is further elaborated.
Embodiment 1
Using 156 millimeters of x156 millimeters, resistivity is the N-type silicon chip 110 of 2-15 Ohms per centimeter, by N
Type silicon chip 110 is put in monocrystalline etching device, and N-type silicon chip 110 is suspended in flocking additive reaction, N-type
The front of silicon chip 110 contacts with flocking additive, and controlling reaction temperature is 80 DEG C, and the response time is 20min,
Making the first surface of N-type silicon chip 110 is the suede structure of Pyramid, and flocking additive is: alkali,
The mass ratio of isopropanol, additive and water is 2.5:10:0.5:87；
Utilizing sodium hydroxide solution to be polished the second surface of N-type silicon chip 110, the time is 15 minutes,
After polishing, the sodium hydroxide on second surface is cleaned and is dried；
N-type silicon chip 110 1 milliliter of boron source of second surface spin coating (boron oxide and the mixed solution of silicon oxide,
Model is DS-2), and be baked to, the mode using stagewise intensification to dry, dry temperature and be 50-200 DEG C,
Being divided into five sections to heat, the drying time of every section is 10 seconds, the thickness of the boron dopant source layer 120 formed
It is 100 nanometers；
The stone that the N-type silicon chip 110 being formed with boron dopant source layer 120 on second surface is inserted in thermal oxidation furnace
In the groove of Ying Zhou, carrying out reacting and spreading, the temperature of thermal oxidation furnace is 960 DEG C, and the propelling time is 45 minutes,
Thus sequentially form p+ emitter layer 140 and Pyrex layer 130, p+ emitter layer 140 on a second surface
Diffusion square resistance be 65 Ω/sq, meanwhile, on the first surface formed silicon oxide layer 150, silicon oxide layer
The thickness of 150 is 5 nanometers；
The specific region of second surface is carried out at laser by the green ray picosecond laser device using wavelength to be 515 nanometers
Reason, removes the Pyrex corresponding to this specific region and p+ emitter stage, and the zlasing mode used is pulse
Pattern, the pulsewidth of laser instrument is less than 10 psecs, and spot diameter is 500 microns；
N-type silicon chip 110 being put in phosphorus source diffusion furnace, the phosphorus source used is phosphorus oxychloride, at diffusion furnace
Temperature be at 890 DEG C spread 30 minutes, on the second surface of N-type silicon chip 110 not by p+ emitter stage
The region covered with Pyrex forms the phosphorosilicate glass region and n++ surface field region 160 stacked gradually, with
Time, the first surface of N-type silicon chip 110 sequentially forms n+ surface field layer 180 and phosphorosilicate glass layer 170,
The diffusion square resistance in n++ surface field region 160 is 70 Ω/sq, the diffusion square resistance of n+ surface field layer 180
It is 200 Ω/sq；
Optical maser wavelength be the green ray picosecond laser device of 515 nanometers, zlasing mode be pulse mode and hot spot
Under second laser parameter of a diameter of 60 microns, by the p+ emitter stage on second surface and n++ surface field region
160 separate, and form area of isolation 190, isolation between adjacent p+ emitter stage and n++ surface field region 160
The degree of depth in region 190 is 25 microns, and the width of area of isolation is 80 microns；
N-type silicon chip 110 is put in groove-type cleaning machine, removes N-type silicon chip 110 by hydrofluoric acid solution
Phosphorosilicate glass layer 170 on first surface and the phosphorosilicate glass on second surface and Pyrex, then spend
Ionized water is carried out, and puts and be dried at 50 DEG C in an oven after cleaning；
Then, in the groove of the quartz boat that N-type silicon chip 110 is inserted oxidation furnace, two-sided low-temperature oxidation is carried out,
Doped layer and n+ surface field layer 180 are formed the first passivated reflection reducing respectively and penetrates film layer 210 and the second passivation subtracts
Reflective coating 220, the first passivated reflection reducing penetrates film layer 210 and the second passivated reflection reducing is penetrated film layer 220 and is silicon oxide
Layer, its thickness is 10 nanometers, and oxidizing temperature is 980 DEG C, and oxidization time is 30 minutes；
By the method for silk screen printing, penetrate film layer 210 and the second passivated reflection reducing penetrates film layer at the first passivated reflection reducing
Form anelectrode 230 and negative electrode 240 on 220 respectively, and be sintered, thus obtain the IBC sun
Battery, the radical of main gate line electrode is 5, and width is 1mm；The radical of secondary gate line electrode is 100,
Width is 100um.
As shown in Figure 10, the IBC solar cell 100 of an embodiment includes that N-type silicon chip 110, first is passivated
Antireflection film layer the 210, second passivated reflection reducing penetrates film 220, anelectrode 230 and negative electrode 240.
Specifically, N-type silicon chip 110 includes matte and burnishing surface, and the matte of N-type silicon chip 110 is all in gold word
The suede structure of turriform shape, matte is the front of N-type silicon chip 110, and burnishing surface is the back of the body of N-type silicon chip 110
Face.
Wherein, the matte side of N-type silicon chip 110 includes that n+ surface field layer 180, n+ surface field layer 180 are formed
On matte, the diffused sheet resistance of n+ surface field layer 180 is 80-300 Ω/sq.
The burnishing surface side of N-type silicon chip 110 includes p+ emitter region, n++ surface field region 160 and isolation
Region 190, p+ emitter region is formed on burnishing surface, area of isolation 190 respectively with p+ emitter region
Adjacent with n++ surface field region 160, and area of isolation 190 extends in N-type silicon chip 110, n++ table
The top surface of face field areas 160 flushes with the burnishing surface of N-type silicon chip 110, and n++ surface field region 160
Extend in described N-type silicon chip.
The degree of depth of area of isolation 190 is greater than the degree of depth in n++ surface field region 160.N++ surface field region 160
The degree of depth be hundreds of nanometer, the degree of depth of area of isolation 190 is 1 micron to 40 microns, area of isolation 190
Width is 1 micron to 100 microns.Width on the cross section of area of isolation 190 can be unequal, from N
The second surface of type silicon chip 110 on the direction of the inside of N-type silicon chip 110, the cross section of area of isolation 190
Width can be more and more less.The diffused sheet resistance in n++ surface field region is 20-80 Ω/sq.
First passivated reflection reducing is penetrated film layer 210 and is positioned on n+ surface field layer 180, and the second passivated reflection reducing penetrates film layer 220
Cover p+ emitter region, n++ surface field region 160 and area of isolation 190.First passivated reflection reducing penetrates film
Layer 210 and the second passivated reflection reducing are penetrated film layer 220 and are silicon oxide layer, and the first passivated reflection reducing penetrates film layer 210 He
Second passivated reflection reducing is penetrated the thickness of film layer 220 and is 5 nanometer-15 nanometers.
Anelectrode 230 and negative electrode 240 are respectively positioned on the second passivated reflection reducing and penetrate on film layer 220, and anelectrode 230
Extending to p+ emitter region, and it extends to the top surface of p+ emitter region, negative electrode 240 is to n++
Surface field region 160, and it extends to the top surface in n++ surface field region 160.
Anelectrode 230 and negative electrode 240 are gate line electrode.Gate line electrode is some, and gate line electrode divides
It is not distributed in the second passivated reflection reducing and penetrates on film 220, in order to draw the electric current formed.Gate line electrode specifically includes
Main gate line electrode and secondary gate line electrode.Wherein, the radical of main gate line electrode is 2-5 root, and width is
0.5mm-2.5mm；The radical of secondary gate line electrode is 50-150 root, and width is 30um-150um.
It should be noted that in other embodiments, film layer 210 and the second passivation are penetrated at the first passivated reflection reducing
It is respectively formed with the first silicon nitride layer and the second silicon nitride layer on antireflection film layer 220, thus is passivated further,
Reduce reflection.This first silicon nitride layer and the second silicon nitride layer are silicon dioxide, silicon nitride, titanium dioxide
Or the monofilm that aluminium oxide is formed, or it is any in silicon dioxide, silicon nitride, titanium dioxide and aluminium oxide
Two or more multilayer film formed, the thickness of the first silicon nitride layer is 65 nanometer-80 nanometers, the
The thickness of nitride silicon layer is 80 nanometer-150 nanometers.Preferably, the first silicon nitride layer and the second silicon nitride layer
It is silicon nitride layer, thus is passivated further, reduce reflection.
Above-mentioned IBC solar cell and preparation method thereof, by the first surface system by N-type silicon chip 110
Floss processes, and the second surface of N-type silicon chip 110 is polished, then on the second surface of N-type silicon chip 110
Form boron dopant source layer 120, then this N-type silicon chip 110 put into and thermal oxidation furnace is carried out react and spread,
Due to the effect of oxygen, thus the silicon in boron dopant source layer 120 and N-type silicon chip 110 reacts, and is formed
Pyrex layer 130, the boron source in Pyrex layer 130 spreads to second surface simultaneously, thus at the second table
The p+ emitter layer 140 and Pyrex layer 130 stacked gradually is formed on face, again due to the effect of oxygen,
Form silicon oxide layer 150 on the first surface, and the specific region of second surface is carried out laser treatment, thus
Remove the Pyrex corresponding to this specific region and p+ emitter stage, so that only part on second surface
Region overlay has p+ emitter stage and Pyrex, thus when N-type silicon chip 110 is put in phosphorus source diffusion furnace,
Owing to second surface upper part region is covered by Pyrex so that do not covered by Pyrex on second surface
Region formed n++ surface field region 160, meanwhile, sequentially form n+ surface field layer 180 on the first surface
With phosphorosilicate glass layer 170, then second surface is carried out laser treatment, separate the p+ emitter stage on second surface
With n++ surface field region 160, thus form figure on a second surface, by Pyrex and phosphorosilicate glass layer
Remove, then make passivated reflection reducing and penetrate film layer and electrode, mixed by formation boron on the second surface that polish
Miscellaneous active layer 120, then carry out oxide-diffused, thus do not form boron dopant source layer 120 on the first surface, at it
After carry out phosphorus source diffusion in, it is not necessary to first surface is processed, can directly be diffused, thus reduce
Technological process in IBC manufacturing process, and use the mode of laser, second surface is patterned process,
Technique is more simply and more accurate.
Each technical characteristic of embodiment described above can combine arbitrarily, for making description succinct, the most right
The all possible combination of each technical characteristic in above-described embodiment is all described, but, if these skills
There is not contradiction in the combination of art feature, is all considered to be the scope that this specification is recorded.
Embodiment described above only have expressed several embodiments of the present utility model, its describe more concrete and
In detail, but therefore can not be interpreted as the restriction to utility model patent scope.It should be pointed out that, it is right
For those of ordinary skill in the art, without departing from the concept of the premise utility, it is also possible to do
Going out some deformation and improvement, these broadly fall into protection domain of the present utility model.Therefore, this utility model is special
The protection domain of profit should be as the criterion with claims.
Claims (10)
1. an IBC solar cell, it is characterised in that including:
N-type silicon chip, described N-type silicon chip has matte and burnishing surface, and the matte side of described N-type silicon chip includes
N+ surface field layer, described n+ surface field layer is formed on described matte,
The burnishing surface side of described N-type silicon chip includes p+ emitter region, n++ surface field region and isolation area
Territory, described p+ emitter region is formed on described burnishing surface, and described area of isolation is launched with described p+ respectively
Territory, polar region and described n++ surface field region are adjacent, and described area of isolation extends in described N-type silicon chip,
The described top surface in n++ surface field region flushes with the burnishing surface of described N-type silicon chip, and described n++ table
Face field areas extends in described N-type silicon chip；
First passivated reflection reducing penetrates film layer and the second passivated reflection reducing penetrates film layer, and described first passivated reflection reducing penetrates film layer position
On described n+ surface field layer, described second passivated reflection reducing is penetrated film layer and is covered described p+ emitter region, described
N++ surface field region and described area of isolation；And
Anelectrode and negative electrode, described anelectrode and described negative electrode are respectively positioned on described second passivated reflection reducing and penetrate film
On layer, and described anelectrode extends to described p+ emitter region, and it extends to described p+ emitter region
Top surface, described negative electrode is to described n++ surface field region, and it extends to place, described n++ surface
The top surface in territory.
IBC solar cell the most according to claim 1, it is characterised in that described n+ surface field layer
Diffused sheet resistance be 80-300 Ω/sq.
IBC solar cell the most according to claim 1, it is characterised in that described area of isolation deep
Degree is more than the degree of depth in described n++ surface field region.
IBC solar cell the most according to claim 3, it is characterised in that described area of isolation deep
Degree is 1 micron to 40 microns.
IBC solar cell the most according to claim 4, it is characterised in that the width of described area of isolation
Degree is 1 micron to 100 microns.
IBC solar cell the most according to claim 1, it is characterised in that place, described n++ surface
The diffused sheet resistance in territory is 20-80 Ω/sq.
IBC solar cell the most according to claim 1, it is characterised in that the floss of described N-type silicon chip
Face is pyramid shape.
IBC solar cell the most according to claim 1, it is characterised in that described first passivated reflection reducing
Penetrate film layer and thickness that described second passivated reflection reducing penetrates film layer is 5 nanometer-15 nanometers.
IBC solar cell the most according to claim 8, it is characterised in that described first passivated reflection reducing
Penetrate film layer and described second passivated reflection reducing is penetrated film layer and is membranous layer of silicon oxide.
IBC solar cell the most according to claim 1, it is characterised in that also include the first nitridation
Silicon layer and the second silicon nitride layer, described first silicon nitride layer is positioned at described first passivated reflection reducing and penetrates on film layer, institute
State the second silicon nitride layer to be positioned at described second passivated reflection reducing and penetrate on film layer.
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| CN201620143393.6U CN205542815U (en) | 2016-02-25 | 2016-02-25 | Ibc solar battery |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105609571A (en) * | 2016-02-25 | 2016-05-25 | 上海大族新能源科技有限公司 | IBC solar cell and manufacturing method thereof |
| CN109698252A (en) * | 2018-12-25 | 2019-04-30 | 浙江晶科能源有限公司 | A kind of IBC battery and preparation method thereof |
| CN117637874A (en) * | 2024-01-26 | 2024-03-01 | 隆基绿能科技股份有限公司 | Back contact battery and manufacturing method thereof |
-
2016
- 2016-02-25 CN CN201620143393.6U patent/CN205542815U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105609571A (en) * | 2016-02-25 | 2016-05-25 | 上海大族新能源科技有限公司 | IBC solar cell and manufacturing method thereof |
| CN109698252A (en) * | 2018-12-25 | 2019-04-30 | 浙江晶科能源有限公司 | A kind of IBC battery and preparation method thereof |
| CN117637874A (en) * | 2024-01-26 | 2024-03-01 | 隆基绿能科技股份有限公司 | Back contact battery and manufacturing method thereof |
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