CN205540705U

CN205540705U - A time schedule controller for laser induction punctures spectrum

Info

Publication number: CN205540705U
Application number: CN201620283528.9U
Authority: CN
Inventors: 李祥友; 李秋实; 郭连波; 曾晓雁; 陆永枫; 沈萌; 曾庆栋; 杨新艳
Original assignee: Huazhong University of Science and Technology
Current assignee: Huazhong University of Science and Technology
Priority date: 2016-04-07
Filing date: 2016-04-07
Publication date: 2016-08-31
Anticipated expiration: 2026-04-07

Abstract

The utility model discloses a time schedule controller for laser induction punctures spectrum, including USB interface circuit, power management circuit, reference clock circuit, master control and chronogenesis generating circuit, output driver circuit and synchronization signal output interface, USB interface circuit is used for for power management circuit provides DC power supply, and does the master control provides the interface of communicating with the host computer with chronogenesis generating circuit, the reference clock circuit is connected with chronogenesis generating circuit with the master control, provides required operation clock for it, the master control is used for producing multichannel synchronization pulse time series signal with chronogenesis generating circuit under the drive of system clock to export through the output driver circuit, synchronization signal output interface and output driver circuit link to each other, provide the standard interface for the signal transmission cable of laser instrument and spectrum appearance. The utility model has the characteristics of multichannel, high accuracy, frequency and pulse width are adjustable, LIBS experiment platform both can have been satisfied to time schedule control's requirement, in the small -size instruments such as the hand -held type LIBS analysis appearance that also can integrate.

Description

A kind of time schedule controller for LIBS

Technical field

This utility model relates to LIBS analysis technical field, be specifically related to a kind of for The time schedule controller of LIBS.

Background technology

(Laser-induced Breakdown Spectroscopy is called for short LIBS LIBS) being a kind of technology utilizing Atomic Emission Spectral Analysis material element, its ultimate principle is to utilize Superlaser ablation ionized sample surface, inspires plasma, by plasma cooling procedure The characteristic spectrum of middle radiation is analyzed, and the element of sample can be carried out qualitative and quantitative analysis.Should Technology have prepare without sample, the advantage such as multicomponent is quickly analyzed, online in situ detection, Ke Yiguang General it is applied to the fields such as metallurgical analysis, environmental monitoring, geological prospecting, on-line monitoring.

Due in the whole life cycle of plasma, the characteristic spectrum signal intensity in different time stage There is difference with signal to noise ratio, and the signal intensity of characteristic spectrum and signal to noise ratio directly affect quantitative analysis , therefore there is optimal Spectral acquisition times point in accuracy and detectable limit.In LIBS system, generally Use adjustable delay precision nanosecond or picosecond other multichannel delay time generator accurately control laser Device goes out the time interval (i.e. work schedule) of light and spectrometer collection spectrum, thus obtains optimal spectrum number According to.Therefore, time schedule controller has key effect in LIBS system.

Existing LIBS experiment porch typically uses universal delay time generator (as U.S. Stanford is public The DG535 of department) control work schedule.Although this kind of time schedule controller function admirable, but volume is big, Power consumption is high, expensive, and dependence on import, is not suitable for the system integration.And, along with LIBS system System gradually move towards instrumentation and miniaturization, existing time schedule controller cannot meet system to volume, power consumption, The strict demand of the aspects such as integration, needs to develop a kind of small size of LIBS system, low of being applicable to Power consumption, low cost, novel time schedule controller easy of integration.

Utility model content

The purpose of this utility model be for existing time schedule controller cannot meet LIBS system instrumentization and The problem of miniature requirement, proposes a kind of time schedule controller for LIBS, is one Plant the high-precision multi-path time schedule controller of miniaturization, both can meet LIBS experiment porch to sequencing contro Requirement, it is possible to be integrated in the miniature instruments such as hand-held LIBS analyser.

A kind of time schedule controller for LIBS that this utility model provides, its feature Being, it includes usb circuit, electric power management circuit, reference clock circuit, master control and sequential There is circuit, output driving circuit and synchronizing signal output interface；

Described usb circuit is connected with electric power management circuit, is used for providing DC source, additionally also It is connected with timing generator circuit with described master control, for providing the interface communicated with host computer；

Described electric power management circuit provides required running voltage for each parts in time schedule controller；

Described reference clock circuit is connected with timing generator circuit with described master control, provides required work for it Make clock；

Described master control is connected with described output driving circuit with timing generator circuit, at system clock Driving under produce Multi-path synchronous pulse sequence signal, and export through described output driving circuit；

Described synchronizing signal output interface is connected with described output driving circuit, is used for as laser instrument and light The signal transmission cable of spectrometer provides standard interface.

As the improvement of technique scheme, described master control and timing generator circuit are by single chip microcontroller MCU is constituted.Described microcontroller has been internally integrated clock multiplier PLL module, pulsewidth modulation HRPWM Module, serial communication SCI module, intervalometer and central processor CPU；Clock multiplier PLL module with Described reference clock circuit is connected, and after external reference clock frequency multiplication, provides system clock for MCU； Pulsewidth modulation HRPWM module is connected with output driving circuit, produces multichannel under the driving of system clock Lock-out pulse clock signal exports through output driving circuit；Serial communication SCI module connects with described USB Mouth circuit is connected, it is achieved with host computer communication；Intervalometer timing under the driving of system clock, passes through Timer interrupt periodically drives CPU reload HRPWM module parameter and again enable this module, Produce periodic synchronization pulse clock signal, it is achieved the control to pulse frequency；Central processor CPU For system control, each module operational factor is set according to host computer instruction, and monitors the operation of each module State.

As the further improvement of technique scheme, described pulsewidth modulation HRPWM module is provided with multiple Separate unit that can be synchronous enabled, each unit include digit counter, comparator, two compare and post Storage and programmable delay line, digit counter, two comparand registers and programmable delay line are equal Being connected with comparator, described programmable delay line is connected with described output driving circuit.

As the further improvement of technique scheme, described usb circuit includes that USB turns string Mouthful and USB power two parts；USB power pack is connected with electric power management circuit, and USB turns serial ports part It is connected with the serial communication SCI module within microcontroller.

Microcontroller chip and a small amount of peripheral circuit that this utility model employing monolithic is highly integrated achieve Multichannel, in high precision, the lock-out pulse time schedule controller of frequency and adjustable pulse width, meeting LIBS system Unite on the basis of sequencing contro is required, significantly reduce the volume of time schedule controller, power consumption, one-tenth This, can be integrated in the miniature instruments such as hand-held LIBS analyser.

Accompanying drawing explanation

Fig. 1 is the structural representation of this utility model example；

Fig. 2 is pulsewidth modulation HRPWM unit knot in the microcontroller that this utility model example provides Structure schematic diagram；

Fig. 3 is each passage time diagram；

In Fig. 3, Ax, Bx represent the value of comparand register A and B of xth unit respectively.

Detailed description of the invention

Below in conjunction with the accompanying drawings detailed description of the invention of the present utility model is described further.Need at this Illustrate, the explanation of these embodiments is adapted to assist in and understands this utility model, but not structure Paired restriction of the present utility model.Additionally, in each embodiment of this utility model disclosed below Just can be mutually combined as long as involved technical characteristic does not constitutes conflict each other.

As it is shown in figure 1, this utility model example provide a kind of for LIBS time Sequence controller, including usb circuit, electric power management circuit, reference clock circuit, master control and time Sequence generation circuit, output driving circuit and synchronizing signal output interface.

Described usb circuit includes that USB turns serial ports and USB powers two parts；USB power pack with Electric power management circuit connects, it is provided that 5V/500mA DC source；Electric power management circuit is each circuit module Required running voltage is provided；USB turns serial ports part and the serial communication SCI mould within microcontroller Block connects, it is provided that the interface communicated with host computer.

Described reference clock circuit is made up of, and in microcontroller the 20MHz active crystal oscillator of high accuracy Portion's clock multiplier PLL module is connected, and provides required work clock for each module in MCU inside.

Described master control and timing generator circuit are by single chip microcontroller MCU (such as TI TMS320C28346) Constitute.Microcontroller be internally integrated clock multiplier PLL module, pulsewidth modulation HRPWM module, Serial communication SCI module, intervalometer and central processor CPU.Clock multiplier PLL module and outside base Quasi-clock circuit is connected, and after 10 times of frequencys multiplication of 20MHz external reference clock, provides 200MHz for MCU System clock；Pulsewidth modulation HRPWM module is connected with output driving circuit, at 200MHz system clock Driving under produce 8 road lock-out pulse clock signals through output driving circuit export；Serial communication SCI Module turns serial ports part with the USB of usb circuit and is connected, it is achieved with host computer communication；Intervalometer Timing under the driving of 200MHz system clock, periodically drives CPU again to add by timer interrupt Carry HRPWM module parameter and again enable this module, producing periodic synchronization pulse clock signal, real The now control to pulse frequency.Described central processor CPU controls for system, refers to according to host computer Order arranges each module operational factor, and monitors each module running status.

Further, described pulsewidth modulation HRPWM module, have 8 can be synchronous enabled independence Unit, each unit includes: 16 bit digital enumerators, comparator, 16 bit comparison depositor A and B, Adjustable delay resolution is the programmable delay line of 55ps, as shown in Figure 2.Comparator respectively with numeral Enumerator, comparand register A with B, programmable delay line are connected, programmable delay line and outside output Drive circuit is connected.Described pulsewidth modulation HRPWM module has high-resolution.

The principle that HRPWM module produces lock-out pulse clock signal is as follows:

When, after CPU synchronous enabled HRPWM module each unit, the digit counter of each unit is at 200MHz Synchronous counting under the driving of system clock, each clock cycle (5ns) enumerator adds 1, simultaneously with This unit comparand register A and B carries out ratio, on duty equal time, comparator output level is the most immediately Upset, produces pulse signal.As it is shown on figure 3, the relative time delay etc. between each unit pulse signal forward position Difference in each unit comparand register A is multiplied by clock cycle 5ns, and each unit pulse signal width is equal to Each the difference of comparand register B Yu A is multiplied by clock cycle 5ns.Compare deposit by arranging each unit The value of device A, can produce the 8 road synchronization pulses that adjustable relative time delay resolution is 5ns；Logical Cross the value that each unit comparand register B is set, i.e. adjustable each pulse signal width.

The pulse signal of the 5ns delay resolution that each unit comparator produces is input to respective able to programme Delay line carries out the fine time delay of secondary.As in figure 2 it is shown, each unit programmable delay line is by 255 sections Propagation delay time is that the gated programmable delay line of 55ps is composed in series, the series connection programmable delay of gating The quantity of line is determined by the value of strobe register.Deposit by arranging each unit programmable delay line gating The value of device, can carry out secondary fine thin tuning to the relative time delay between each unit pulse front edge, it is thus achieved that can The 8 road synchronization pulses adjusting delay resolution to be 55ps.This pulse signal is adjusted through output driving circuit Export after entire signal voltage and driving force.

The long process such as described output driving circuit is made up of monolithic 8 road driving chip, each road transmission line work, Between Shi Ge road, propagation delay time is consistent.Laser instrument and spectrogrph is exported by synchronizing signal output interface.

Described synchronizing signal output interface is made up of the SMA female seat of 8 impedances 50 ohm, for laser instrument Standard interface is provided with the signal transmission cable of spectrogrph.

Work process of the present utility model is:

(1) microcontroller electrification reset, enters serial ports SCI Boot pattern, by serial ports SCI Module and usb circuit download firmware program from host computer；Run firmware program, initialize clock Frequency multiplication PLL module produces 200MHz system clock, initializes HRPWM module, initialization timing device；

(2) host computer issues passage gating command, relative time delay parameter, width parameter, frequency parameter, CPU receives interrupt function by serial ports SCI FIFO and receives instruction, according to the channel instruction ginseng received Number arranges HRPWM each unit comparand register A and B, programmable delay line strobe register, and it is fixed to arrange Time device period register；

(3) host computer issues sign on, after CPU receives sign on, enables intervalometer and starts meter Count, and synchronous enabled HRPWM each unit counter synchronisation starts counting up；When each unit Counter Value with When each the value of comparand register A, B is equal, producing pulse signal, this pulse signal is through gating Export after programmable delay line time delay；After the unit of all gatings all produces pulse signal, stop The all location counters of HRPWM, waiting timer interrupts；When timer interruption produces, CPU is again HRPWM each unit depositor is set, and starts counting up from the new each unit enumerator that enables, produce next Wheel pulse signal.

(4) when host computer issues halt instruction, CPU stops intervalometer and HRPWM all unit meter Number device also resets each unit depositor, and waiting for the start instructs；Under halted state, under host computer Sending out channel parameters instruction, CPU updates the value of each depositor, and waiting for the start instructs.

The beneficial effects of the utility model are:

Microcontroller chip and a small amount of peripheral circuit that this utility model employing monolithic is highly integrated achieve Relative time delay precision that 8 passages, 55ps are adjustable, frequency and the lock-out pulse time schedule controller of adjustable pulse width, Meet LIBS system to sequencing contro require on the basis of, significantly reduce the body of time schedule controller Long-pending, power consumption, cost, can be integrated in the miniature instruments such as hand-held LIBS analyser.

Below it is only the explanation done for specific embodiment of the utility model and know-why thereof, and The restriction not technology contents of the present utility model carried out, any technology being familiar with the art Personnel in technical scope disclosed in the utility model, the change being readily apparent that or replacement, all answer Contain in protection domain of the present utility model.

Claims

1. the time schedule controller for LIBS, it is characterised in that it includes USB Interface circuit, electric power management circuit, reference clock circuit, master control are driven with timing generator circuit, output Galvanic electricity road and synchronizing signal output interface；

Time schedule controller for LIBS the most according to claim 1, it is special Levying and be, described master control is made up of single chip microcontroller MCU with timing generator circuit.

Time schedule controller for LIBS the most according to claim 2, it is special Levying and be, described microcontroller has been internally integrated clock multiplier PLL module, pulsewidth modulation HRPWM Module, serial communication SCI module, intervalometer and central processor CPU；

Clock multiplier PLL module is connected with described reference clock circuit, after external reference clock frequency multiplication, System clock is provided for MCU；Pulsewidth modulation HRPWM module is connected with output driving circuit, in system Produce Multi-path synchronous pulse sequence signal under the driving of clock to export through output driving circuit；Serial communication SCI module is connected with described usb circuit, it is achieved with host computer communication；Intervalometer is at system clock Driving under timing, periodically driven CPU to reload HRPWM module parameter by timer interrupt And again enable this module, produce periodic synchronization pulse clock signal, it is achieved the control to pulse frequency System；Central processor CPU controls for system, arranges each module operational factor according to host computer instruction, And monitor each module running status.

Time schedule controller for LIBS the most according to claim 3, it is special Levying and be, described pulsewidth modulation HRPWM module is provided with multiple separate unit that can be synchronous enabled, each Unit includes digit counter, comparator, two comparand registers and programmable delay line, digital meter Number devices, two comparand registers and programmable delay line are all connected with comparator, described able to programme prolong Time line be connected with described output driving circuit.

5. according to the described sequential control for LIBS arbitrary in Claims 1-4 Device processed, it is characterised in that described usb circuit includes that USB turns serial ports and USB powers two parts； USB power pack is connected with electric power management circuit, and USB turns within serial ports part and microcontroller Serial communication SCI module connects.