CN205452330U

CN205452330U - Si substrate led epitaxial wafer

Info

Publication number: CN205452330U
Application number: CN201521094173.0U
Authority: CN
Inventors: 刘波; 戭玉龙; 王波; 袁凤坡; 潘鹏; 汪灵; 白欣娇; 周晓龙; 王静辉
Original assignee: CETC 13 Research Institute
Current assignee: CETC 13 Research Institute
Priority date: 2015-12-26
Filing date: 2015-12-26
Publication date: 2016-08-10
Anticipated expiration: 2025-12-26

Abstract

The utility model discloses a si substrate LED epitaxial wafer relates to the device technical field who has special crystal structure. The epitaxial wafer includes si substrate and the epitaxial layer that is located si substrate upper surface, epitaxial layer from the bottom up is alNAlGaN buffer layer, involuntary doping U type gaN layer, si doping N type gaN layer, the multiple quantum well radiation layer of inGaNGaN, electron barrier layer and mg doping P type gaN layer in proper order. The epitaxial wafer has improved internal quantum efficiency, reduce the piezoelectricity polarized electric field simultaneously, increase the wave function overlap in electron and hole for the radiative recombination probability increases, has further improved internal quantum efficiency.

Description

Si substrate LED

Technical field

This utility model relates to the device arts with special crystal structure, particularly relates to a kind of Si substrate LED.

Background technology

LED is a kind of solid-state semiconductor device that electric energy is converted into luminous energy, relative to conventional light source, LED has the advantages that volume is little, length in service life, fast response time, luminous efficiency are high, and therefore LED becomes a kind of novel green light source got most of the attention entrance lighting field.Wherein on Si substrate, LED is particularly subject to the extensive concern of people owing to cost is relatively low.But Si substrate and GaN lattice mismatch and thermal mismatching are relatively big, the stress between causing InGaN/GaN multiple quantum well area trap to be built is relatively big, and piezoelectric polarization effect increases, and causes internal quantum efficiency relatively low, constrains on Si substrate LED in the development of general illumination field.

Utility model content

Technical problem to be solved in the utility model is to provide a kind of Si substrate LED, and described epitaxial wafer improves internal quantum efficiency；Reducing piezoelectric polarization electric field, the wave function increasing electronics and hole overlaps so that radiation recombination probability increases, and further increases internal quantum efficiency simultaneously.

For solving above-mentioned technical problem, technical solution adopted in the utility model is: a kind of Si substrate LED, it is characterized in that: including Si substrate and be positioned at the epitaxial layer of Si substrate top surface, described epitaxial layer is followed successively by AlN/AlGaN cushion, the U-shaped GaN layer of involuntary doping, Si doped N-type GaN layer, InGaN/GaN multiple quantum trap luminescent layer, electronic barrier layer and Mg doped p-type GaN layer from top to bottom.

Further technical scheme is: described InGaN/GaN multiple quantum trap luminescent layer includes 9～15 pairs of InGaN well layer and GaN barrier layer structure.

Further technical scheme is: the thickness of described InGaN well layer is 2 nanometer-4 nanometers；The InN layer being respectively provided on two sides with 3 angstroms～5 angstroms up and down of every layer of InGaN well layer；The thickness of GaN barrier layer is 9～12 nanometers.

Use and have the beneficial effects that produced by technique scheme: described epitaxial wafer grows InN layer before and after growth InGaN SQW respectively, the stress between being built by release trap, increase carrier localization and improve internal quantum efficiency；The method simultaneously using gliding temperature when growing InGaN/GaN multiple quantum trap changes In component in SQW, reduces piezoelectric polarization electric field, and the wave function increasing electronics and hole overlaps so that radiation recombination probability increases, thus improves internal quantum efficiency.By checking, described epitaxial wafer improves nearly 5%～10% than the epitaxial wafer optical output power of traditional InGaN/GaN quantum well structure.

Accompanying drawing explanation

Fig. 1 is the structural representation of epitaxial wafer described in the utility model；

Wherein: 1, Si substrate 2, AlN/AlGaN cushion 3, U-shaped GaN layer 4, Si doped N-type GaN layer 5, InGaN/GaN multiple quantum trap luminescent layer 5-1, InN layer 5-2, GaN barrier layer 5-3, InGaN well layer 6, electronic barrier layer 7, Mg doped p-type GaN layer.

Detailed description of the invention

Below in conjunction with the accompanying drawing in this utility model embodiment, the technical scheme in this utility model embodiment is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present utility model rather than whole embodiments.Based on the embodiment in this utility model, the every other embodiment that those of ordinary skill in the art are obtained under not making creative work premise, broadly fall into the scope of this utility model protection.

Elaborate a lot of detail in the following description so that fully understanding this utility model, but this utility model can also use other to be different from alternate manner described here to be implemented, those skilled in the art can do similar popularization in the case of this utility model intension, and therefore this utility model is not limited by following public specific embodiment.

As it is shown in figure 1, the utility model discloses a kind of Si substrate LED, including Si substrate 1 and the epitaxial layer being positioned at Si substrate 1 upper surface.Described epitaxial layer is followed successively by AlN/AlGaN cushion 2, the U-shaped GaN layer of involuntary doping 3, Si doped N-type GaN layer 4, InGaN/GaN multiple quantum trap luminescent layer 5, electronic barrier layer 6 and Mg doped p-type GaN layer 7 from top to bottom.Described InGaN/GaN multiple quantum trap luminescent layer 5 includes 9～15 pairs of InGaN well layer 5-3 and GaN barrier layer 5-2 structure.The thickness of described InGaN well layer 5-3 is 2 nanometer-4 nanometers；The InN layer 5-1 being respectively provided on two sides with 3 angstroms～5 angstroms up and down of every layer of InGaN well layer 5-3, the thickness of GaN barrier layer is 9～12 nanometers.

The preparation method of above-mentioned Si substrate LED, comprises the steps:

Upper surface grown epitaxial layer at Si substrate 1, epitaxial layer growth process is as follows: Si substrate 1 prebake conditions, then in the upper surface growing AIN the most successively/AlGaN cushion 2 of Si substrate 1, the U-shaped GaN layer of involuntary doping 3, Si doped N-type GaN layer 4, InGaN/GaN multiple quantum trap luminescent layer 5, electronic barrier layer 6 and Mg doped p-type GaN layer 7.

At growth InGaN/GaN multiple quantum trap luminescent layer 5(MQW) time, the first InN layer 5-1 of growth 3 angstroms～5 angstroms, then InGaN SQW is grown with the method for temperature gradients, range of temperature is for for 20 DEG C, i.e. when growing InGaN well layer 5-3, temperature is from the standard growth temperature-10 DEG C of T1(T1=SQW) the standard growth temperature+10 DEG C of T2(T2=SQW is changed stepwise).After the growth of InGaN well layer 5-3 terminates, regrowth 3～the InN layer 5-1 of 5 angstroms, then regrowth GaN barrier layer 5-2, as a cycle, InGaN well layer 5-3 of 9-15 periodicity of growth and GaN barrier layer 5-2 structure.

InGaN/GaN multiple quantum trap luminescent layer 5(MQW) it is the core of this epitaxial wafer.There is lattice mismatch between building in grown quantum trap InGaN material and growth GaN, SQW also exists compressive stress between building, and the size of stress is closely related with trap barrier layer thickness, and the direction of stress is pointed to by trap and built, and namely points to the surface direction of GaN material；GaN material Ga atom and atom N charge-site are misaligned, cause GaN material to there is polarity effect, and trap barrier layer all exists polarization stress；The imbalance of compressive stress and polarization stress can cause InGaN and GaN material energy band bend and tilt, and the wave function decreasing electronics and hole overlaps so that radiation recombination probability reduces, thus reduces internal quantum efficiency (IQE).

By growing InN before and after InGaN well layer, can effectively reduce the lattice mismatch between SQW InGaN material and GaN base, the stress between release trap base, improve internal quantum efficiency.Use when InGaN layer grows the method for gliding temperature to modulate In component simultaneously, offset the impact of partial polarization electric field with this, thus improve electronics and hole-recombination probability, improve luminous efficiency.By checking, described epitaxial wafer improves nearly 5%～10% than the epitaxial wafer optical output power of traditional InGaN/GaN quantum well structure.

Claims

1. a Si substrate LED, it is characterized in that: include Si substrate (1) and be positioned at the epitaxial layer of Si substrate (1) upper surface, described epitaxial layer is followed successively by AlN/AlGaN cushion (2), the U-shaped GaN layer of involuntary doping (3), Si doped N-type GaN layer (4), InGaN/GaN multiple quantum trap luminescent layer (5), electronic barrier layer (6) and Mg doped p-type GaN layer (7) from top to bottom；Described InGaN/GaN multiple quantum trap luminescent layer (5) includes 9～15 pairs of InGaN well layer (5-3) and GaN barrier layer (5-2) structure；The thickness of described InGaN well layer (5-3) is 2 nanometer-4 nanometers；The InN layer (5-1) being respectively provided on two sides with 3 angstroms～5 angstroms up and down of every layer of InGaN well layer (5-3)；The thickness of GaN barrier layer (5-2) is 9～12 nanometers.