CN205385023U - Embedded high -pressure LDMOS -SCR device with strong voltage clamp system and ESD robustness - Google Patents
Embedded high -pressure LDMOS -SCR device with strong voltage clamp system and ESD robustness Download PDFInfo
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- CN205385023U CN205385023U CN201620186167.6U CN201620186167U CN205385023U CN 205385023 U CN205385023 U CN 205385023U CN 201620186167 U CN201620186167 U CN 201620186167U CN 205385023 U CN205385023 U CN 205385023U
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Abstract
The utility model provides the utility model relates to an embedded high -pressure LDMOS of strong voltage clamp system and ESD robustness the SCR device, the ESD protection is gone up to the piece that can be used to high -pressure IC. Mainly by the P substrate, the P trap, the N trap, first oxygen isolation region, a P+ injection domain, second field oxygen isolation region, a N+ injection domain, first fin formula polysilicon gate, the 2nd N+ injection domain, second fin formula polysilicon gate, the 3rd N+ injection domain, third fin formula polysilicon gate, the polysilicon gate, fourth fin formula polysilicon gate, the 2nd P+ injection domain, the 5th fin formula polysilicon gate, the 3rd P+ injection domain, the 6th fin formula polysilicon gate, fourth P+ injection domain, third field oxygen isolation region, fourth N+ injection domain and fourth field oxygen isolation region constitute. This device under the ESD impulse action, can the formation source the embedded NMOS interdigitated of end and the embedded PMOS interdigitated's of drain terminal resistance -capacitance coupling current path and LDMOS the ESD electric current of the SCR structure route of releasing to the ESD robustness of reinforcing device improves voltage clamp system ability.
Description
Technical field
The invention belongs to the electrostatic discharge (ESD) protection field of integrated circuit, relate to a kind of high-voltage ESD protective device, be specifically related to one and there is forceful electric power pressing tongs
System and the embedded high-voltage LDMOS-SCR device of ESD robustness, can be used for improving the reliability of ESD protection on high voltage integrated circuit sheet.
Background technology
Along with updating of semiconductor integration technology, Circuits System is constantly to high density, integrated direction development.For meeting Circuits System height collection
The growth requirement of one-tenthization, power semiconductor integrated technology is applied increasingly extensive in Circuits System.Although static discharge (ESD) electricity integrated to CMOS
The infringement on road has caused circuit engineering teacher and the extensive concern of scientific research personnel and attention, and traditional low pressure ESD protection method and measure are achieved with necessarily
Effect.But, because the introducing of power semiconductor integrated technology causes the operating voltage of Circuits System constantly to raise, traditional low pressure ESD protection side
Method and measure can not be simply transplanted in current power semiconductor IC system, high voltage integrated circuit on power semiconductor integrated circuit or sheet
The ESD protection of (high pressure IC) has become a major issue and the study hotspot in electrostatic defending field.Because of high pressure IC be usually operated at big voltage,
Under big electric current, strong electromagnetic, frequent hot plug, the super working environment being more or less than the high intensity such as room temperature, ESD protection face on the sheet of high pressure IC
Face more stern challenge.Therefore designer needs that the ESD design protection of Power IC is done extra technology and considers.
LDMOS (LDMOS) device has high pressure resistant and low on-resistance characteristic because of it, in the output of high pressure IC
End is often used as driving pipe and the ESD self-protection device of load.But, along with the continuous reduction of IC preparation technology characteristic size, the core of high pressure IC
Sheet area constantly reduces, and voltage clamp ability and the ESD robustness of LDMOS unit are are the most weakened, it is difficult to reach International Electrotechnical Commission
The electronic product of regulation requires that manikin is not less than the electrostatic defending standard (IEC6000-4-2) of 2000V.Constantly groping through scientific research personnel,
It is found that and embed controllable silicon (SCR) in LDMOS device inside configuration, it is thus achieved that LDMOS-SCR structure the ESD of device can be greatly improved
Robustness.But, embedded in the maintenance voltage after the LDMOS device of SCR is opened under esd pulse effect and significantly reduce, easily produce door bolt
Lock effect.If maintenance voltage or the electric current of LDMOS-SCR device can be improved, then can be prevented effectively from device and produce breech lock.Present example is by knot
Closing the bulky capacitor advantage of LDMOS-SCR strong robustness and interdigital MOS structure, devise one and have easily triggering, high maintenance voltage is special with electric current
The strong voltage of property clamps down on the embedded high-voltage LDMOS-SCR device with ESD robustness.Under esd pulse effect, this ESD high voltage protector
Part can form the ESD current drain path with LDMOS-SCR structure, strengthens current drain ability and the ESD robustness of device, it addition,
There is the resistance-capacitance coupling current drain path of embedded PMOS and NMOS interdigital structure, device can be promoted to carry out interim quickly triggering at esd pulse and open
Open, there is easy trigger characteristic.And, the many interdigital structures of PMOS and NMOS, on the one hand, can increase the parasitic capacitance of device, improve device
Opening speed and trigger current；On the other hand, after device is opened, maintain electric current to increase, it is possible to decrease the electronics in device SCR path and hole
Emissivity, thus improve maintenance voltage and the voltage clamp ability of device.
Summary of the invention
Maintenance voltage breech lock low, anti-and the problem of voltage clamp scarce capacity is generally there is for ESD protection device on the sheet in existing high pressure IC,
Present example devises a kind of to be had strong voltage and clamps down on the embedded high-voltage LDMOS-SCR device with ESD robustness, both takes full advantage of
The feature of the high pressure resistant and strong ESD robustness of LDMOS-SCR device, make use of again the bulky capacitor of embedded PMOS with NMOS interdigital structure to post
Come into force the feature answered, and to form the ESD current conducting path both with LDMOS-SCR structure, has again embedded PMOS Yu NMOS fork
Refer to the parasitic resistance-capacitance coupling current conducting path of structure, improve the maintenance voltage and current of device, strengthen latch-up immunity and the ESD robustness of device,
It is applicable to ESD protection on the sheet of high pressure IC.
The present invention is achieved through the following technical solutions:
A kind of have strong voltage and clamp down on the embedded high-voltage LDMOS-SCR device with ESD robustness, and it includes the interdigital knot of source built-in NMOS
The resistance-capacitance coupling current path of structure and drain terminal embedded PMOS interdigital structure and the ESD current drain path with LDMOS-SCR structure, to increase
The ESD robustness of strong device, improves voltage clamp ability, it is characterised in that: mainly by substrate P, p-well, N trap, first oxygen isolated area,
Oneth P+ injection region, second oxygen isolated area, a N+ injection region, the first fin polysilicon gate, the 2nd N+ injection region, the second fin polycrystalline
Si-gate, the 3rd N+ injection region, the 3rd fin polysilicon gate, polysilicon gate, the 4th fin polysilicon gate, the 2nd P+ injection region, the 5th fin are many
Crystal silicon grid, the 3rd P+ injection region, the 6th fin polysilicon gate, the 4th P+ injection region, the 3rd oxygen isolated area, the 4th N+ injection region and the 4th
Oxygen isolated area is constituted；
Described p-well and described N trap, the left side edge of described substrate P and described P it is sequentially provided with from left to right in the region, surface of described substrate P
The left side edge of trap is connected, and the right side of described p-well is connected with the left side of described N trap, the right side of described N trap and the right side edge of described substrate P
It is connected；
Described first oxygen isolated area, a described P+ injection region, described second oxygen it is sequentially provided with from left to right in the region, surface of described p-well
Isolated area and described built-in NMOS interdigital structure, described built-in NMOS interdigital structure is by a described N+ injection region, described first fin polycrystalline
Si-gate, described 2nd N+ injection region, described second fin polysilicon gate, described 3rd N+ injection region and described 3rd fin polysilicon gate are constituted,
And alternately can be extended by N+ injection region and fin polysilicon gate successively along device widths direction according to the actual requirements in the range of device widths, institute
The left side edge in the left side and described p-well of stating first oxygen isolated area is connected, the right side of described first oxygen isolated area and a described P+ injection region
Left side be connected, on the right side of a described P+ injection region, the left side with described second oxygen isolated area is connected, the right side of described second oxygen isolated area and institute
The left side stating built-in NMOS interdigital structure is connected；
Be sequentially provided with from left to right in the region, surface of described N trap described embedded PMOS interdigital structure, described 3rd oxygen isolated area, described
Four N+ injection regions and described 4th oxygen isolated area, described embedded PMOS interdigital structure is by described 4th fin polysilicon gate, described 2nd P+ note
Enter the 3rd P+ injection region described in district, described 5th fin polysilicon gate, described 6th fin polysilicon gate, described 4th P+ injection region composition, and
Alternately can be extended by N+ injection region and fin polysilicon gate successively along device widths direction according to the actual requirements in the range of device widths, described
The right side of embedded PMOS interdigital structure is connected with the left side of described 3rd oxygen isolated area, the right side and the described 4th of described 3rd oxygen isolated area
The left side of N+ injection region is connected, and the right side of described 4th N+ injection region is connected with the left side of described 4th oxygen isolated area, described 4th oxygen isolation
The right side in district is connected with the right side edge of described N trap；
Described polysilicon gate across in described p-well and the surface portion region of described N trap, the left side of described polysilicon gate and described built-in NMOS
The right side of interdigital structure is connected, and the right side of described polysilicon gate is connected with the left side of described embedded PMOS interdigital structure；
A described P+ injection region is connected with the first metal 1, and a described N+ injection region is connected with the second metal 1, described first fin polysilicon
Grid and the 3rd metal 1 are connected, and described 2nd N+ injection region is connected with the 4th metal 1, and described second fin polysilicon gate is connected with fifth metal 1,
Described 3rd N+ injection region is connected with the 6th metal 1, and described 3rd fin polysilicon gate and the 7th metal 1 are connected, described polysilicon gate and the 8th
Metal 1 is connected, and described 4th fin polysilicon gate and the 9th metal 1 are connected, and described 2nd P+ injection region is connected with the tenth metal 1, and the described 5th
Fin polysilicon gate and the 11st metal 1 are connected, and described 3rd P+ injection region is connected with the 12nd metal 1, described 6th fin polysilicon gate and the
13 metals 1 are connected, and described 4th P+ injection region is connected with the 14th metal 1, and described 4th N+ injection region is connected with the 15th metal 1；
Described first metal 1, described second metal 1, described 3rd metal 1, described fifth metal 1, described 6th metal 1, described 7th gold medal
Belong to 1 to be all connected with the first metal 2, from described first metal 2 extraction electrode, as the metallic cathode of device；
Described 8th metal 1, described 9th metal 1, described tenth metal 1, described 11st metal 1, described 13rd metal 1, described
14 metals 1 are all connected with the second metal 2 with described 15th metal 1, from described second metal 2 extraction electrode, as the metal anode of device；
Described 4th metal 1 is connected with the 3rd metal 2, and described 12nd metal 1 is connected with described 3rd metal 2；
The Advantageous Effects of the present invention is:
(1) at the drain-end region of present example device, by described 4th fin polysilicon gate, described 2nd P+ injection region, described 5th fin
The described embedded PMOS that polysilicon gate, described 3rd P+ injection region, described 6th fin polysilicon gate, described 4th P+ injection region are constituted is interdigital
Structure, can improve the maintenance voltage of device, strengthens the voltage clamp ability of device.
(2) in the source-end region of present example device, by a described N+ injection region, described first fin polysilicon gate, described 2nd N+
The described built-in NMOS fork that injection region, described second fin polysilicon gate, described 3rd N+ injection region and described 3rd fin polysilicon gate are constituted
Refer to structure, it is possible to decrease the trigger voltage of device, increase ESD robustness and the voltage clamp ability of device.
(3) the described embedded PMOS interdigital structure in present example device and described built-in NMOS interdigital structure can increase the parasitic electricity of device
Hold, under transient state esd pulse effect, because resistance-capacitance coupling effect can increase the trigger current in the dead resistance of described p-well and described N trap, fall
The trigger voltage of low device, strengthens the voltage clamp ability of device, improves the surface current conducting homogeneity of device.
Accompanying drawing explanation
Fig. 1 is the schematic three dimensional views of present example device architecture；
Fig. 2 is present example device metal connection diagram；
Fig. 3 is present example device schematic diagram of ESD current drain path CP1 and CP2 under esd pulse effect；
Fig. 4 is the inside equivalent circuit diagram under present example device cross-section structure at current path CP1 and esd pulse effect thereof；
Detailed description of the invention
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:
Present example devises a kind of to be had strong voltage and clamps down on the embedded high-voltage LDMOS-SCR device with ESD robustness, by combining
LDMOS-SCR structure strong ESD robustness and the advantage of the big parasitic capacitance of PMOS Yu NMOS interdigital structure, strengthen device at high pressure ESD arteries and veins
Voltage clamping under punching effect and latch-up immunity.
The schematic three dimensional views of present example device architecture as shown in Figure 1, is specially and has strong voltage clamp down on and the embedding of ESD robustness for a kind of
Formula high-voltage LDMOS-SCR device, it includes that the resistance-capacitance coupling of source built-in NMOS interdigital structure and drain terminal embedded PMOS interdigital structure triggers
Current path and the ESD big current drain path with LDMOS-SCR structure, to strengthen the ESD robustness of device, improve voltage clamp energy
Power and the opening speed of device, it is characterised in that: main by substrate P 101, p-well 102,103, first oxygen isolated area 104, first of N trap
The 107, first fin polysilicon gate the 108, the 2nd N+ injection region 109,105, second oxygen isolated area the 106, the oneth N+ injection region, P+ injection region,
Second fin polysilicon gate the 110, the 3rd N+ injection region the 111, the 3rd fin polysilicon gate 112, polysilicon gate the 113, the 4th fin polysilicon gate
114, the 2nd P+ injection region the 115, the 5th fin polysilicon gate the 116, the 3rd P+ injection region the 117, the 6th fin polysilicon gate the 118, the 4th P+
Injection region 119, the 3rd oxygen isolated area the 120, the 4th N+ injection region 121 and the 4th oxygen isolated area 122 are constituted；
Described p-well 102 and described N trap 103, a left side for described substrate P 101 it is sequentially provided with from left to right in the region, surface of described substrate P 101
Lateral edges is connected with the left side edge of described p-well 102, and the right side of described p-well 102 is connected with the left side of described N trap 103, described N trap 103
Right side be connected with the right side edge of described substrate P 101；
Described first oxygen isolated area 104, a described P+ injection region 105, institute it is sequentially provided with from left to right in the region, surface of described p-well 102
State second oxygen isolated area 106 and described built-in NMOS interdigital structure, described built-in NMOS interdigital structure by a described N+ injection region 107,
Described first fin polysilicon gate 108, described 2nd N+ injection region 109, described second fin polysilicon gate 110, described 3rd N+ injection region
111 and described 3rd fin polysilicon gate 112 constitute, and can in the range of device widths according to the actual requirements along device widths direction successively by N+
Injection region and fin polysilicon gate alternately extend, and the left side of described first oxygen isolated area 104 is connected with the left side edge of described p-well 102,
The right side of described first oxygen isolated area 104 is connected with the left side of a described P+ injection region 105, on the right side of a described P+ injection region 105 and institute
The left side stating second oxygen isolated area 106 is connected, the left side phase of the right side of described second oxygen isolated area 106 and described built-in NMOS interdigital structure
Even；
Be sequentially provided with from left to right in the region, surface of described N trap 103 described embedded PMOS interdigital structure, described 3rd oxygen isolated area 120,
Described 4th N+ injection region 121 and described 4th oxygen isolated area 122, described embedded PMOS interdigital structure is by described 4th fin polysilicon gate
114, described 2nd P+ injection region 115, described 5th fin polysilicon gate 116, described 3rd P+ injection region 117, described 6th fin polysilicon
Grid 118, described 4th P+ injection region 119 are constituted, and can be noted by N+ successively along device widths direction according to the actual requirements in the range of device widths
Enter district and fin polysilicon gate alternately extends, the left side phase of the right side of described embedded PMOS interdigital structure and described 3rd oxygen isolated area 120
Even, the right side of described 3rd oxygen isolated area 120 is connected with the left side of described 4th N+ injection region 121, the right side of described 4th N+ injection region 121
Side is connected with the left side of described 4th oxygen isolated area 122, the right side of described 4th oxygen isolated area 122 and the right side edge phase of described N trap 103
Even；
Described polysilicon gate 113 across in described p-well 102 and the surface portion region of described N trap 103, the left side of described polysilicon gate 113 with
The right side of described built-in NMOS interdigital structure is connected, and the right side of described polysilicon gate 113 is connected with the left side of described embedded PMOS interdigital structure；
As in figure 2 it is shown, a described P+ injection region 105 is connected with the first metal 1 201, described N+ injection region 107 and second metal 1 202
Being connected, described first fin polysilicon gate 108 is connected with the 3rd metal 1 203, and described 2nd N+ injection region 109 is connected with the 4th metal 1 204,
Described second fin polysilicon gate 110 is connected with fifth metal 1 205, and described 3rd N+ injection region 111 is connected with the 6th metal 1 206, described
3rd fin polysilicon gate 112 is connected with the 7th metal 1 207, and described polysilicon gate 113 is connected with the 8th metal 1 208, described 4th fin
Polysilicon gate 114 is connected with the 9th metal 1 209, and described 2nd P+ injection region 115 is connected with the tenth metal 1 210, described 5th fin polycrystalline
Si-gate 116 is connected with the 11st metal 1 211, and described 3rd P+ injection region 117 is connected with the 12nd metal 1 212, described 6th fin polycrystalline
Si-gate 118 is connected with the 13rd metal 1 213, and described 4th P+ injection region 119 is connected with the 14th metal 1 214, described 4th N+ injection region
121 are connected with the 15th metal 1 215；
Described first metal 1 201, described second metal 1 202, described 3rd metal 1 203, described fifth metal 1 205, described 6th metal
1 206, described 7th metal 1 207 is all connected with the first metal 2 301, from described first metal 2 301 extraction electrode 304, as the gold of device
Belong to negative electrode；
Described 8th metal 1 208, described 9th metal 1 209, described tenth metal 1 210, described 11st metal 1 211, the described 13rd
Metal 1 213, described 14th metal 1 214 are all connected with the second metal 2 302 with described 15th metal 1 215, from described second metal 2 302
Extraction electrode 305, as the metal anode of device；
Described 4th metal 1 204 is connected with the 3rd metal 2 303, and described 12nd metal 1 212 is connected with described 3rd metal 2 303；
As it is shown on figure 3, by described metal anode, described N trap 103, described 4th N+ injection region 121, described 2nd P+ injection region 115,
Described 4th fin polysilicon gate 114, described polysilicon gate 113, described p-well 102, a described N+ injection region 107, described first
P+ injection region 105 and described metallic cathode one ESD big current drain path CP1 with LDMOS-SCR structure of composition, thus booster
The secondary failure electric current of part and voltage clamp ability；
By described metal anode, described N trap 103, described 4th N+ injection region 121, described 4th P+ injection region 119, the described 6th
Fin polysilicon gate 118, described 3rd P+ injection region 117, described p-well 102, described 2nd N+ injection region 109, described second fin
Formula polysilicon gate 110, described 3rd N+ injection region 111, a described P+ injection region 105 and described metallic cathode are constituted described in one article of source
The resistance-capacitance coupling trigger current path CP2 of embedded PMOS interdigital structure described in built-in NMOS interdigital structure and drain terminal, by fin grid shape
Described built-in NMOS interdigital structure and described embedded PMOS interdigital structure, increase the parasitic capacitance of device surface, thus improve the triggering of device
Electric current and opening speed；
As shown in Figure 4, when esd pulse acts on invention example device, by described N trap 103, described 4th P+ injection region 119, described
The described embedded PMOS interdigital structure that 6th fin polysilicon gate 118 and described 3rd P+ injection region 117 are constituted can equivalent parasitic capacitances Cp, institute
State electric capacity CpTrap resistance R with described N trap 103NWThe first resistance-capacitance coupling effect can be formed；Injected by described p-well 102, described 2nd N+
The described built-in NMOS interdigital structure that district 109, described second fin polysilicon gate 110 and described 3rd N+ injection region 111 are constituted can be posted in equivalence
Raw electric capacity Cn, described electric capacity CnTrap resistance R with described p-well 102PWThe second resistance-capacitance coupling effect can be formed；In described first resistance-capacitance coupling effect
The electric current in described p-well 102 or described N trap 103 dead resistance should can be improved with under the common effect of described second resistance-capacitance coupling effect.Work as institute
State resistance RNWOr described resistance RPWOn voltage when rapidly increasing to 0.7V, the parasitic triode Q1 of described LDMOS-SCR inside configuration
Or Q2 opens, thus form described ESD big current drain path CP1, thus improve the maintenance voltage and current of device.
Finally illustrating, above example is only in order to illustrate technical scheme and unrestricted, although entering the present invention with reference to preferred embodiment
Go detailed description, it will be understood by those within the art that, technical scheme can be modified or equivalent, and not
Departing from objective and the scope of technical solution of the present invention, it all should be contained in the middle of scope of the presently claimed invention.
Claims (4)
1. there is strong voltage and clamp down on the embedded high-voltage LDMOS-SCR device with ESD robustness, it include source built-in NMOS and
The resistance-capacitance coupling current path of drain terminal embedded PMOS interdigital structure and the ESD current drain path with LDMOS-SCR structure, with booster
The ESD robustness of part, improves voltage clamp ability, it is characterised in that: mainly by substrate P (101), p-well (102), N trap (103), the
One oxygen isolated area (104), a P+ injection region (105), second oxygen isolated area (106), a N+ injection region (107), the first fin
Polysilicon gate (108), the 2nd N+ injection region (109), the second fin polysilicon gate (110), the 3rd N+ injection region (111), the 3rd fin are many
Crystal silicon grid (112), polysilicon gate (113), the 4th fin polysilicon gate (114), the 2nd P+ injection region (115), the 5th fin polysilicon gate (116),
3rd P+ injection region (117), the 6th fin polysilicon gate (118), the 4th P+ injection region (119), the 3rd oxygen isolated area (120), the 4th
N+ injection region (121) and the 4th oxygen isolated area (122) are constituted；
Described p-well (102) and described N trap (103), described substrate P it is sequentially provided with from left to right in the region, surface of described substrate P (101)
(101) left side edge is connected with the left side edge of described p-well (102), the right side of described p-well (102) and a left side for described N trap (103)
Side is connected, and the right side of described N trap (103) is connected with the right side edge of described substrate P (101)；
Be sequentially provided with from left to right in the region, surface of described p-well (102) described first oxygen isolated area (104), a described P+ injection region (105),
Described second oxygen isolated area (106) and embedded MOS interdigital structure, described embedded MOS interdigital structure by a described N+ injection region (107),
Described first fin polysilicon gate (108), described 2nd N+ injection region (109), described second fin polysilicon gate (110), described 3rd N+
Injection region (111) and described 3rd fin polysilicon gate (112) are constituted, and can be according to the actual requirements along device widths side in the range of device widths
To alternately being extended by N+ injection region and fin polysilicon gate successively, the left side of described first oxygen isolated area (104) and described p-well (102)
Left side edge be connected, the right side of described first oxygen isolated area (104) is connected with the left side of a described P+ injection region (105), described first
P+ injection region (105) right side be connected with the left side of described second oxygen isolated area (106), the right side of described second oxygen isolated area (106) and
The left side of described embedded MOS interdigital structure is connected；
Be sequentially provided with from left to right in the region, surface of described N trap (103) embedded PMOS interdigital structure, described 3rd oxygen isolated area (120),
Described 4th N+ injection region (121) and described 4th oxygen isolated area (122), described embedded PMOS interdigital structure is by described 4th fin polycrystalline
Si-gate (114), described 2nd P+ injection region (115), described 5th fin polysilicon gate (116), described 3rd P+ injection region (117), institute
State the 6th fin polysilicon gate (118), described 4th P+ injection region (119) is constituted, and can be according to the actual requirements along device in the range of device widths
Part width is alternately extended by N+ injection region and fin polysilicon gate successively, the right side of described embedded PMOS interdigital structure and the described 3rd
The left side of field oxygen isolated area (120) is connected, the right side of described 3rd oxygen isolated area (120) and the left side of described 4th N+ injection region (121)
Being connected, the right side of described 4th N+ injection region (121) is connected with the left side of described 4th oxygen isolated area (122), described 4th oxygen isolation
The right side in district (122) is connected with the right side edge of described N trap (103)；
Described polysilicon gate (113) is across at described p-well (102) and the surface portion region of described N trap (103), described polysilicon gate (113)
Left side be connected with the right side of described built-in NMOS interdigital structure, the right side of described polysilicon gate (113) and described embedded PMOS interdigital structure
Left side be connected；
A described P+ injection region (105) is connected with the first metal 1 (201), a described N+ injection region (107) and the second metal 1 (202)
Being connected, described first fin polysilicon gate (108) is connected with the 3rd metal 1 (203), described 2nd N+ injection region (109) and the 4th metal
1 (204) be connected, described second fin polysilicon gate (110) is connected with fifth metal 1 (205), described 3rd N+ injection region (111) and
6th metal 1 (206) is connected, and described 3rd fin polysilicon gate (112) is connected with the 7th metal 1 (207), described polysilicon gate (113)
Being connected with the 8th metal 1 (208), described 4th fin polysilicon gate (114) is connected with the 9th metal 1 (209), described 2nd P+ injection region
(115) being connected with the tenth metal 1 (210), described 5th fin polysilicon gate (116) is connected with the 11st metal 1 (211), and the described 3rd
P+ injection region (117) is connected with the 12nd metal 1 (212), described 6th fin polysilicon gate (118) and the 13rd metal 1 (213) phase
Even, described 4th P+ injection region (119) is connected with the 14th metal 1 (214), described 4th N+ injection region (121) and the 15th metal 1
(215) it is connected；
Described first metal 1 (201), described second metal 1 (202), described 3rd metal 1 (203), described fifth metal 1 (205), institute
State the 6th metal 1 (206), described 7th metal 1 (207) is all connected with the first metal 2 (301), draws from described first metal 2 (301)
Go out electrode (304), as the metallic cathode of device；
Described 8th metal 1 (208), described 9th metal 1 (209), described tenth metal 1 (210), described 11st metal 1 (211),
Described 13rd metal 1 (213), described 14th metal 1 (214) and described 15th metal 1 (215) all with the second metal 2 (302)
It is connected, from described second metal 2 (302) extraction electrode (305), as the metal anode of device；
Described 4th metal 1 (204) is connected with the 3rd metal 2 (303), described 12nd metal 1 (212) and described 3rd metal 2 (303)
It is connected.
A kind of have strong voltage and clamp down on the embedded high-voltage LDMOS-SCR device with ESD robustness, its feature
It is: at drain-end region, by described 4th fin polysilicon gate (114), described 2nd P+ injection region (115), described 5th fin polysilicon gate
(116), the institute that described 3rd P+ injection region (117), described 6th fin polysilicon gate (118), described 4th P+ injection region (119) are constituted
State embedded PMOS interdigital structure, the maintenance voltage of device can be improved, strengthen the voltage clamp ability of device.
A kind of have strong voltage and clamp down on the embedded high-voltage LDMOS-SCR device with ESD robustness, its feature
Be: in source-end region, by a described N+ injection region (107), described first fin polysilicon gate (108), described 2nd N+ injection region (109),
It is described interior that described second fin polysilicon gate (110), described 3rd N+ injection region (111) and described 3rd fin polysilicon gate (112) are constituted
Embedding NMOS interdigital structure, it is possible to decrease the trigger voltage of device, increases ESD robustness and the voltage clamp ability of device.
A kind of have strong voltage and clamp down on the embedded high-voltage LDMOS-SCR device with ESD robustness, its feature
It is: described embedded PMOS interdigital structure and described built-in NMOS interdigital structure can increase the parasitic capacitance of device, makees at transient state esd pulse
Under with, because resistance-capacitance coupling effect can increase the trigger current in the dead resistance of described p-well (102) and described N trap (103), reduce device
Trigger voltage, strengthens the voltage clamp ability of device, improves the surface current conducting homogeneity of device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620186167.6U CN205385023U (en) | 2016-03-11 | 2016-03-11 | Embedded high -pressure LDMOS -SCR device with strong voltage clamp system and ESD robustness |
Applications Claiming Priority (1)
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| CN201620186167.6U CN205385023U (en) | 2016-03-11 | 2016-03-11 | Embedded high -pressure LDMOS -SCR device with strong voltage clamp system and ESD robustness |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017152414A1 (en) * | 2016-03-11 | 2017-09-14 | 江南大学 | Embedded high-voltage ldmos-scr device having strong voltage clamping and esd robustness |
| CN105633075B (en) * | 2016-03-11 | 2018-04-03 | 江南大学 | A kind of embedded high-voltage LDMOS SCR devices clamped down on strong voltage with ESD robustness |
| CN108109997A (en) * | 2017-12-15 | 2018-06-01 | 江南大学 | A kind of method that low pressure ESD protection performance is improved using trap cutting techniques |
| CN113270400A (en) * | 2021-05-21 | 2021-08-17 | 南京邮电大学 | SCR-LDMOS type ESD protection device with embedded double MOS trigger |
-
2016
- 2016-03-11 CN CN201620186167.6U patent/CN205385023U/en not_active Withdrawn - After Issue
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017152414A1 (en) * | 2016-03-11 | 2017-09-14 | 江南大学 | Embedded high-voltage ldmos-scr device having strong voltage clamping and esd robustness |
| CN105633075B (en) * | 2016-03-11 | 2018-04-03 | 江南大学 | A kind of embedded high-voltage LDMOS SCR devices clamped down on strong voltage with ESD robustness |
| US10290627B2 (en) | 2016-03-11 | 2019-05-14 | Jiangnan University | Embedded high voltage LDMOS-SCR device with a strong voltage clamp and ESD robustness |
| CN108109997A (en) * | 2017-12-15 | 2018-06-01 | 江南大学 | A kind of method that low pressure ESD protection performance is improved using trap cutting techniques |
| CN108109997B (en) * | 2017-12-15 | 2020-08-04 | 江南大学 | Method for improving low-voltage ESD protection performance by using trap segmentation technology |
| CN113270400A (en) * | 2021-05-21 | 2021-08-17 | 南京邮电大学 | SCR-LDMOS type ESD protection device with embedded double MOS trigger |
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