CN205376542U - Crystalline silicon solar battery - Google Patents
Crystalline silicon solar battery Download PDFInfo
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- CN205376542U CN205376542U CN201521126191.2U CN201521126191U CN205376542U CN 205376542 U CN205376542 U CN 205376542U CN 201521126191 U CN201521126191 U CN 201521126191U CN 205376542 U CN205376542 U CN 205376542U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
The utility model provides a crystalline silicon solar battery, be in including silicon chip and setting horizontal vice grid lines of four bar positive main grid lines of silicon chip, many and encircleing the frame electrode grid line of the positive edge of silicon chip, horizontal vice grid line with the main grid line is mutually perpendicular, the front of silicon chip includes second area that lies in the rectangle in the middle part of this silicon chip and the first region of surrounding this second area, between the horizontal vice grid line in the second area closely spaced in interval between the horizontal vice grid line of first region intra -area, article four, the grid line is parallel to each other, and just two are located the outside the main grid line is located the line of demarcation in second area and first region lies in two inboard main grid lines and passes first region and second area, the both ends of main grid line all extend to frame electrode grid line. The utility model discloses crystalline silicon solar battery has improved crystalline silicon solar cells's conversion efficiency, has reduced manufacturing cost.
Description
Technical field
This utility model relates to a kind of battery, particularly relates to a kind of crystal-silicon solar cell.
Background technology
Current crystal-silicon solar cell industrialization technology is highly developed, but compared with conventional energy resource, the product quality of of a relatively high cost, relatively low efficiency and high-quality constrains its development, therefore, how to make crystal-silicon solar cell have high conversion efficiency, low cost is always up the major trend of crystal-silicon solar cell industry development, is also the target pursued of technical research person.
In affecting the factor of crystal-silicon solar cell conversion efficiency and assembly life-span, battery front side gate line electrode is one of them key factor, and it is responsible for the photogenerated current in cell body to draw outside batteries；Simultaneously when battery being made assembly and welding rod play the effect of conduction electric current, its design is to collect photoelectric current to greatest extent.Existing crystal-silicon solar cell front electrode, generally comprise the some secondary grid line transversely arranged, to being provided with 2-4 root main gate line along the direction vertical with secondary grid line, main gate line and secondary grid line conducting, the width of main gate line is more than the width of secondary grid line, and in existing electrode structure, main gate line and secondary grid line are generally all equidistantly be uniformly distributed.But, along with going deep into of research and development, it has been found that silicon chip sheet resistance (diffused sheet resistance) after diffusion is not equally distributed.
This is because, at present, the diffusion PN junction technique of crystal-silicon solar cell is adulterated mostly in tubular diffusion furnace, due to silicon chip distance in Quartz stove tube only small (about 2.5mm), the difficulty that diffusive gas flow enters into silicon chip central area is big compared with marginal area, and the centre of silicon chip is difficult to obtain the doped source with surrounding equivalent, and after causing diffusion, silicon chip sheet resistance centre impurity concentration is low, therefore, often there is the phenomenon that the square resistance of core is higher in silicon chip after diffusion.On the other hand the PN junction degree of depth is also had and has a great impact by temperature.Owing to tubular diffusion furnace is to be heated in the surrounding of quartz ampoule, this just easily causes the temperature of silicon chip in quartz ampoule is uneven, silicon chip central portion temp is slightly below surrounding, cause silicon chip core impurity source diffusion depth inadequate, thus causing that the sheet resistance of silicon chip core forms high square resistance region because junction depth is on the low side.And the average sheet resistance of silicon chip is more big, the difference of the average sheet resistance of silicon chip core and the average sheet resistance of marginal portion is also more big, and the raising of crystal-silicon solar cell photoelectric transformation efficiency will be brought adverse effect by this.
Under the background that cell piece efficiency requirements is improved, the average sheet resistance of crystalline silicon solar cell piece is increased to current 80-120 Ω/ from original 30-40 Ω/, even higher, the dead layer effect of diffusion layer is reduced with this, and improve the short wave response of battery, thus improving the conversion efficiency of cell piece；But shallow junction can cause the increase of cell piece series resistance, also lead to the average sheet resistance of cell piece front electrode core simultaneously and become big with the difference of the average sheet resistance of marginal portion, thus having influence on again the further raising of cell piece conversion efficiency.
At present, mainly through uniformly increasing main grid in battery front side electrode, secondary grid number to reduce the series resistance of cell piece, fill factor, curve factor is improved.The method of present this uniform increase grid line number, front side silver paste consumption can be increased and cause that the manufacturing cost of cell piece increases on the one hand, the increase of grid line also results in the increase of battery surface shading-area on the other hand, sheet resistance part on the low side for silicon chip edge, bring adverse influence on the contrary, also fail to effectively reduce the difference adverse effect of the average sheet resistance of battery front side core and the average sheet resistance of marginal portion, therefore, it is difficult to obtain good result.
Due to the square resistance skewness of silicon chip after diffusion, continue to adopt the electrode structure at right side of traditional main gate line with surface uniformity distribution and secondary grid line, can not meet battery for fully collecting and conduct the requirement of photo-generated carrier.Therefore, how reasonably design battery front side electrode structure, reach secondary grid line and match with diffused sheet resistance, make main gate line be fully contacted with secondary grid line simultaneously, improve the battery collection efficiency to photo-generated carrier, the final electrical property promoting cell piece, there is positive realistic meaning.
Secondly in silver slurry printing and sintering process, battery front side pair grid line also tends to the problem that can there are disconnected grid and empty print, significantly high resistance will be formed at this breakpoint place or empty print place, the transmission route of such photoelectric current is blocked, and is equivalent to circuit breaker, and the electronics of so empty print or disconnected gate part requires over other secondary grid line and converges in main gate line by electric current, consume one part of current, which adds the series resistance of solar cell, cause that electric current collection rate declines, thus reducing the efficiency of battery；If being packaged making assembly by these disconnected grid, empty printed battery sheet, disconnected grid, empty print place, it is also possible that the hot spot phenomenon of local pyrexia, reduce the service life of assembly.
Summary of the invention
The purpose of this utility model is in that to overcome above-mentioned the deficiencies in the prior art, it is provided that a kind of crystal-silicon solar cell that can improve photoelectric transformation efficiency.
Additional aspect of the present utility model and advantage will be set forth in part in the description, and partly will be apparent from from describe, or can the acquistion by practice of the present utility model.
According to an aspect of the present utility model, a kind of crystal-silicon solar cell, including silicon chip and four main gate line being arranged on described front side of silicon wafer, a plurality of laterally secondary grid line and the border electrode grid line being looped around described front side of silicon wafer edge, described laterally secondary grid line is perpendicular with described main gate line, the front of described silicon chip includes the second area being positioned at the rectangle in the middle part of this silicon chip and the first area surrounding this second area, the spacing being smaller than between the laterally secondary grid line in described first area between laterally secondary grid line in described second area, described four grid lines are parallel to each other, and two described main gate line being positioned at outside are positioned at the demarcation line of described second area and first area, it is positioned at two main gate line described first areas of traverse and the second area of inner side, the two ends of described main gate line all extend to described border electrode grid line.
According to an embodiment of the present utility model, being provided with the longitudinally secondary grid line that a plurality of and described main gate line is paralleled in described first area and in described second area, a plurality of described laterally secondary grid line is connected with a plurality of described longitudinally secondary grid line.
Being placed equidistant two longitudinally secondary grid lines between adjacent two main gate line in described second area, the middle position of adjacent two main gate line in described first area is provided with a longitudinally secondary grid line cut off by this second area.
Every described longitudinal pair grid line is made up of multiple spaced longitudinal grid line sections, and grid line section connects two adjacent laterally secondary grid lines longitudinally in each, and the distance between two longitudinal grid line sections is equal to the distance between two horizontal secondary grid lines.
Described main gate line includes multiple hollow out section connected successively and linkage section, and the upper surface of described hollow out section is provided with multiple through hole extending to described silicon chip upper surface, and described linkage section includes the connecting line of two two adjacent hollow out sections that are parallel to each other and connect.
The two ends of described main gate line are additionally provided with the tip that width is gradually reduced, and described tip is the V-type caved in centre.
The spacing between the main gate line of inner side of this main gate line being smaller than the described main gate line in outside and vicinity between two described main gate line of inner side.
To be provided with between this border electrode and main gate line between described border electrode grid line and main gate line equidistant longitudinal secondary grid line.
The width of described laterally secondary grid line is 0.03-0.045mm, and the width of described longitudinally secondary grid line is 0.03-0.045mm, and the width of described main gate line is 1.3-1.6mm.
Described laterally secondary grid line, the longitudinally width of secondary grid line and border electrode grid line are equal.
As shown from the above technical solution, advantage of the present utility model and having the active effect that
This utility model crystal-silicon solar cell, front side of silicon wafer is set to two different first areas and second area, laterally secondary grid line arrangement density in second area is bigger, solve that diffused sheet resistance is uneven and the distant bigger problem of battery front side electrode resistance caused of main gate line, improve the conversion efficiency of crystal silicon solar energy battery, reduce production cost.
Accompanying drawing explanation
Its example embodiment being described in detail by referring to accompanying drawing, of the present utility model above-mentioned and further feature and advantage will be apparent from.
Fig. 1 is the schematic diagram of the crystal-silicon solar cell of this utility model one embodiment；
Fig. 2 is the partial enlarged view at A place in Fig. 1；
Fig. 3 is the schematic diagram of wherein one end of main gate line in Fig. 1；
Fig. 4 is the schematic diagram showing first area in this utility model one embodiment；
Fig. 5 is the schematic diagram showing second area in this utility model one embodiment.
In figure: 11, main gate line；12, horizontal secondary grid line；13, longitudinal secondary grid line；14, border electrode grid line；15, silicon chip；22, horizontal secondary grid line；23, longitudinal secondary grid line.
Detailed description of the invention
It is described more fully with example embodiment referring now to accompanying drawing.But, example embodiment can be implemented in a variety of forms, and is not understood as limited to embodiment set forth herein；On the contrary, it is provided that these embodiments make this utility model will fully and completely, and the design of example embodiment is conveyed to those skilled in the art all sidedly.Accompanying drawing labelling identical in figure represents same or similar structure, thus will omit their detailed description.
Referring to Fig. 1 to and Fig. 5, the utility model discloses a kind of crystal-silicon solar cell, including four main gate line 11 in silicon chip 15 and the front being arranged on this silicon chip 15, a plurality of laterally secondary grid line, a frame gate electrode line 14 and a plurality of longitudinally secondary grid line.
Silicon chip 15 is used for receiving sunlight and irradiates.In the present embodiment, this silicon chip 15 is substantially square, and forms chamfering at its four edges to contract.Border electrode grid line 14 is a complete annular grid line, and this border electrode grid line 14 is looped around the edge in the front of this silicon chip 15, and, its width substantially 0.03-0.045mm, the distance of distance silicon chip 15 can at about 1mm.It should be pointed out that, the shape of above-mentioned silicon chip 15 is exemplary only, it is not intended that restriction of the present utility model, for instance, the shape of silicon chip 15 is alternatively other shapes such as rectangle or even circle.
This silicon chip 15 be divided into first area and second area, wherein, this second area is shaped as rectangle, and this second area is positioned at the middle part of silicon chip 15, and first area is around this second area, and from this second area to extending around to border electrode grid line 14.In second area and first area, it is provided with a plurality of laterally secondary grid line, specifically refers to the laterally secondary grid line 22 that Fig. 4 and Fig. 5, Fig. 4 show that the laterally secondary grid line 12, Fig. 5 in the first area of this utility model one embodiment shows in second area.Comparison diagram 4 and Fig. 5, known referring again to Fig. 1, the spacing of the laterally secondary grid line 12 being smaller than in this first area between the laterally secondary grid line 22 in this second area, it is to say, the arrangement density of the arrangement density of the laterally secondary grid line 22 in the second area laterally secondary grid line 12 that is higher than in first area.The spacing b=1.5mm between laterally secondary grid line 22 in the first area shown in spacing a=1.6mm, Fig. 5 between laterally secondary grid line 12 in the first area shown in the diagram
Thus, crystal-silicon solar cell of the present utility model, the characteristic distributions of square resistance after spreading according to silicon chip 15, front is divided into two regions, and in the two region, configurate the laterally secondary grid line that density is different, the grid line making the front of silicon chip 15 matches with diffused sheet resistance, it is possible to increase electronics is collected, and improves photoelectric transformation efficiency.Laterally the width of secondary grid line 12 and 22 can be 0.03-0.045mm.
By Fig. 1 and Fig. 5 it can be seen that four main gate line 11 in present embodiment are parallel to each other each other, and, four main gate line 11 are perpendicular with laterally secondary grid line 12.Article four, in main gate line 11, having two to be positioned at outside, two other is located opposite from inner side.As shown in Figure 1, the spacing between these four main gate line 11 is different, and specifically, the spacing between two main gate line of inner side is less than the main gate line being positioned at inner side of main gate line and this main gate line contiguous being positioned at outside.Namely, from when shown in Fig. 5, view is observed from left to right, Article 1, the spacing between main gate line and Article 2 main gate line is more than the spacing between Article 2 main gate line and Article 3 main gate line, Article 1, the spacing c=39mm between main gate line and Article 2 main gate line, spacing d=36mm between Article 2 main gate line and Article 3 main gate line, the spacing between Article 3 main gate line and Article 4 main gate line is 39mm.And the width of main gate line 11 can be 1.3-1.6mm.
Thus, owing to two main gate line 11 inside being positioned at are near the center of silicon chip 15, sheet resistance between two main gate line 11 of inner side is bigger, by reducing the spacing between these two main gate line 11, the length making the laterally secondary grid line 22 between these two main gate line 11 also correspondingly shortens, and the photogenerated current produced between these two main gate line 11 can arrive main gate line 11 through shorter path.
Two main gate line 11 being positioned at outside are positioned on the demarcation line of first area and second area.Being positioned at two main gate line 11 of inner side through this first area and second area, the two ends of these four main gate line 11 all extend to border electrode grid line 14.
Further, a plurality of longitudinally secondary grid line parallel with main gate line it is provided with in first area and in second area.These longitudinal secondary grid lines are connected with laterally secondary grid line.If consequently, it is possible to laterally there is disconnected grid, empty print phenomenon between secondary grid line 12 and 22 and main gate line 11, then photogenerated current can be conducted to other intact laterally secondary grid line from the longitudinally secondary grid line that disconnected grid occur, then is conducted to main gate line 11.Specifically, being placed equidistant two longitudinally secondary grid lines 23 between adjacent two main gate line in second area, the middle position of adjacent two main gate line 11 in first area is provided with a longitudinally secondary grid line 13 cut off by this second area.To be provided with between border electrode grid line 14 and main gate line 11 between this border electrode grid line 14 and main gate line 11 equidistant longitudinal secondary grid line.It is to say, the multiple longitudinally secondary grid lines 13 and 23 arranged on silicon chip 15 are substantially at and divide equally position between two main gate line or between main gate line and border electrode grid line.Longitudinally the width of secondary grid line 13 and 23 can be 0.03-0.045mm.In the present embodiment, longitudinally secondary grid line, the laterally width of secondary grid line and border electrode grid line are equal, are 0.04mm.
Longitudinally secondary grid line 13 and 23 can be continuous print line segment, can also be made up of multiple small and spaced longitudinal grid line sections, grid line section connects two adjacent laterally secondary grid lines longitudinally in each, and the distance between two longitudinal grid line sections is equal to the distance between two horizontal secondary grid lines.Consequently, it is possible to these longitudinal grid line sections can make any one horizontal secondary grid line can both be connected to a wherein laterally secondary grid line being adjacent.When disconnected grid occur any one secondary grid line, the photogenerated current at this pair grid line place can flow to other laterally secondary grid line 3 via longitudinal grid line section, then flows to main gate line 1.Owing to longitudinally secondary grid line 2 is made up of these longitudinal grid line sections, thus so both can reduce the materials'use amount of longitudinally secondary grid line, alleviate weight and reduce cost, and compared to continuous print longitudinally secondary grid line, additionally it is possible to increase effective light absorption area of battery front side.
From the figure 3, it may be seen that the main gate line 1 of present embodiment includes multiple hollow out section 11 connected successively and linkage section 12.Upper surface in hollow out section 11 is provided with multiple through hole extending to silicon chip 15 upper surface, in the present embodiment, these through holes be shaped as circular hole, but, this utility model is not limited by this, in other embodiments of the present utility model, the through hole in hollow out section 111 is alternatively other forms such as strip hole or polygonal hole.By increasing through hole, it is possible to reduce the surface area of hollow out section 111, correspondingly increase the illuminating area on silicon chip 15.Linkage section 112 includes the connecting line of two two adjacent hollow out sections 111 that are parallel to each other and connect.This linkage section 112 is owing to being made up of two lines bar, thus the area of the silicon chip 15 taken is less, it is possible to significantly more increase the illuminating area of silicon chip 15.
Furthermore, the tip 113 that width is gradually reduced it is additionally provided with at the two ends of main gate line 11.This tip 113 is connected to border electrode grid line.Width due to most advanced and sophisticated 113 is gradually reduced, it is thus possible to reduces silver slurry consumption, reduces main gate line 11 shading-area, improve battery short circuit electric current and fill factor, curve factor.In the present embodiment, most advanced and sophisticated is shaped as the V-type caved in centre, can reduce the area of most advanced and sophisticated 113 so on the one hand, also makes every one end of main gate line 11 and border electrode grid line 14 can have two junction points on the other hand, has good connection effect.It should be pointed out that, the shape of most advanced and sophisticated 113 is not limiting as, for instance, in other embodiments of the present utility model, the shape of most advanced and sophisticated 113 is alternatively other shapes such as triangle.
To sum up, the beneficial effects of the utility model are as follows.
1, the sheet resistance characteristic distributions after spreading according to silicon chip, front side of silicon wafer is set to two different first areas and second area, laterally secondary grid line arrangement density in second area is bigger, solve that diffused sheet resistance is uneven and the distant bigger problem of battery front side electrode resistance caused of main gate line, improve the conversion efficiency of crystal silicon solar energy battery, reduce production cost.
2, main gate line adopts segmentation structure design, in every main gate line, adjacent two hollow out sections are connected by the linkage section being made up of two parallel fine rules, and it is respectively arranged at two ends with tip in main gate line, to reduce the width at main gate line two ends, so can reduce silver slurry consumption, reduce main gate line shading-area, improve battery short circuit electric current and fill factor, curve factor, effectively reduce the production cost of cell piece further.
3, in order to, under the premise not increasing production cost, reach the optimization to battery front side grid line, improve the battery collection efficiency to photogenerated current, improve the disconnected grid impact on cell piece efficiency and assembly life-span simultaneously as much as possible.Sheet resistance characteristic distributions after spreading according to silicon chip separately designs the thin grid line increasing some parallel anelectrode main grids in first area and second area, the photogenerated current transmission path to main grid will be optimized to a great extent, reduce disconnected grid, void prints and distributes the photoelectric current transmission impact on short circuit current and battery conversion efficiency after giving birth to, and also reduces assembly hot spot phenomenon and the harmful effect to assembly life-span that assembly end local pyrexia causes simultaneously.
4, in width and the respective regions of longitudinally secondary grid line, border electrode grid line, laterally the width of secondary grid line is roughly equal, and longitudinally secondary grid line, all adopt discontinuity designs, so can reduce the materials'use amount of longitudinally secondary grid line 13,23, alleviate weight, reduce cost；Longitudinally secondary grid line 13,23 shading-area can be reduced again, it is ensured that effective light absorption area of battery.
More than it is particularly shown and described illustrative embodiments of the present utility model.It should be understood that this utility model is not limited to disclosed embodiment, on the contrary, this utility model intention contains the various amendments in the spirit and scope being included in claims and equivalent arrangements.
Claims (10)
1. a crystal-silicon solar cell, including silicon chip and four main gate line being arranged on described front side of silicon wafer, a plurality of laterally secondary grid line and the border electrode grid line being looped around described front side of silicon wafer edge, described laterally secondary grid line is perpendicular with described main gate line, it is characterized in that: the front of described silicon chip includes being positioned at the second area of the rectangle in the middle part of this silicon chip and around the first area of this second area, the spacing being smaller than between the laterally secondary grid line in described first area between laterally secondary grid line in described second area, described four grid lines are parallel to each other, and two described main gate line being positioned at outside are positioned at the demarcation line of described second area and first area, it is positioned at two main gate line described first areas of traverse and the second area of inner side, the two ends of described main gate line all extend to described border electrode grid line.
2. crystal-silicon solar cell according to claim 1, it is characterized in that, being provided with the longitudinally secondary grid line that a plurality of and described main gate line is paralleled in described first area and in described second area, a plurality of described laterally secondary grid line is connected with a plurality of described longitudinally secondary grid line.
3. crystal-silicon solar cell according to claim 2, it is characterized in that, being placed equidistant two longitudinally secondary grid lines between adjacent two main gate line in described second area, the middle position of adjacent two main gate line in described first area is provided with a longitudinally secondary grid line cut off by this second area.
4. crystal-silicon solar cell according to claim 1, it is characterized in that, every described longitudinally secondary grid line is made up of multiple spaced longitudinal grid line sections, grid line section connects two adjacent laterally secondary grid lines longitudinally in each, and the distance between two longitudinal grid line sections is equal to the distance between two horizontal secondary grid lines.
5. crystal-silicon solar cell according to claim 1, it is characterized in that, described main gate line includes multiple hollow out section connected successively and linkage section, the upper surface of described hollow out section is provided with multiple through hole extending to described silicon chip upper surface, and described linkage section includes the connecting line of two two adjacent hollow out sections that are parallel to each other and connect.
6. crystal-silicon solar cell according to claim 4, it is characterised in that the two ends of described main gate line are additionally provided with the tip that width is gradually reduced, described tip is the V-type caved in centre.
7. crystal-silicon solar cell according to claim 5, it is characterised in that the spacing between the main gate line of inner side of this main gate line being smaller than the described main gate line in outside and vicinity between two described main gate line of inner side.
8. crystal-silicon solar cell according to claim 2, it is characterised in that to be provided with between this border electrode and main gate line between described border electrode grid line and main gate line equidistant longitudinal secondary grid line.
9. crystal-silicon solar cell according to claim 1, it is characterised in that the width of described laterally secondary grid line is 0.03-0.045mm, the width of described longitudinally secondary grid line is 0.03-0.045mm, and the width of described main gate line is 1.3-1.6mm.
10. according to the arbitrary described crystal-silicon solar cell of claim 1 to 9, it is characterised in that described laterally secondary grid line, the longitudinally width of secondary grid line and border electrode grid line are equal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521126191.2U CN205376542U (en) | 2015-12-29 | 2015-12-29 | Crystalline silicon solar battery |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521126191.2U CN205376542U (en) | 2015-12-29 | 2015-12-29 | Crystalline silicon solar battery |
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| CN205376542U true CN205376542U (en) | 2016-07-06 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449797A (en) * | 2016-11-07 | 2017-02-22 | 刘锋 | Multi-grid solar cell |
| CN110957386A (en) * | 2018-09-21 | 2020-04-03 | 苏州阿特斯阳光电力科技有限公司 | Strip-shaped cell piece, solar cell piece and photovoltaic module |
| CN113013281A (en) * | 2019-12-20 | 2021-06-22 | 苏州阿特斯阳光电力科技有限公司 | Battery piece, alignment method thereof and photovoltaic module |
| CN113658098A (en) * | 2021-07-16 | 2021-11-16 | 江苏森标科技有限公司 | Method and system for detecting color spots of solar cell and storage medium |
| CN113690329A (en) * | 2021-08-27 | 2021-11-23 | 浙江晶科能源有限公司 | Battery piece, photovoltaic module and welding frock |
-
2015
- 2015-12-29 CN CN201521126191.2U patent/CN205376542U/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449797A (en) * | 2016-11-07 | 2017-02-22 | 刘锋 | Multi-grid solar cell |
| CN110957386A (en) * | 2018-09-21 | 2020-04-03 | 苏州阿特斯阳光电力科技有限公司 | Strip-shaped cell piece, solar cell piece and photovoltaic module |
| CN113013281A (en) * | 2019-12-20 | 2021-06-22 | 苏州阿特斯阳光电力科技有限公司 | Battery piece, alignment method thereof and photovoltaic module |
| CN113658098A (en) * | 2021-07-16 | 2021-11-16 | 江苏森标科技有限公司 | Method and system for detecting color spots of solar cell and storage medium |
| CN113658098B (en) * | 2021-07-16 | 2024-03-15 | 江苏森标科技有限公司 | Method, system and storage medium for detecting color spots of solar cell |
| CN113690329A (en) * | 2021-08-27 | 2021-11-23 | 浙江晶科能源有限公司 | Battery piece, photovoltaic module and welding frock |
| CN113690329B (en) * | 2021-08-27 | 2023-08-29 | 浙江晶科能源有限公司 | Battery piece, photovoltaic module and welding frock |
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