CN205304397U - Feeder automation tests monitored control system - Google Patents
Feeder automation tests monitored control system Download PDFInfo
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- CN205304397U CN205304397U CN201520919791.8U CN201520919791U CN205304397U CN 205304397 U CN205304397 U CN 205304397U CN 201520919791 U CN201520919791 U CN 201520919791U CN 205304397 U CN205304397 U CN 205304397U
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- 238000005259 measurement Methods 0.000 abstract description 3
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Abstract
The utility model relates to a feeder automation tests monitored control system, this feeder automation tests monitored control system includes: RTDS and power amplifier, the terminal of awaiting measuring, control workstation, computer, RTDS and power amplifier connect the terminal of awaiting measuring, the terminal connection that awaits measuring control workstation and computer. The utility model discloses set up computer, control workstation, RTDS and power amplifier, utilize modern computer control technique, communication technology and network technique etc. On the basis of original instrument and equipment, through network or serial ports to the data of treating the test terminal are received to specific stipulations, realize the supervision to telemetering measurement in the terminal data, remote signalling, and to the remote control of terminal monitoring devices, smooth implementation to distribution network automation is significant.
Description
Technical field
This utility model belongs to distribution network automated technical field, particularly relates to a kind of feeder automation test monitor system.
Background technology
At present, along with electrical network develops rapidly, the reliability requirement of safe power supply is more and more higher, the development of intelligent distribution network is inexorable trend, one of main contents that power distribution automation is built as intelligent grid, and its effect is directly connected to the success or failure of intelligent power distribution network construction, in recent years, along with the rapid development of China's economy, power industry, power system construction be also at a flourish new stage, increasing circuit will be had later and put into distribution automation system.
The construction of China's power distribution network is not taken seriously for a long time always, the distribution automation process making China far lags behind western developed country, the quality of life having had a strong impact on the people also governs expanding economy simultaneously, the present stage grid automation of China is just at the early-stage, this just requires that we must especially focus on the construction of current power distribution network, because only that good electrical network and distribution network automated the implementing smoothly of good electric network composition guarantee.
Ensure the reliability service of intelligent distribution network, need to carry out reliably to it, completely, efficient test, simultaneously need to the processing procedure of FA when getting information about grid collapses, this patent provides a kind of for the feeder automation test monitor system in system for distribution network of power, when power distribution network is carried out Faults Characteristic Analysis, can completely comprehensively understand when breaking down, the information that each monitor terminal of power distribution network collects, real-time grasp break down after the system processing procedure to fault, whether correct logic is processed with failure judgement, if the monitoring system that neither one is unified, often can only remove to recall the feedback information of each terminal one by one, can only from macroscopically judging that power distribution network whether can normal operation, the process of fault can not be carried out effectively careful analysis, in order to enable to grasp in real time the remote measurement of each terminal in test process, remote signalling data, simultaneously in order to the details of all switches seen more intuitively under each monitor terminal, therefore a set of efficient feeder automation test monitor system is essential.
Under traditional pattern, waste the plenty of time when, also not necessarily it can be found that power distribution network exist hidden danger, simultaneously to the location pinpointed the problems and follow-up correction efficiency all relatively low under.
Utility model content
This utility model is solve under traditional pattern, when the waste plenty of time, also not necessarily it can be found that the hidden danger that exists of power distribution network, problem under all relatively low of the location pinpointed the problems and follow-up corrections efficiency is provided the feeder automation test monitor system of a kind of simple in construction, easy to install, raising work efficiency simultaneously.
This utility model is adopted the technical scheme that by the technical problem solving to exist in known technology:
The feeder automation test monitor system of this utility model embodiment, this feeder automation test monitor system includes: RTDS and power amplifier, terminal to be measured, monitor workstation, computer;
RTDS and power amplifier connect terminal to be measured, and terminal to be measured connects monitor workstation and computer.
Further, described power amplifier includes prime power amplifier and secondary power amplifier.
Further, the described input of prime power amplifier is connected with the signal output part of virtual signal generator, and the outfan of described prime power amplifier is connected with the input of described secondary power amplifier.
Further, described prime power amplifier includes the first electric capacity, second electric capacity, 3rd electric capacity, 4th electric capacity, 5th electric capacity, first inductance, second inductance, first resistance, second resistance, 3rd resistance, first potentiometer, second potentiometer and the first transistor, first end of described first electric capacity is connected with the outfan of described virtual signal generator, second end of described first electric capacity is connected with the base stage of described the first transistor, first end of described first potentiometer is connected with the first end of described first resistance, second end of described first resistance is connected with the first end of the first end of described first inductance and described second electric capacity respectively, second end of described first inductance respectively with the colelctor electrode of described the first transistor, second end of the second electric capacity and the first end of described 3rd electric capacity connect, the emitter stage of described the first transistor is connected with the first end of the first end of described second resistance and described 5th electric capacity respectively, second end of described 5th electric capacity respectively with the sliding end of described first potentiometer, first end of the first potentiometer, first end of the second potentiometer connects, second end of described second resistance is connected with the second end of described second potentiometer and the sliding end of the second potentiometer respectively, first end of described 3rd electric capacity is connected with the input of the first end of described second inductance and described secondary power amplifier respectively, second end of described second inductance is connected with the first end of described 3rd resistance and the first end of described 4th electric capacity respectively, ground connection after second end of described 3rd resistance and the second end connection of described 4th electric capacity.
Further, described secondary power amplifier includes transistor seconds, 4th resistance, 5th resistance, 6th resistance, 7th resistance, 6th electric capacity, 7th electric capacity, 8th electric capacity, 9th electric capacity, tenth electric capacity, 11st electric capacity, 12nd electric capacity and the 3rd potentiometer, the base stage of described transistor seconds is connected with the second end of described 3rd electric capacity and the first end of described second inductance respectively, the colelctor electrode of described transistor seconds respectively with the first end of described 6th electric capacity, first end of the 7th electric capacity and the first end of described 3rd inductance connect, second end of described 6th electric capacity respectively with the first end of described 7th electric capacity, second end of the 3rd inductance, first end of the 8th electric capacity and the first end of described 4th inductance connect, second end of described 4th inductance is connected with the first end of power supply and described 9th electric capacity respectively, ground connection after second end of described 8th electric capacity and the second end connection of described 9th electric capacity, first end of described 3rd inductance respectively with the first end of described tenth electric capacity, first end of the 11st electric capacity and the first end of described 12nd electric capacity connect, second end of described tenth electric capacity is connected with the first end of described 5th resistance, second end of described 5th resistance be connected with the first end of described 6th resistance and the first end of described 7th resistance respectively after ground connection, second end of described 6th resistance is connected with the second end of described 11st electric capacity, second end of described 7th resistance is connected with the second end of described 12nd electric capacity, the emitter stage of described transistor seconds is connected with the first end of described 4th resistance, second end of described 4th resistance is connected with the first end of described 3rd potentiometer and the sliding end of described 3rd potentiometer respectively, second end ground connection of described 3rd potentiometer.
This utility model has the advantage that and has the benefit effect that owing to this utility model arranges computer, monitor workstation, RTDS and power amplifier, utilize modern computer control technology, communication technology and network technology etc., on the basis of original instrument and equipment, by network or serial ports, with specific stipulations, receive the data of terminal to be tested, it is achieved the supervision to remote measurement in terminal data, remote signalling, and the remote control to the monitored equipment of terminal;When testing at the scene, the real time data at circuit each point place can be seen intuitively during particularly in fault simulation, analysis for system FA function provides condition, that can graphically change objective interface sees the state of each switch in whole piece circuit simultaneously, the process of whole system fault insulation and resume can be seen clearly, thus this test monitor system is significant to the enforcement smoothly of distribution automation. This utility model is made up of prime power amplifier and secondary power amplifier, power amplifier gain can be made in wider passband relatively stable, the output signal of prime power amplifier as the input signal of secondary power amplifier, secondary power amplifier as last stage of transmitter power amplifier to obtain bigger output and higher efficiency.
Accompanying drawing explanation
Fig. 1 is the feeder automation test monitor system structural representation that this utility model embodiment provides;
In figure: 1, RTDS and power amplifier; 2, terminal to be measured; 3, monitor workstation; 4, computer.
Fig. 2 is the power amplifier structure schematic diagram that this utility model embodiment provides.
Detailed description of the invention
For summary of the invention of the present utility model, feature and effect can be further appreciated that, hereby enumerate following example, and it is as follows to coordinate accompanying drawing to describe in detail.
As it is shown in figure 1, the feeder automation test monitor system of this utility model embodiment is mainly made up of: RTDS and power amplifier 1, terminal to be measured 2, monitor workstation 3, computer 4;
RTDS and power amplifier 1 connect terminal 2 to be measured, and terminal 2 to be measured connects monitor workstation 3 and computer 4.
As shown in Figure 2, the combined power amplifier of this utility model, including prime power amplifier and secondary power amplifier, the described input of prime power amplifier is connected with the signal output part of virtual signal generator, the outfan of described prime power amplifier is connected with the input of described secondary power amplifier, described prime power amplifier includes the first electric capacity C1, second electric capacity C2, 3rd electric capacity C3, 4th electric capacity C4, 5th electric capacity C5, first inductance L1, second inductance L2, first resistance R1, second resistance R2, 3rd resistance R3, first potentiometer RP1, second potentiometer RP2 and the first transistor VT1, described first end of the first electric capacity C1 is connected with the outfan of described virtual signal generator, second end of described first electric capacity C1 is connected with the base stage of described the first transistor VT1, first end of described first potentiometer RP1 is connected with first end of described first resistance R1, second end of described first resistance R1 is connected with the first end of first end of described first inductance L1 and described second electric capacity C2 respectively, second end of described first inductance L1 respectively with the colelctor electrode of described the first transistor VT1, second end of the second electric capacity C2 and first end of described 3rd electric capacity C3 connect, the emitter stage of described the first transistor VT1 is connected with first end of described second resistance R2 and first end of described 5th electric capacity C5 respectively, second end of described 5th electric capacity C5 respectively with the sliding end of described first potentiometer RP1, first end of the first potentiometer RP1, first end of the second potentiometer RP2 connects, second end of described second resistance R2 is connected with second end of described second potentiometer RP2 and the sliding end of the second potentiometer RP2 respectively, first end of described 3rd electric capacity C3 is connected with first end of described second inductance L2 and the input of described secondary power amplifier respectively, second end of described second inductance L2 is connected with first end of described 3rd resistance R3 and first end of described 4th electric capacity C4 respectively, ground connection after second end of described 3rd resistance R3 and the second end connection of described 4th electric capacity C4.
Described secondary power amplifier includes transistor seconds VT2, 4th resistance R4, 5th resistance R5, 6th resistance R6, 7th resistance R7, 6th electric capacity C6, 7th electric capacity C7, 8th electric capacity C8, 9th electric capacity C9, tenth electric capacity C10, 11st electric capacity C11, 12nd electric capacity C12 and the three potentiometer RP3, the base stage of described transistor seconds VT2 is connected with the first end of second end of described 3rd electric capacity C3 and described second inductance L2 respectively, the colelctor electrode of described transistor seconds VT2 respectively with first end of described 6th electric capacity C6, first end of the 7th electric capacity C7 and first end of described 3rd inductance L3 connect, second end of described 6th electric capacity C6 respectively with first end of described 7th electric capacity C7, second end of the 3rd inductance L3, first end of the 8th electric capacity C8 and first end of described 4th inductance L4 connect, second end of described 4th inductance L4 is connected with the first end of power supply and described 9th electric capacity C9 respectively, ground connection after second end of described 8th electric capacity C8 and the second end connection of described 9th electric capacity C9, first end of described 3rd inductance L3 respectively with first end of described tenth electric capacity C10, first end of the 11st electric capacity C11 and first end of described 12nd electric capacity C12 connect, second end of described tenth electric capacity C10 is connected with first end of described 5th resistance R5, second end of described 5th resistance R5 be connected with first end of described 6th resistance R6 and first end of described 7th resistance R7 respectively after ground connection, second end of described 6th resistance R6 is connected with second end of described 11st electric capacity C11, second end of described 7th resistance R7 is connected with second end of described 12nd electric capacity C12, the emitter stage of described transistor seconds VT2 is connected with first end of described 4th resistance R4, second end of described 4th resistance R4 is connected with first end of described 3rd potentiometer RP3 and the sliding end of described 3rd potentiometer RP3 respectively, the second end ground connection of described 3rd potentiometer RP3.
In the present invention, test monitor system relates to herein below:
(1) the graphic interface form of expression of the monitoring each monitor terminal of system and each switch;
(2) combined floodgate of each switch in circuit represents with gate-dividing state different colours, and the folding situation of the on-load switch of whole piece circuit to be measured, chopper, interconnection switch etc. is very clear;
(3) only retaining the topological structure of circuit to be measured on graphic interface, unrelated circuit is display not;
(4) each switch can freely switch and shows below data:
Three-phase voltage: Ua, Ub, Uc;
Three-phase current: Ia, Ib, Ic;
Operating state: with monitor terminal communication state, tripping, return to school unsuccessfully, locking starts, locking terminates;
Other state: interconnection switch, SOE event, a distant place on the spot, earthing;
2, to each monitor terminal configuration of IP address in monitoring system so that it is consistent with the IP address of scene terminal to be measured, so as to get monitor terminal data;
3, this cover system according to the voltage x current data of each switch collected, can identify the position of interconnection switch, show in systems simultaneously automatically;
4, the information that monitor terminal collects is all that properly functioning distribution network is by the secondary side data after PT or CT, for tester, the data display of primary side can be more directly perceived, each monitor terminal can be respectively provided with the voltage x current proportionality coefficient of correspondence by this test monitor system, represent the no-load voltage ratio of CT or PT, show value can be multiplied by these coefficients by system automatically, and the three-phase voltage of the display on interface is all parameter during electrical network actual motion with the data of three-phase current when the time comes;
5, all there is bigger difference in the topology of each electrical network, therefore this monitoring system provides a network topology drawing instrument easy to use, utilizing this instrument quickly system to be tested to be modeled, the switch namely each monitor terminal monitored in the process of modeling is associated;
6, when testing, testing results monitoring software, software gets the data of each monitor terminal automatically, now needs a bit of time of waiting, the identification of waiting system interconnection switch, observes the communications status (communications status measures value 1 and 0) with each monitor terminal simultaneously:
(1) 1 represents that monitoring system is normal with terminal communication, and now the parameter of each switch under counterpart terminal all can normally show;
(2) 0 represent that monitoring system and terminal communication are unsuccessful;
7, utilize this test monitoring software that monitor terminal is assigned telecommand, after corresponding switch correct operation, the switch color that test monitor system is corresponding changes, it was shown that action success, as run into the situation such as switch failure, slow motion, it is possible to find out from system intuitively;
8, the communication protocol difference used according to different distribution network monitoring terminals, this test monitor system is prefixed many set common communication stipulations, it is possible to freely switch very easily with the demand at satisfied scene;
9, when certain point breaks down, monitoring system can automatically detect the fault message of monitor terminal, and Reflector is indicated in the abort situation of correspondence;
10, when circuit logic to be measured is correct, the on-off phenomenon shown by this monitoring software is as follows:
(1) outlet breaker is become the empty frame under gate-dividing state from the green display under "on" position;
(2) on-load switch of both sides, trouble point is become the empty frame under gate-dividing state from the green display of "on" position;
(3), after the some time, outlet breaker and the interconnection switch of fault down stream are become the green display under "on" position from the empty frame under gate-dividing state;
11, when carrying out power distribution network test, the key step utilizing this test monitor system is as follows:
(1) topological structure of electrical network to be measured and the address of each monitor terminal are understood;
(2) drawing instrument utilizing test monitor system draws out system topological figure according to the topological structure of network under test, and each switch in electrical network is associated with in the monitor terminal of correspondence according to on-site actual situations, note being easy to identify plus title annotation after drawing completes;
(3) address of monitor terminal is set, selects the stipulations used with monitor terminal communication simultaneously, the no-load voltage ratio of on-the-spot CT and PT is provided with;
(4) testing results monitoring system, treats that the parameters of all switches all shows, interconnection switch identification success;
(5) utilize this monitoring system that the switch in system is remotely controlled (during actual test, this switch can be analog switch);
(6) test is proceeded by, it is possible to from monitoring system, see the course of action of each switch in whole network and the status information of each switch intuitively, it is possible to quickly judge that whether the logical process function of system is correct.
The invention provides a kind of feeder automation test monitor system, when it can be tested at the scene, the real time data at circuit each point place can be seen intuitively during particularly in fault simulation, analysis for system FA function provides condition, that can graphically change objective interface sees the state of each switch in whole piece circuit simultaneously, the process of whole system fault insulation and resume can be seen clearly, thus this test monitor system is significant to the enforcement smoothly of distribution automation.
The above is only to preferred embodiment of the present utility model, not this utility model is done any pro forma restriction, every according to technical spirit of the present utility model to any simple modification made for any of the above embodiments, equivalent variations and modification, belong in the scope of technical solutions of the utility model.
Claims (4)
1. a feeder automation test monitor system, it is characterised in that this feeder automation test monitor system includes: RTDS and power amplifier, terminal to be measured, monitor workstation, computer;
RTDS and power amplifier connect terminal to be measured, and terminal to be measured connects monitor workstation and computer.
2. feeder automation test monitor system as claimed in claim 1, it is characterised in that described power amplifier includes prime power amplifier and secondary power amplifier.
3. feeder automation test monitor system as claimed in claim 2, it is characterized in that, the described input of prime power amplifier is connected with the signal output part of virtual signal generator, and the outfan of described prime power amplifier is connected with the input of described secondary power amplifier.
4. feeder automation test monitor system as claimed in claim 3, it is characterized in that, described prime power amplifier includes the first electric capacity, second electric capacity, 3rd electric capacity, 4th electric capacity, 5th electric capacity, first inductance, second inductance, first resistance, second resistance, 3rd resistance, first potentiometer, second potentiometer and the first transistor, first end of described first electric capacity is connected with the outfan of described virtual signal generator, second end of described first electric capacity is connected with the base stage of described the first transistor, first end of described first potentiometer is connected with the first end of described first resistance, second end of described first resistance is connected with the first end of the first end of described first inductance and described second electric capacity respectively, second end of described first inductance respectively with the colelctor electrode of described the first transistor, second end of the second electric capacity and the first end of described 3rd electric capacity connect, the emitter stage of described the first transistor is connected with the first end of the first end of described second resistance and described 5th electric capacity respectively, second end of described 5th electric capacity respectively with the sliding end of described first potentiometer, first end of the first potentiometer, first end of the second potentiometer connects, second end of described second resistance is connected with the second end of described second potentiometer and the sliding end of the second potentiometer respectively, first end of described 3rd electric capacity is connected with the input of the first end of described second inductance and described secondary power amplifier respectively, second end of described second inductance is connected with the first end of described 3rd resistance and the first end of described 4th electric capacity respectively, ground connection after second end of described 3rd resistance and the second end connection of described 4th electric capacity,
Described secondary power amplifier includes transistor seconds, 4th resistance, 5th resistance, 6th resistance, 7th resistance, 6th electric capacity, 7th electric capacity, 8th electric capacity, 9th electric capacity, tenth electric capacity, 11st electric capacity, 12nd electric capacity and the 3rd potentiometer, the base stage of described transistor seconds is connected with the second end of described 3rd electric capacity and the first end of described second inductance respectively, the colelctor electrode of described transistor seconds respectively with the first end of described 6th electric capacity, first end of the 7th electric capacity and the first end of described 3rd inductance connect, second end of described 6th electric capacity respectively with the first end of described 7th electric capacity, second end of the 3rd inductance, first end of the 8th electric capacity and the first end of described 4th inductance connect, second end of described 4th inductance is connected with the first end of power supply and described 9th electric capacity respectively, ground connection after second end of described 8th electric capacity and the second end connection of described 9th electric capacity, first end of described 3rd inductance respectively with the first end of described tenth electric capacity, first end of the 11st electric capacity and the first end of described 12nd electric capacity connect, second end of described tenth electric capacity is connected with the first end of described 5th resistance, second end of described 5th resistance be connected with the first end of described 6th resistance and the first end of described 7th resistance respectively after ground connection, second end of described 6th resistance is connected with the second end of described 11st electric capacity, second end of described 7th resistance is connected with the second end of described 12nd electric capacity, the emitter stage of described transistor seconds is connected with the first end of described 4th resistance, second end of described 4th resistance is connected with the first end of described 3rd potentiometer and the sliding end of described 3rd potentiometer respectively, second end ground connection of described 3rd potentiometer.
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