CN204966058U - Utilize negative voltage to get into circuit of chip testing mode - Google Patents
Utilize negative voltage to get into circuit of chip testing mode Download PDFInfo
- Publication number
- CN204966058U CN204966058U CN201520726843.XU CN201520726843U CN204966058U CN 204966058 U CN204966058 U CN 204966058U CN 201520726843 U CN201520726843 U CN 201520726843U CN 204966058 U CN204966058 U CN 204966058U
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- Prior art keywords
- switching tube
- negative voltage
- pin
- switch tube
- chip
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Abstract
The utility model discloses an utilize negative voltage to get into circuit of chip testing mode, switch tube M0's source connection power VDD, chip pin P1 and switch tube M1's drain electrode is connected in switch tube M0's drain electrode, switch tube M0's grid connecting resistance RO, switch tube M1's grid, switch tube M2's grid and switch tube M3's grid, resistance R0's other end ground connection, switch tube M3's source connection power VDD, switch tube M1's source connection switch tube M2's source electrode and not gate I9's input B, not gate I9's input A connects trigger DFF5's ON foot, chip pin PFI is connected to trigger DFF5's CP foot. The utility model provides a multiplexing IO pin needs the cooperation to apply the circuit that the negative voltage could get into the test mode, does not possess in technology under the condition of non -volatile storage, still can have a plurality of state modes behind chip package to can not influence the customer normally uses.
Description
Technical field
The utility model belongs to integrated circuit (IC) design field, proposes a kind of multiplexing I/O pin and need to coordinate to apply the circuit that negative voltage just can enter test pattern, simplifies production test flow process, conveniently analyzes debugging when chip goes wrong.
Background technology
Various inefficacy may be caused: the defect of material and process deviation all may to cause between the short circuit of circuit in chip, open circuit and device knot the problems such as break-through in semiconductor technology.And such physical failure must cause the fault of circuit function or aspect of performance.
The correctness that the basis such as line, transistor is manufactured is guaranteed in order to the fault of locating in manufacturing process by means of testing effectively.Original design needs to modify, and adds the test logic only just used in test process.Test logic is not only convenient to the automatic generation of high-quality test vector, also provides the highly efficient process of diagnosis ineffective part simultaneously.
The detection of fault comprises the activation of fault and transmission two steps of fault.Device pin adds one group of specific pumping signal, and when pumping signal is delivered to the node that there is fault, this node can present the state of mistake, and this process is called the activation of fault, and claims this specific fault to have controllability.Also will consider observe fault delivery to the output pin of chip is convenient to and expect different result, such fault is also referred to as having observability simultaneously.Due to circuit structure, unit and interconnected high complexity, guarantee that the requirement that each fault meets controllability and observability simultaneously just becomes very difficult, the test data transmitted and malfunction are very easy to " being flooded " in the circuit structure and circuit interconnects of complexity, all the more so in sequential logic design.So seek the pass through mechanism adding some rule in design circuit, facilitate input and the derivation of information, greatly can improve controllability and the observability of fault like this.
Usual IC product all has multiple state model, and modal is mode of operation and test pattern, state when the former is chip normal use, and the latter is the state of chip production test phase.
The performance of the stress produced in chip package process to chip has a certain impact, and trims so the major part chip high to accuracy requirement all can select to do circuit after packaging.This can bring a problem, namely the chip pin after encapsulating under normal circumstances is all the pin needing in application to use, if want these pins multiplexing to enter test pattern to carry out realizing circuit and trim, when then needing to guarantee chip normal use, client can not trigger and again enter test pattern in other words, so deviser generally can reserve some fuse and control circuit in chip, just fuse these fuse after completing circuit trims, and test pattern can not be entered.Above-mentioned this method relates to non-volatile memory module such as OTP, MTP and flash, and these all can increase the complexity of chip cost and design.
Therefore, prior art existing defects, needs to improve.
Utility model content
Problem to be solved in the utility model is to provide a kind of circuit utilizing negative voltage to enter chip test mode, to solve the problem proposed in above-mentioned background technology.
For achieving the above object, the utility model provides following technical scheme:
A kind of circuit utilizing negative voltage to enter chip test mode, comprise switching tube M0, switching tube M1, resistance R0 and not gate I9, the source electrode of described switching tube M0 connects power vd D, the drain electrode of switching tube M0 connects the drain electrode of chip pin P1 and switching tube M1, the grid contact resistance R0 of switching tube M0, the grid of switching tube M1, the grid of switching tube M2 and the grid of switching tube M3, the other end ground connection of resistance R0, the source electrode of switching tube M3 connects power vd D, the source electrode of source electrode connecting valve pipe M2 of switching tube M1 and the input end B of not gate I9, the input end A of not gate I9 connects the 0N pin of trigger DFF5, the CP pin of trigger DFF5 connects pin PFI.
As preferred version of the present utility model: the model of described trigger DFF5 is B418.
Preferably, described chip pin P1 and pin PFI is the I/O pin after chip package respectively.
Preferably, the voltage that described chip pin P1 applies is negative voltage.Furthermore, described negative voltage is DC voltage or pulse voltage.
Preferably, described switching tube M1 is NMOS tube, metal-oxide-semiconductor or triode.
Compared with prior art, the beneficial effects of the utility model are: the utility model proposes a kind of multiplexing I/O pin and need to coordinate applying negative voltage just can enter the circuit of test pattern, do not possess the condition of non-volatile memories in technique under, still can have multiple state model after chip package, and client's normal use can not be had influence on.
Accompanying drawing explanation
Fig. 1 is the circuit diagram utilizing negative voltage to enter the circuit of chip test mode.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, be clearly and completely described the technical scheme in the utility model embodiment, obviously, described embodiment is only the utility model part embodiment, instead of whole embodiments.Based on the embodiment in the utility model, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all belong to the scope of the utility model protection.
Refer to Fig. 1, a kind of circuit utilizing negative voltage to enter chip test mode, comprise switching tube M0, switching tube M1, resistance R0 and not gate I9, the source electrode of described switching tube M0 connects power vd D, the drain electrode of switching tube M0 connects the drain electrode of chip pin P1 and switching tube M1, the grid contact resistance R0 of switching tube M0, the grid of switching tube M1, the grid of switching tube M2 and the grid of switching tube M3, the other end ground connection of resistance R0, the source electrode of switching tube M3 connects power vd D, the source electrode of source electrode connecting valve pipe M2 of switching tube M1 and the input end B of not gate I9, the input end A of not gate I9 connects the 0N pin of trigger DFF5, the CP pin of trigger DFF5 connects pin PFI.
The model of trigger DFF5 is B418.
Principle of work of the present utility model is: P1 and PFI in circuit is 2 I/O pins after chip package, when P1 is within the scope of the normal working voltage of 0 ~ VDD, because VG node voltage value is GND, so M1 does not open, M2 and M3 opens, the magnitude of voltage of TM node is made to be VDD, and the magnitude of voltage of the QN node of DFF5 after electrification reset is also VDD, the logic of this Sheffer stroke gate of I9 is made to export as " 0 " i.e. GND, no matter at this moment PFI there is which type of waveform, all can not change output QN=" 1 " this state of DFF5, the mark that this state normally works as chip, when applying negative voltage on P1, as long as this negative voltage absolute value is greater than the raceway groove cut-in voltage of M1, i.e. threshold V T H, , M1 pipe will be opened, because the pull-up circuit ability of M2 and M3 composition is more weak, so the voltage of TM node is pulled low to " 0 ", Sheffer stroke gate I9 subsequently, logic exports and becomes " 1 ", as long as at this moment PFI pin provides a clock signal, the logic of QN exports and will become " 0 ", no matter PFI there is which type of waveform afterwards, all can not change the state of QN, unless DFF5 is reset, this state just enters the mark of test pattern as chip.The negative voltage of the upper applying of P1 can be DC voltage also can be pulse voltage; M1 is not limited only to NMOS tube, also can be the metal-oxide-semiconductor of other types, or triode, and many group serial or parallel connections also belong to the protection domain of this circuit structure.In above-mentioned, the magnitude of voltage of " 1 " correspondence is VDD, and the magnitude of voltage of " 0 " correspondence is GND.
Compared with prior art, the beneficial effects of the utility model are: the utility model proposes a kind of multiplexing I/O pin and need to coordinate applying negative voltage just can enter the circuit of test pattern, do not possess the condition of non-volatile memories in technique under, still can have multiple state model after chip package, and client's normal use can not be had influence on.
Claims (6)
1. the circuit utilizing negative voltage to enter chip test mode, comprise switching tube M0, switching tube M1, resistance RO and not gate I9, it is characterized in that, the source electrode of described switching tube M0 connects power vd D, the drain electrode of switching tube M0 connects the drain electrode of chip pin P1 and switching tube M1, the grid contact resistance RO of switching tube M0, the grid of switching tube M1, the grid of switching tube M2 and the grid of switching tube M3, the other end ground connection of resistance RO, the source electrode of switching tube M3 connects power vd D, the source electrode of source electrode connecting valve pipe M2 of switching tube M1 and the input end B of not gate I9, the input end A of not gate I9 connects the ON pin of trigger DFF5, the CP pin of trigger DFF5 connects chip pin PFI.
2. a kind of circuit utilizing negative voltage to enter chip test mode according to claim 1, is characterized in that, the model of described trigger DFF5 is B418.
3. a kind of circuit utilizing negative voltage to enter chip test mode according to claim 1, is characterized in that, described chip pin P1 and pin PFI is the I/O pin after chip package respectively.
4. a kind of circuit utilizing negative voltage to enter chip test mode according to claim 1, is characterized in that, the voltage that described chip pin P1 applies is negative voltage.
5. a kind of circuit utilizing negative voltage to enter chip test mode according to claim 4, it is characterized in that, described negative voltage is DC voltage or pulse voltage.
6. a kind of circuit utilizing negative voltage to enter chip test mode according to claim 1, it is characterized in that, described switching tube M1 is NMOS tube, metal-oxide-semiconductor or triode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520726843.XU CN204966058U (en) | 2015-09-18 | 2015-09-18 | Utilize negative voltage to get into circuit of chip testing mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520726843.XU CN204966058U (en) | 2015-09-18 | 2015-09-18 | Utilize negative voltage to get into circuit of chip testing mode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204966058U true CN204966058U (en) | 2016-01-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520726843.XU Expired - Fee Related CN204966058U (en) | 2015-09-18 | 2015-09-18 | Utilize negative voltage to get into circuit of chip testing mode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204966058U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105207657A (en) * | 2015-09-18 | 2015-12-30 | 芯佰微电子（北京）有限公司 | Circuit switched to chip testing mode by utilizing negative voltage |
| CN108196181A (en) * | 2017-12-18 | 2018-06-22 | 上海艾为电子技术股份有限公司 | A kind of chip test mode access method, into system and chip |
| CN115602237A (en) * | 2022-11-25 | 2023-01-13 | 成都利普芯微电子有限公司（Cn） | Chip trimming circuit and method and driving chip |
-
2015
- 2015-09-18 CN CN201520726843.XU patent/CN204966058U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105207657A (en) * | 2015-09-18 | 2015-12-30 | 芯佰微电子（北京）有限公司 | Circuit switched to chip testing mode by utilizing negative voltage |
| CN105207657B (en) * | 2015-09-18 | 2017-12-22 | 芯佰微电子（北京）有限公司 | A kind of circuit for entering chip test mode using negative voltage |
| CN108196181A (en) * | 2017-12-18 | 2018-06-22 | 上海艾为电子技术股份有限公司 | A kind of chip test mode access method, into system and chip |
| CN115602237A (en) * | 2022-11-25 | 2023-01-13 | 成都利普芯微电子有限公司（Cn） | Chip trimming circuit and method and driving chip |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160113 Termination date: 20190918 |