CN104935324A - Double-through-silicon-via (TSV) online self-fault-tolerance structure - Google Patents
Double-through-silicon-via (TSV) online self-fault-tolerance structure Download PDFInfo
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Abstract
The invention discloses a double-through-silicon-via (TSV) online self-fault-tolerance structure. The double-through-silicon-via online self-fault-tolerance structure comprises a leakage current closing structure, a transient discharging structure, TSVs, an or gate, a node in and an output out, wherein the leakage current closing structure comprises a first delay buffer, a second delay phase inverter, a first three-state buffer, a second three-state buffer, a first NAND gate and a second NAND gate; the transient discharging structure comprises a first NOR gate, a second NOR gate, a first delay phase inverter, a second delay phase inverter, a first NMOS (N-Channel Metal Oxide Semiconductor) transistor and a second NMOS transistor in sequence; and the TSVs comprise a first TSV and a second TSV in sequence. On the premise of no testing time or circuit port overhead and no influence on normal work of a circuit, online fault tolerance is performed on the leakage faults of the TSVs and the resistor open-circuit faults, so that the yield and reliability of a three-dimensional integrated circuit are effectively improved.
Description
Technical field
The invention belongs to very lagre scale integrated circuit (VLSIC) fault-toleranr technique field, be specifically related to a kind of two silicon through hole online from fault-tolerant architecture.
Background technology
Three dimensional integrated circuits is a kind of emerging technology, is subject to the attention of more and more industrial quarters and academic member.Different with two-dimensional integrated circuit, three dimensional integrated circuits by multiple wafer vertical stacking, shortens the length of interconnection line between wafer by silicon through hole (Through Silicon Via, TSV).It has low in energy consumption, and bandwidth is high, and area is little, and performance is good, supports the advantages such as Manufacturing resource.But 1) manufacturing process of TSV is not yet ripe, leakage failure and the resistive-open fault of TSV have a strong impact on its yield and reliability.TSV Numerous in circuit, a TSV breaks down and will damage whole chip, along with the increase of the wafer stacking number of plies, TSV lost efficacy the three dimensional integrated circuits yield caused loss exponentially property increase.2) incipient fault of TSV is difficult to repair, and along with circuit working can be serious all the more, finally causes circuit to occur functional fault.3) integrated level of three dimensional integrated circuits is far above two-dimentional chip, but package pins can only be placed in the surrounding of chip, therefore three dimensional integrated circuits package pin number is substantially identical with two-dimentional chip, cause the test resource distributing to each unit relatively to tail off, controllability and the observability of test all decline.Therefore, a kind of online fault-tolerant networks of the TSV of the test process of TSV of can avoiding is proposed very necessary.
At present, TSV fault-tolerant networks mainly can be divided three classes: test fault-tolerant, test fault-tolerant, double T SV fault-tolerant networks online.
Test fault-tolerant networks effectively can improve the yield of three dimensional integrated circuits, but there is following problem: 1) need test cost: the TSV broken down must be detected in advance, could repair it, by the expense of testing time and circuit port, be incorporated into TSV fault-tolerant in.2) test resource is not enough: the integrated level of three dimensional integrated circuits is far above two-dimentional chip, but package pins can only be placed in the surrounding of chip, therefore three dimensional integrated circuits package pin number is substantially identical with two-dimentional chip, causes the test resource distributing to each unit relatively to tail off.3) do not support that TSV is fault-tolerant online: the incipient fault of TSV is difficult to repair, along with circuit working can be serious all the more, but the program does not support that TSV is fault-tolerant online, finally causes circuit to occur functional fault, affects the reliability of circuit.
Test the reliability that online fault-tolerant networks effectively can improve three dimensional integrated circuits, but when carrying out fault-tolerant to TSV, 1) still need to test TSV, consume the test resource of three dimensional integrated circuits; 2) the normal work of its TSV test and circuit reconfiguration process meeting interrupt circuit.
Double T SV fault-tolerant networks can avoid the test process of TSV, realizes the fault-tolerant online of TSV.But there is following problem in this structure: 1) when signal transmission, circuit generating function fault; 2) leakage current of leakage failure TSV is larger.Fig. 1 is double T SV fault-tolerant networks structure principle chart, and it is made up of two symmetrical passages (passage 1 and passage 2 also deposit metal-oxide-semiconductor in the channel 1 and door in passage 2).For passage 1, by the holding tube of PMOS MP3 as TSV (19) signal, its conducting resistance is large, assuming that leakage failure occurs TSV (19), during node i n=0, fault TSV (19) leakage current reduces to some extent.But it is conducting still, leakage current is larger.NMOS tube MN5 and the first inverter (17) composition discharging structure, as node node 1=0, discharge (passage 2 and passage 1 symmetry also exist 0 and drive path e) to passage 2.Node i n=1, node node 1=0, NMOS tube MN5 opens, but node node 2 is also in transmission 0, on output without impact.Node i n=0 subsequently, PMOS MP1 and MP2 start TSV (19) capacitor charging.When charging just starts, electric charge in TSV 3 (19) electric capacity is 0, and node node 1=0, node t1 are discharged to node node 2 by NMOS tube MN5 and the first inverter (17), make node node 2 electric capacity always cannot stored charge, node 2 remains 0.In like manner, passage 2 and passage 1 symmetry, also can produce same situation when signal transmits in passage 2, makes the consistent inhibit signal 0 of node node 1.In sum, there is stuck at 1 fault from fault-tolerant networks output (out) online in double T SV.
Summary of the invention
The object of this invention is to provide a kind of two silicon through hole online from fault-tolerant architecture, solve existing test fault-tolerant networks, need TSV test process, and do not support the problem that TSV is fault-tolerant online; The online fault-tolerant networks of existing test, needs the problem of test and circuit reconfiguration expense; The structural sequence problem of the online fault-tolerant networks of double T SV, and can leakage current be further reduced; The present invention has simple to operate, the advantage of practical grade.
The technical solution used in the present invention is:
A kind of two silicon through hole, online from fault-tolerant architecture, is characterized in that, comprises leakage current closing structure, of short duration discharging structure, TSV or door (15), node i n and exports out; Described leakage current closing structure includes the first delay buffer (1), second successively and postpones inverter (2), the first tristate buffer (3), the second tristate buffer (4), the first NAND gate (5) and the second NAND gate (6); Of short duration discharging structure includes the first NOR gate (7) successively, the second NOR gate (8), first postpones inverter (9), second and postpones inverter (10), the first NMOS tube (11) and the second NMOS tube (12); TSV includes a TSV (13) and the 2nd TSV (14) successively; Described node i n is the input of the first delay buffer (1), the second delay buffer (2), the first tristate buffer (3), the second tristate buffer (4); The output (n3) of the first delay buffer (1) is connected with the first NAND gate (5) input a, the output (n7) of the first tristate buffer (3) is connected through the input b of inverter with the first NAND gate (5), and the first NAND gate (5) output (n5) is connected with the control end of the first tristate buffer (3); Second output (n4) postponing inverter (2) is connected with the input a of the second NAND gate (6), the output (n8) of the second tristate buffer (4) is connected through the input b of inverter with the second NAND gate (6), and the output (n6) of the second NAND gate (6) is connected with the control end of the second tristate buffer (4); The input (n7) of the one TSV (13) is connected with the output of the first tristate buffer (3), and the input (n8) of the 2nd TSV (14) is connected with the second tristate buffer (4) output; The input a of the output (n1) respectively with the first NOR gate (7) of the one TSV (13), the input of the first delay inverter (9), the drain electrode of the second NMOS tube (12) or the input a of door (15) are connected; The input b of the output (n2) respectively with the second NOR gate (8) of the 2nd TSV (14), the input of the second delay inverter (10), the drain electrode of the first NMOS tube (11) or the input b of door (15) are connected; The output (n12) of the first NOR gate (7) is connected with the grid of the first NMOS tube (11), and the output (n10) of the second NOR gate (8) is connected with the grid of the second NMOS tube (12); First postpones inverter (9) output (n11) is connected with the input b of the first NOR gate (7), and the second output (n9) postponing inverter (10) is connected with the input a of the second NOR gate (8); The source class ground connection of the first NMOS tube (11) and the second NMOS tube (12); Or door (15) output is this structure output out.
The two silicon through hole of described one is online from fault-tolerant architecture, and it is characterized in that, described the first delay buffer (1) and the delay of the second delay buffer (2) (are assumed to t
buffer) equal, slightly larger than signal from node i n to a TSV (13) with the rise edge delay of the 2nd TSV (14) input (node n7 and n8).
The two silicon through hole of described one, online from fault-tolerant architecture, is characterized in that, the described first delay postponing inverter (9) and the second delay inverter (10) (is assumed to t
delay) equal, slightly larger than signal from node i n to a TSV (13) and the 2nd TSV (14) output (node n1 and n2) trailing edge postpone.
The two silicon through hole of described one is online from fault-tolerant architecture, and it is characterized in that, a described TSV (13) is identical with the electric parameter of the 2nd TSV (14).
Beneficial effect of the present invention is:
The present invention utilizes leakage current closing structure to shield TSV leakage failure to the impact of circuit; Utilize of short duration discharging structure to shield resistive-open fault to the impact of circuit, can realize leaking TSV and resistive-open two kinds of faults fault-tolerant, the yield of whole circuit and reliability are greatly improved; The feature of fault-tolerant architecture proposed by the invention is from fault-tolerant networks, can avoid the test process of TSV, and the normal work of interrupt circuit does not provide that TSV's is fault-tolerant online, and circuit structure and practical operation simple.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and case study on implementation, the present invention is further described.
Fig. 1 is existing double T SV fault-tolerant networks structural circuit schematic diagram.
Fig. 2 is that of the present invention pair of silicon through hole is online from fault-tolerant architecture circuit theory diagrams.
When Fig. 3 is TSV (13) fault-free, the 2nd TSV (14) leakage failure, leakage structure closing structure truth table of the present invention.
Fig. 4 is the 2nd TSV (14) fault-free, TSV (13) resistive-open fault, during without of short duration discharging structure, or door output principle figure.
Fig. 5 is the two of short duration discharging structure fundamental diagram of silicon through hole online in fault-tolerant architecture of the present invention.
Embodiment
In order to the object, technical scheme and the advantage that make we bright are more clear, below in conjunction with accompanying drawing, the present invention is described in more detail.Concrete case study on implementation described herein, only for explaining explanation the present invention, is not intended to limit the present invention.Figure 2 shows that the circuit theory diagrams of TSV fault-tolerant architecture of the present invention, its concrete structure is as follows:
A kind of two silicon through hole, online from fault-tolerant architecture, comprises leakage current closing structure, of short duration discharging structure, TSV or door 15, node i n and exports out; Described leakage current closing structure includes the first delay buffer 1, second successively and postpones inverter 2, first tristate buffer 3, second tristate buffer 4, first NAND gate 5 and the second NAND gate 6; Of short duration discharging structure includes the first NOR gate 7, second NOR gate 8, first successively and postpones inverter 9, second delay inverter 10, first NMOS tube 11 and the second NMOS tube 12; TSV includes a TSV13 and the 2nd TSV14 successively; Described node i n is the input of the first delay buffer 1, second delay buffer 2, first tristate buffer 3, second tristate buffer 4; The output n3 of the first delay buffer 1 is connected with the first NAND gate 5 input a, the output n7 of the first tristate buffer 3 is connected through the input b of inverter with the first NAND gate 5, and the first NAND gate 5 output n5 is connected with the control end of the first tristate buffer 3; The second output n4 postponing inverter 2 is connected with the input a of the second NAND gate 6, the output n8 of the second tristate buffer 4 is connected through the input b of inverter with the second NAND gate 6, and the output n6 of the second NAND gate 6 is connected with the control end of the second tristate buffer 4; The input n7 of the one TSV13 is connected with the output of the first tristate buffer 3, and the input n8 of the 2nd TSV14 is connected with the second tristate buffer 4 output; The input a of output n1 respectively with the first NOR gate 7 of the one TSV13, the input of the first delay inverter 9, the drain electrode of the second NMOS tube 12 or the input a of door 15 are connected; The input b of output n2 respectively with the second NOR gate 8 of the 2nd TSV14, the input of the second delay inverter 10, the drain electrode of the first NMOS tube 11 or the input b of door 15 are connected; The output n12 of the first NOR gate (7) is connected with the grid of the first NMOS tube 11, and the output n10 of the second NOR gate 8 is connected with the grid of the second NMOS tube 12; First postpones inverter 9 output n11 is connected with the input b of the first NOR gate 7, and the second output n9 postponing inverter 10 is connected with the input a of the second NOR gate 8; The source class ground connection of the first NMOS tube 11 and the second NMOS tube 12; Or door 15 output is this structure output out.
The delay of the first delay buffer 1 and the second delay buffer 2 (is assumed to t
buffer) equal, slightly larger than signal from node i n to a TSV13 with the rise edge delay of the 2nd TSV14 input (node n7 and n8).
First delay postponing inverter 9 and the second delay inverter 10 (is assumed to t
delay) equal, slightly larger than signal from node i n to a TSV13 and the 2nd TSV14 output (node n1 and n2) trailing edge postpone.
One TSV13 is identical with the electric parameter of the 2nd TSV14.
the principle that the present invention filters leakage failure is as follows:
Assuming that leakage failure occurs the 2nd TSV14, first, input an initialize signal 0 to node i n.Subsequently, node i n=1, in the time of delay of the first delay buffer (1)
t bufferin, it is that to export n5 be the 1, first tristate buffer 3 conducting to the 0, first NAND gate 5 that the first delay buffer 1 exports n3, draws high the voltage of its output node n7.Through the time of delay of the first delay buffer 1
t bufferafter, it is the 1, one TSV13 fault-free that the first delay buffer 1 exports n3, and the output node n7 of the first tristate buffer is 1 for drawing high, and ensureing that the first NAND gate 5 exports n5 is the 1, the first tristate buffer 3 conducting, channel transfer 1;
In the time of delay of the second delay buffer 2
t bufferin, it is that to export n6 be the 1, second tristate buffer 4 conducting to the 0, second NAND gate 6 that the second delay buffer 2 exports n4, draws high the voltage of its output node n8.Through the time of delay of the second delay buffer 2
t bufferafter, it is that the 1, two TSV14 leakage failure occurs, in the time of delay of the second delay buffer 2 that the second delay buffer 2 exports n4
t bufferin, it is that to export n6 be the 0, second tristate buffer 4 high-impedance state to the 1, second NAND gate 6 that the output node n8 of the second tristate buffer 4 fails to be drawn high due to the existence of leakage current, and the second triple gate output node n8 latches 0, closes the leakage current of the 2nd TSV15.At this moment signal 1 is transmitted by a TSV13.
Subsequently, node i n=0, postpones inverter 1 time of delay first
t bufferin, be 1 at the first output n7 postponing inverter 1.One TSV (13) fault-free, the output n7 of the first tristate buffer 3 is still that to export n5 be that the 1, first tristate buffer 3 continues conducting to the 1, first NAND gate 5, and passage 1 transmits 0; Through the time of delay of the first delay buffer 3
t bufferafter, it is the 0, first tristate buffer 3 conducting that the first NAND gate 5 exports n5, channel transfer 0.The time of delay of inverter 2 is postponed second
t bufferin, it is 1 that the second delay inverter 2 exports n4.There is leakage failure in the 2nd TSV14, the output n8 of the second tristate buffer 4 is that to export n6 be that the 0, second tristate buffer 4 continues cut-off to the 0, second NAND gate 6, the 2nd TSV14 transmission 0; Through the time of delay of the second delay buffer 2
t bufferafter, it is the 0, first tristate buffer 3 conducting that the second NAND gate 6 exports n6, TSV13 transmission 0.Fault TSV transmits 0 signal can not produce leakage current.Its Signal transmissions truth table as shown in Figure 3.
the principle of filter resistor open fault of the present invention is as follows:
Assuming that there is resistive-open fault in a TSV13.When not adding of short duration discharging structure, a TSV13 exports n1, the 2nd TSV14 exports n2 or door 15 exports out oscillogram, as shown in Figure 4.Or door 15 rise edge delay that exports out and the 2nd TSV14 to export n2 identical, do not export the impact of n1 by a TSV13, and trailing edge postpones to export n1 trailing edge with a TSV13 and is consistent, and postpones increase.Of short duration discharging structure can when the trailing edge of the 2nd TSV14 signal, produces a width and equals the second delay inverter 10 and postpone t
delayelectric discharge positive pulse, help a TSV13 capacitor discharge, thus avoid a TSV13 trailing edge to postpone to become large.2nd TSV14 exports n2, second to postpone inverter 10 and exports the waveform that n9 and the second NOR gate 8 export n10, as shown in Figure 5.1) when the 2nd TSV14 output n2 is 1, postpone
t delayin, second postpones inverter 10, and to export n9 be that to export n10 be 0 to the 1, second NOR gate 8; Postpone
t delayafter end, second postpones inverter 10, and to export n9 be that to export n10 be 0 to the 0, second NOR gate 8.2) when the 2nd TSV14 output n2 is 0, postpone
t delayin, second postpones inverter 10, and to export n9 be that to export n10 be 1 to the 0, second NOR gate 8, opens the second NMOS tube 12 to a TSV13 capacitor discharge; Postpone
t delayafter end, second postpones inverter 10, and to export n9 be that to export n10 be 0 to the 1, second NOR gate 8.In like manner, the one TSV13 export n1 signal trailing edge time also can at trailing edge time produce one section of discharge signal, now the 2nd TSV14 transmits 0, can not affect Output rusults.
Key point of the present invention is, first a kind of channel structure of symmetry is adopted to carry out fault-tolerant to TSV, improve the yield of three dimensional integrated circuits, utilize the leakage current closing structure of design to close leakage path, the logic state simultaneously keeping leakage failure passage is 0; The of short duration discharging structure of design is utilized to shield the impact of TSV leakage failure on structure output.Circuit structure is simple, does not need test and circuit reconfiguration, does not also need the normal work of interrupt circuit when carrying out fault-tolerant to TSV, can support that TSV's is fault-tolerant online simultaneously.
Claims (4)
1. two silicon through hole is online from a fault-tolerant architecture, it is characterized in that, comprises leakage current closing structure, of short duration discharging structure, TSV or door (15), node i n and exports out; Described leakage current closing structure includes the first delay buffer (1), second successively and postpones inverter (2), the first tristate buffer (3), the second tristate buffer (4), the first NAND gate (5) and the second NAND gate (6); Of short duration discharging structure includes the first NOR gate (7) successively, the second NOR gate (8), first postpones inverter (9), second and postpones inverter (10), the first NMOS tube (11) and the second NMOS tube (12); TSV includes a TSV (13) and the 2nd TSV (14) successively; Described node i n is the input of the first delay buffer (1), the second delay buffer (2), the first tristate buffer (3), the second tristate buffer (4); The output (n3) of the first delay buffer (1) is connected with the first NAND gate (5) input a, the output (n7) of the first tristate buffer (3) is connected through the input b of inverter with the first NAND gate (5), and the first NAND gate (5) output (n5) is connected with the control end of the first tristate buffer (3); Second output (n4) postponing inverter (2) is connected with the input a of the second NAND gate (6), the output (n8) of the second tristate buffer (4) is connected through the input b of inverter with the second NAND gate (6), and the output (n6) of the second NAND gate (6) is connected with the control end of the second tristate buffer (4); The input (n7) of the one TSV (13) is connected with the output of the first tristate buffer (3), and the input (n8) of the 2nd TSV (14) is connected with the second tristate buffer (4) output; The input a of the output (n1) respectively with the first NOR gate (7) of the one TSV (13), the input of the first delay inverter (9), the drain electrode of the second NMOS tube (12) or the input a of door (15) are connected; The input b of the output (n2) respectively with the second NOR gate (8) of the 2nd TSV (14), the input of the second delay inverter (10), the drain electrode of the first NMOS tube (11) or the input b of door (15) are connected; The output (n12) of the first NOR gate (7) is connected with the grid of the first NMOS tube (11), and the output (n10) of the second NOR gate (8) is connected with the grid of the second NMOS tube (12); First postpones inverter (9) output (n11) is connected with the input b of the first NOR gate (7), and the second output (n9) postponing inverter (10) is connected with the input a of the second NOR gate (8); The source class ground connection of the first NMOS tube (11) and the second NMOS tube (12); Or door (15) output is this structure output out.
2. the two silicon through hole of one according to claim 1 is online from fault-tolerant architecture, it is characterized in that, described the first delay buffer (1) is equal with the delay of the second delay buffer (2), slightly larger than signal from node i n to a TSV (13) with the rise edge delay of the 2nd TSV (14) input.
3. the two silicon through hole of one according to claim 1 is online from fault-tolerant architecture, it is characterized in that, described first postpone inverter (9) and second postpone inverter (10) delay equal, slightly larger than signal from node i n to a TSV (13) and the 2nd TSV (14) output trailing edge delay.
4. the two silicon through hole of one according to claim 1 is online from fault-tolerant architecture, and it is characterized in that, a described TSV (13) is identical with the electric parameter of the 2nd TSV (14).
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105405785A (en) * | 2015-11-05 | 2016-03-16 | 合肥工业大学 | Pre-bond through-silicon via test structure based on arbiter |
| CN110223965A (en) * | 2019-06-06 | 2019-09-10 | 安徽工程大学 | One kind is clustered failure tolerant structure based on cellular TSV |
| CN112951176A (en) * | 2021-04-20 | 2021-06-11 | 合肥京东方显示技术有限公司 | Data sampler, drive circuit, display panel and display device |
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| KR930007646B1 (en) * | 1990-09-18 | 1993-08-14 | 삼성전자 주식회사 | Mono multibibrator ic with capacitor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105405785A (en) * | 2015-11-05 | 2016-03-16 | 合肥工业大学 | Pre-bond through-silicon via test structure based on arbiter |
| CN105405785B (en) * | 2015-11-05 | 2020-12-25 | 合肥工业大学 | Silicon through hole test structure before binding based on arbiter |
| CN110223965A (en) * | 2019-06-06 | 2019-09-10 | 安徽工程大学 | One kind is clustered failure tolerant structure based on cellular TSV |
| CN112951176A (en) * | 2021-04-20 | 2021-06-11 | 合肥京东方显示技术有限公司 | Data sampler, drive circuit, display panel and display device |
| CN112951176B (en) * | 2021-04-20 | 2022-09-06 | 合肥京东方显示技术有限公司 | Data sampler, drive circuit, display panel and display device |
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Application publication date: 20150923 |
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