CN201956999U - Clock network of three-dimensional (3D) domino integrated circuit - Google Patents
Clock network of three-dimensional (3D) domino integrated circuit Download PDFInfo
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- CN201956999U CN201956999U CN2010205743008U CN201020574300U CN201956999U CN 201956999 U CN201956999 U CN 201956999U CN 2010205743008 U CN2010205743008 U CN 2010205743008U CN 201020574300 U CN201020574300 U CN 201020574300U CN 201956999 U CN201956999 U CN 201956999U
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Abstract
The utility model relates to a clock network of a three-dimensional (3D) domino integrated circuit, belonging to the application field of integrated circuits. The block network of the 3D domino integrated circuit comprises input signal ends, output signal ends, clock signal ends, pre-charging tubes, holding tubes, clock tubes, output static inverters and pull-down networks. The substrates of all P-channel metal-oxide semiconductor (PMOS) tubes are connected with power supply voltage. The substrates of all N-channel metal-oxide semiconductor (NMOS) tubes are connected with grounding voltage. The clock signal end of a standard domino circuit is connected with the clock network of the 3D domino integrated circuit. One end of a through-silicon-via which is used as a delay unit is connected with the clock end of a previous-stage domino circuit, the other end of the through-silicon-via is connected with the clock end of a next-stage domino circuit, and the clocks of multiple-stage domino circuits are interconnected together through the through-silicon-vias. Since the delay of the through-silicon-via is used as the delay unit in the clock network of the domino circuit, the clock network of the 3D domino integrated circuit has the advantages that a delay clock technology is realized, layout area is saved, the power consumption of the circuit is reduced, the performance of the circuit is improved and a constraint is turned into an effective use.
Description
Technical field
The utility model relates to a kind of clock network, is a kind of domino circuit clock network based on 3D structure integrated circuit specifically, belongs to the integrated circuit application.
Background technology
The good characteristic that domino circuit is fast with its speed, area is little is widely used in the critical path part and memory of processor, is the dynamic logic circuit of the main flow of high-performance processor and memory.The domino circuit of standard is an important branch of cmos circuit, and it is that the static inverter of output constitutes on the dynamic logic piece string that is made of one group of NMOS pipe, as shown in Figure 1.The operation principle of circuit is as follows: when clock signal CLK=0, be the preliminary filling stage of circuit, this moment, preliminary filling PMOS pipe P1 was in conducting state, dynamic node by preliminary filling to high level V
Dd, the static inverter of the output that is connected in series with it is output as low level; When CLK=1, evaluate phase for circuit, at this moment P1 ends, the input signal that dynamic node is looked NMOS pulldown network (PDN) discharges conditionally: if there is the DC channel from the dynamic node to ground in NMOS pipe logical block, dynamic node is discharged to low level over the ground so, and output rises to high level; Otherwise dynamic node will keep high value V by means of holding tube P2
Dd, up to following one-period.
In the domino circuit design, domino doors at different levels exist and postpone, and in order to guarantee the correctness of logic, use rearmounted clock technology usually, make the preliminary filling and the evaluation clock of domino circuit by the rearmounted clock trees of using self-timing.Rearmounted clock is always set up the back in the data input of domino door and is arrived, thereby has guaranteed the correctness of logic.Rearmounted clock domino circuit not only can provide the output signal of paraphase and noninvert, and rearmounted clock can reduce power consumption and noise at preliminary filling stage domino circuit.
As shown in Figure 2, each rearmounted clock domino door comprises a domino unit and a delay cell in the domino circuit.The delay cell of clock has determined the cut-in time of next door, and like this, the time of delay of delay cell is always greater than the poorest time of delay of domino door.Each grade goalkeeper adopts clock signal separately in the rearmounted clock domino circuit.These clock signals will be propagated as ripple in module together along with data computation.Like this, the clock of half is used for domino door preliminary filling, and second half clock is used for the evaluation of door.Therefore, delay cell is always in critical path, and it has stoped by the input signal of non-unidirectional saltus step and changes the disturbance of caused data in domino door evaluate phase.
Four parts that corresponding domino circuit has been mated in the delay of delay cell postpone: the fan-out load delay and the surplus of the inherent delay of door, the wire delay of output node, door.Wherein inherent delay is the delay during the poorest pulldown network evaluation of respective doors, the introducing of surplus is used to mate between settling time of place door and delay cell and the next stage door difference of aborning technology, voltage and temperature, and because the difference of the delay of output line, fan-out load and the parasitogenic signal that is coupled.
So the clock network of traditional domino circuit, owing to used rearmounted clock technology, thus introduced extra delay cell, increased the complexity of circuit design, and delay cell itself has increased chip area, has consumed extra power consumption, has influenced the combination property of domino circuit.
The 3D integrated circuit, the structure that adopts active layer (device layer) to superpose one by one, promptly make full use of the space of integrated circuit, it is developed to the direction of 3D, reduce chip area, improved chip integration, improved the performance of deep submicron integrated circuit, satisfied the integrated circuit low cost, high performance development trend.
As shown in Figure 3, the 3D integrated circuit is realized by the silicon via process, and the silicon through hole not only needs to penetrate the various materials of forming the lamination circuit, also needs to penetrate very thick silicon substrate.The silicon through hole is by between chip and chip as encapsulation technology of new generation, makes vertical conducting between wafer and the wafer, realizes the state-of-the-art technology that interconnects between the chip.
But, because the silicon through hole is generally metallic copper, it must pass active layer (device layer) and thicker substrate in the application, must bring certain signal transmission delay, especially in some high-frequency circuit, this delay meeting produces greatly influence to circuit performance, and this also becomes one of restraining factors of 3D integrated circuit extensive use.
Summary of the invention
The purpose of this utility model is to utilize in the 3D integrated circuit, the delay of silicon through hole is as the delay cell in the domino circuit clock network, realize back time-delay clock technology, the restraining factors during the 3D integrated circuit is used have been overcome, and saved chip area, lower the power consumption of circuit, improved the performance of circuit.
The domino circuit of standard comprises the input signal end, output signal end, and clock signal terminal, the preliminary filling pipe, holding tube, the clock pipe is exported static inverter and pulldown network.In the domino circuit, the substrate of all PMOS pipes connects supply voltage, the substrate earthed voltage of all NMOS pipes.
The clock signal terminal of standard domino circuit links to each other with the clock network of 3D domino integrated circuit, one end of silicon through hole connects the clock end of the domino circuit of upper level, the other end of silicon through hole connects the clock end of the domino circuit of next stage, silicon through hole itself has been realized back time-delay clock technology as delay cell.So clock end cascade each grade of domino circuit together is certain for different wafer layers, clock is interconnected at together by the silicon through hole.
In addition, in the clock network of above-mentioned 3D domino integrated circuit, indivedual nodes can add driver, to increase the driving force of clock network, like this clock signal when propagating also by shaping, this makes clock waveform can not decay in any logic, thereby has guaranteed correct operation, but this can increase the power consumption and the chip area of circuit.
In the above-mentioned 3D domino integrated circuit, the pulldown network of each domino circuit unit can be any gate, as: or door, with door, same or door or XOR gate.
Above-mentioned 3D domino integrated circuit, each domino circuit unit can be economized and remove the clock pipe, i.e. the direct ground connection of pulldown network.
Compare with traditional domino circuit clock network, the utility model can be obtained following beneficial effect:
The one, the sharp Technology Need of the back time-delay clock of traditional domino circuit adds delay cell, the clock network of 3D domino integrated circuit, with the delay of silicon through hole as the delay cell in the domino circuit clock network, realize back time-delay clock technology, saved chip area, lower the power consumption of circuit, improved the performance of circuit.
The 2nd, the silicon through hole of 3D integrated circuit can must bring certain signal transmission delay and deviation, especially in some high-frequency circuit, this delay meeting produces greatly influence to circuit performance, the clock network of 3D domino integrated circuit, effectively utilized this delay, the change restraining factors are effective use.
Description of drawings:
The domino circuit schematic diagram of Fig. 1 standard;
Fig. 2 utilizes the domino circuit schematic diagram of rearmounted clock technology;
Figure 33 D domino integrated circuit clock network diagram.
Embodiment
Be further described for the utility model below in conjunction with drawings and Examples.
Present embodiment is the clock network of multistage domino or door.
Be illustrated in figure 3 as 3D domino integrated circuit clock network, it is made up of several parts:
The domino of standard or door comprise the input signal end, output signal end, and clock signal terminal, the preliminary filling pipe, holding tube, the clock pipe is exported static inverter and pulldown network.In the domino circuit, the substrate of all PMOS pipes connects supply voltage, the substrate earthed voltage of all NMOS pipes.
The clock signal terminal of standard domino circuit links to each other with the clock network of 3D domino integrated circuit: an end of silicon through hole 1 is connected the clock end of domino circuit 1, and the other end of silicon through hole 1 connects the clock end of domino circuit 2; One end of silicon through hole 2 connects the clock end of domino circuit 2, and the other end of silicon through hole 2 connects the clock end of domino circuit 3.Silicon through hole itself has been realized back time-delay clock technology as delay cell.So clock end cascade each grade of domino circuit together is certain for different wafer layers, clock is interconnected at together by the silicon through hole.
In addition, in the clock network of above-mentioned 3D domino integrated circuit, indivedual nodes can add driver, to increase the driving force of clock network, like this clock signal when propagating also by shaping, this makes clock waveform can not decay in any logic, thereby has guaranteed correct operation, but this can increase the power consumption and the chip area of circuit.
In the above-mentioned 3D domino integrated circuit, the pulldown network of each domino circuit unit can be any gate, as: or door, with door, same or door or XOR gate.
Above-mentioned 3D domino integrated circuit, each domino circuit unit can be economized and remove the clock pipe, i.e. the direct ground connection of pulldown network.
Claims (4)
1.3D domino integrated circuit clock network, comprise the input signal end, output signal end, clock signal terminal, the preliminary filling pipe, holding tube, the clock pipe, export static inverter and pulldown network, the substrate of all PMOS pipes connects supply voltage, the substrate earthed voltage of all NMOS pipes, it is characterized in that: the clock signal terminal of standard domino circuit links to each other with the clock network of 3D domino integrated circuit, connect the clock end of the domino circuit of upper level as an end of the silicon through hole of delay cell, the other end of silicon through hole connects the clock end of the domino circuit of next stage, and the clock of multistage domino circuit is interconnected at together by the silicon through hole.
2. the clock network of 3D domino integrated circuit according to claim 1 is characterized in that: in the clock network of 3D domino integrated circuit, the node place that the clock end of silicon through hole and domino circuit links to each other can add driver.
3. the clock network of 3D domino integrated circuit according to claim 1 is characterized in that: the pulldown network of each domino circuit unit can be: or door, with door, same or door or XOR gate.
4. the clock network of 3D domino integrated circuit according to claim 1 is characterized in that: each domino circuit unit can be economized and remove the clock pipe, i.e. the direct ground connection of pulldown network.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205743008U CN201956999U (en) | 2010-10-15 | 2010-10-15 | Clock network of three-dimensional (3D) domino integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205743008U CN201956999U (en) | 2010-10-15 | 2010-10-15 | Clock network of three-dimensional (3D) domino integrated circuit |
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| Publication Number | Publication Date |
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| CN201956999U true CN201956999U (en) | 2011-08-31 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2010205743008U Expired - Fee Related CN201956999U (en) | 2010-10-15 | 2010-10-15 | Clock network of three-dimensional (3D) domino integrated circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103873043A (en) * | 2014-03-14 | 2014-06-18 | 北京工业大学 | High-performance domino circuit design based on clock extraction bias voltage technology |
| CN104937596A (en) * | 2012-11-28 | 2015-09-23 | 高通股份有限公司 | Clock distribution network for 3D integrated circuit |
| CN109379062A (en) * | 2018-09-18 | 2019-02-22 | 宁波大学 | A kind of on piece delay unit circuit based on coaxial through-silicon via |
-
2010
- 2010-10-15 CN CN2010205743008U patent/CN201956999U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104937596A (en) * | 2012-11-28 | 2015-09-23 | 高通股份有限公司 | Clock distribution network for 3D integrated circuit |
| CN103873043A (en) * | 2014-03-14 | 2014-06-18 | 北京工业大学 | High-performance domino circuit design based on clock extraction bias voltage technology |
| CN103873043B (en) * | 2014-03-14 | 2017-07-14 | 北京工业大学 | The high-performance domino circuit design of bias techniques is extracted based on clock |
| CN109379062A (en) * | 2018-09-18 | 2019-02-22 | 宁波大学 | A kind of on piece delay unit circuit based on coaxial through-silicon via |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110831 Termination date: 20141015 |
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| EXPY | Termination of patent right or utility model |