CN204946895U - A kind of encapsulating structure of multi-chip - Google Patents
A kind of encapsulating structure of multi-chip Download PDFInfo
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- CN204946895U CN204946895U CN201520605869.9U CN201520605869U CN204946895U CN 204946895 U CN204946895 U CN 204946895U CN 201520605869 U CN201520605869 U CN 201520605869U CN 204946895 U CN204946895 U CN 204946895U
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- encapsulating structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Wire Bonding (AREA)
Abstract
The utility model provides a kind of encapsulating structure of multi-chip, and it comprises substrate, the first chip and chipset; Substrate has upper surface, lower surface and the first through hole; First chip has first surface and first back side, the upper surface of first surface and substrate is connected, be provided with multiple first bonding point in the middle part of first surface, the first bonding point passes through the lower surface of the first wire bonding to substrate, and the first wire is through the first through hole; Chipset comprises at least one functional chip, functional chip and upper surface of base plate bonding.The encapsulating structure of the utility model multi-chip can use the dynamic random storage chip of standard, omits the operation of chip being carried out to secondary wiring processing, facilitating chip manufacturing process, reduces the manufacturing cost of chip; Chip by existing opposition both sides bonding wire, is optimized for intermediate backsheet bonding wire in encapsulating structure, reduces the horizontal base plate size that chip takies, makes package module more miniaturized.
Description
Technical field
The utility model relates to technical field of semiconductor device, particularly relates to a kind of encapsulating structure of multi-chip.
Background technology
Thin, little, the lightness trend of consumer electronics, more and more higher to the requirement of the miniaturization of multi-chip package device, and along with the diversified development of electronic product function, the integrated more functional requirement of packaging system is also strengthened day by day.EMCP (embedmultichippackage) is the encapsulation of embedded type multi-core sheet, it has built-in NANDFlash and controls wafer, the burden of master wafer computing can be reduced, and have more jumbo fast flash memory bank, stacked structures can make the external form thickness of integral device thinner, this kind of encapsulating structure mostly is chip and is superimposed, and object is reduce overall package area, is thus widely used in the product of the demand thin encapsulations such as mobile phone, flat board, learning machine.
As shown in Figure 1, common EMCP comprises substrate 10, the dynamic random storage chip 30 of low-power consumption, flash memory storage chip 50 and controls the control chip 70 of flash memory, is coated with plastic packaging material 80 above stacking chip.Wherein, dynamic random access memory chip is the both sides bonding wire (as shown in Figure 2) of opposition, and flash chip is one-sided bonding wire (as shown in Figure 3), and controller is adjacent both sides or three side bonding wires (as shown in Figure 4).But, as shown in Figure 5, the dynamic random storage chip 300 of industry internal standard layout format is middle part wire bond 330 being placed on chip when chip manufacturing, but not the side of chip, the capacity of large chip can be added thus and reduce the size of single dynamic random storage chip encapsulation.
Wire bond be placed on chip middle part be unfavorable for multi-chip superposition and superposition time wire bonding because bonding point in the chips between position will bring upper strata chip line ball or bonding line long, be unfavorable for packaging technology realize and management and control.In prior art, the dynamic random storage chip folding chip package for EMCP needs again to do wire bond to distribute, the bonding point of centre is distributed to the side of two opposition of chip by the mode that lead-in wire connects, also need thus again to do to the bonding point of chip processing of once connecting up after chip manufacturing completes, make the chip that wire bond is distributed in side, the packaging technology manufacture of folded chip could be met like this.Bring thus and cannot use original chip, and again need carry out processing and manufacturing to chip, be just used in EMCP.Such supply chain is unfavorable for the standardization application of chip, is unfavorable for the supply of material of chip, and the waste of the time of causing chip again to process and cost, affects the market periods of encapsulating products.
Utility model content
The technical problem that the utility model solves be to provide a kind of can facilitating chip manufacturing process, reduce chip size and the multichip packaging structure that can reduce costs.
The utility model solves the problems of the technologies described above adopted technical scheme:
The utility model provides a kind of encapsulating structure of multi-chip, and it comprises: stack gradually the substrate of setting, the first chip and chipset; Described substrate has the first through hole of upper surface, the lower surface relative with upper surface and through upper surface and lower surface, and it is for carries chips and realize the electrical connection of chip chamber; Described first chip has first surface and first back side relative with described first surface, the upper surface of described first back side and described substrate is connected, multiple first bonding point is provided with in the middle part at described first back side, described first bonding point passes through the lower surface of the first wire bonding to described substrate, and described first wire is through described first through hole; Described chipset is placed in above described first chip, and it comprises at least one functional chip, described functional chip and described upper surface of base plate bonding.
As the further improvement of technique scheme, described chipset comprises the second chip be located at above described first chip, described second chip has second surface and second back side relative with described second surface, described second surface and described first surface are connected, described second back side is provided with multiple second bonding point, and described second bonding point passes through the upper surface of the second wire bonding to described substrate.
As the further improvement of technique scheme, described chipset also comprises the 3rd chip be located at above described second chip, described 3rd chip has the 3rd surface and three back side relative with described 3rd surface, described 3rd surface is connected with described second back side, described 3rd back side is provided with multiple 3rd bonding point, and described 3rd bonding point is bonded to the upper surface of described substrate by privates.
As the further improvement of technique scheme, between described first back side and the upper surface of substrate, between described second surface and first surface, between described 3rd surface and second back side, be all provided with the bonding glued membrane acted on that is connected.
As the further improvement of technique scheme, described first chip is standard dynamic random storage chip, and described second chip is flash chip, and described 3rd chip is control chip.
As the further improvement of technique scheme, the perforated area of described first through hole is greater than the area shared by multiple first bonding points of the first chip.
As the further improvement of technique scheme, the upper and lower surface of described substrate is all coated with plastic packaging material, an overall formation package module.
As the further improvement of technique scheme, the lower surface of described substrate is provided with the soldered ball for the connection of package module external electrical and mechanical support.
As the further improvement of technique scheme, the height of described soldered ball is greater than the height of the plastic packaging material of base lower surface.
The beneficial effects of the utility model are:
The encapsulating structure of the utility model multi-chip can use the dynamic random storage chip of standard, omits the operation of chip being carried out to secondary wiring processing, facilitating chip manufacturing process, reduces the manufacturing cost of chip; Chip by existing opposition both sides bonding wire, is optimized for intermediate backsheet bonding wire in encapsulating structure, reduces the horizontal base plate size that chip takies, makes package module more miniaturized.
Accompanying drawing explanation
Fig. 1 is the structural representation of the encapsulating structure of the EMCP of prior art;
Fig. 2 is the bonding point layout structure schematic diagram of the dynamic random storage chip of the encapsulating structure of the EMCP of prior art;
Fig. 3 is the bonding point layout structure schematic diagram of the flash chip of the encapsulating structure of the EMCP of prior art;
Fig. 4 is the bonding point layout structure schematic diagram of the control chip of the encapsulating structure of the EMCP of prior art;
Fig. 5 is the bonding point layout structure schematic diagram of the standard dynamic random storage chip of the utility model multichip packaging structure;
Fig. 6 is the overall structure schematic diagram of the utility model multichip packaging structure;
Fig. 7 is the fractionation structural representation of the utility model multichip packaging structure.
Embodiment
Be clearly and completely described below with reference to embodiment and the accompanying drawing technique effect to design of the present utility model, concrete structure and generation, to understand the purpose of this utility model, characteristic sum effect fully.Obviously; described embodiment is a part of embodiment of the present utility model, instead of whole embodiment, based on embodiment of the present utility model; other embodiments that those skilled in the art obtains under the prerequisite not paying creative work, all belong to the scope of the utility model protection.In addition, all connection/annexations related in patent, not singly refer to that component directly connects, and refer to and according to concrete performance, can connect auxiliary by adding or reducing, and form more excellent draw bail.Each technical characteristic in the utility model, can combination of interactions under the prerequisite of not conflicting conflict.
Please refer to Fig. 6 and Fig. 7, the encapsulating structure of the utility model multi-chip comprises the substrate 100, first chip 300 and the chipset that stack gradually from bottom to up.
Described substrate 100 is for carries chips and realize the electrical connection of chip chamber, can be organic support plate, inorganic support plate or metal support plate, it has the first through hole 130 of upper surface 110, the lower surface 120 relative with upper surface 110 and through upper surface 110 and lower surface 120.
First chip 300 has first surface 310 and first back side 320 relative with described first surface 310, described first back side 320 is connected with the upper surface 110 of described substrate 100, in the middle part at described first back side 320, there is multiple first bonding point 330, described first bonding point 330 is bonded to the lower surface 120 of described substrate 100 by the first wire 340, described first wire 340 is through described first through hole 130.In order to make the first wire 340 swimmingly through the first through hole 130, in the present embodiment, the perforated area of the first through hole 130 is greater than the area shared by multiple first bonding points 330 of the first chip 300.In this preferred embodiment, first chip 300 is located at the standard dynamic random storage chip of middle part for bonding point, this chip does not need the side of two opposition bonding point of centre being distributed to chip by the mode that lead-in wire connects, and directly uses standard chips.
Described chipset is placed in above described first chip 300, and it comprises at least one functional chip, and described functional chip and described substrate 100 upper surface 110 bonding, it comprises the second chip 500 and the 3rd chip 700.In certain embodiments, the second chip 500 and the 3rd chip 700 can be semiconductor chip, wafer etc.As in the present embodiment, the second chip 500 is flash chip, and the 3rd chip 700 is control chip.Second chip 500 is relative to each other stacking with described first chip 300, and the 3rd chip 700 is stacked in above described second chip 500 further.Certainly, the quantity of the functional chip that described chipset comprises is not limited to two, and it can set flexibly according to the requirement of chip package.
Second chip 500 has second surface 510 and second back side 520 relative with described second surface 510, described second surface 510 is connected with described first surface 310, described second back side 520 is provided with multiple second bonding point 530, and described second bonding point 530 is bonded to the upper surface 110 of described substrate 100 by the second wire 540.
3rd chip 700 has the 3rd surface 710 and three back side 720 relative with described 3rd surface 710, described 3rd surface 710 is connected with described second back side 520, described 3rd back side 720 is provided with multiple 3rd bonding point 730, and described 3rd bonding point 730 is bonded to the upper surface 110 of described substrate 100 by privates 740.
In this preferred embodiment, between described first back side 320 and the upper surface 110 of substrate 100, between described second surface 510 and first surface 310, between described 3rd surface 710 and second back side 520, be all provided with the bonding glued membrane (not shown) acted on that is connected.The bonding line of the chip that the bonding line of described substrate 100 lower surface 120, described substrate 100 upper surface 110 are stacking and substrate 100 upper surface 110 is all coated with plastic packaging material 800, an overall formation package module.The lower surface 120 of described substrate 100 is provided with the soldered ball 140 for the connection of package module external electrical and mechanical support, and the height of described soldered ball 140 is greater than the height that substrate 100 lower surface 120 encapsulates the plastic packaging material 800 of bonding line.
More than that better enforcement of the present utility model is illustrated, but the utility model is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite without prejudice to the utility model spirit, and these equivalent distortion or replacement are all included in the application's claim limited range.
Claims (9)
1. an encapsulating structure for multi-chip, is characterized in that, comprising: stack gradually the substrate of setting, the first chip and chipset;
Described substrate has the first through hole of upper surface, the lower surface relative with upper surface and through upper surface and lower surface, and it is for carries chips and realize the electrical connection of chip chamber;
Described first chip has first surface and first back side relative with described first surface, the upper surface of described first back side and described substrate is connected, multiple first bonding point is provided with in the middle part at described first back side, described first bonding point passes through the lower surface of the first wire bonding to described substrate, and described first wire is through described first through hole;
Described chipset is placed in above described first chip, and it comprises at least one functional chip, described functional chip and described upper surface of base plate bonding.
2. the encapsulating structure of multi-chip as claimed in claim 1, it is characterized in that: described chipset comprises the second chip be located at above described first chip, described second chip has second surface and second back side relative with described second surface, described second surface and described first surface are connected, described second back side is provided with multiple second bonding point, and described second bonding point passes through the upper surface of the second wire bonding to described substrate.
3. the encapsulating structure of multi-chip as claimed in claim 2, it is characterized in that: described chipset also comprises the 3rd chip be located at above described second chip, described 3rd chip has the 3rd surface and three back side relative with described 3rd surface, described 3rd surface is connected with described second back side, described 3rd back side is provided with multiple 3rd bonding point, and described 3rd bonding point is bonded to the upper surface of described substrate by privates.
4. the encapsulating structure of multi-chip as claimed in claim 3, is characterized in that: be all provided with the bonding glued membrane acted on that is connected between described first back side and the upper surface of substrate, between described second surface and first surface, between described 3rd surface and second back side.
5. the encapsulating structure of multi-chip as claimed in claim 4, it is characterized in that: described first chip is standard dynamic random storage chip, and described second chip is flash chip, described 3rd chip is control chip.
6. the encapsulating structure of the multi-chip as described in any one of claim 1 to 5, is characterized in that: the perforated area of described first through hole is greater than the area shared by multiple first bonding points of the first chip.
7. the encapsulating structure of the multi-chip as described in any one of claim 1 to 5, is characterized in that: the upper and lower surface of described substrate is all coated with plastic packaging material, an overall formation package module.
8. the encapsulating structure of multi-chip as claimed in claim 7, is characterized in that: the lower surface of described substrate is provided with the soldered ball for the connection of package module external electrical and mechanical support.
9. the encapsulating structure of multi-chip as claimed in claim 8, is characterized in that: the height of described soldered ball is greater than the height of the plastic packaging material of base lower surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520605869.9U CN204946895U (en) | 2015-08-12 | 2015-08-12 | A kind of encapsulating structure of multi-chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520605869.9U CN204946895U (en) | 2015-08-12 | 2015-08-12 | A kind of encapsulating structure of multi-chip |
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| CN204946895U true CN204946895U (en) | 2016-01-06 |
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| CN201520605869.9U Active CN204946895U (en) | 2015-08-12 | 2015-08-12 | A kind of encapsulating structure of multi-chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018120060A1 (en) * | 2016-12-30 | 2018-07-05 | Intel Corporation | Interposer design in package structures for wire bonding applications |
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2015
- 2015-08-12 CN CN201520605869.9U patent/CN204946895U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018120060A1 (en) * | 2016-12-30 | 2018-07-05 | Intel Corporation | Interposer design in package structures for wire bonding applications |
| US10971478B2 (en) | 2016-12-30 | 2021-04-06 | Intel Corporation | Interposer design in package structures for wire bonding applications |
| US11652087B2 (en) | 2016-12-30 | 2023-05-16 | Tahoe Research, Ltd. | Interposer design in package structures for wire bonding applications |
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