CN204856471U - Simple 8639PCIE test fixture - Google Patents
Simple 8639PCIE test fixture Download PDFInfo
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- CN204856471U CN204856471U CN201520578207.7U CN201520578207U CN204856471U CN 204856471 U CN204856471 U CN 204856471U CN 201520578207 U CN201520578207 U CN 201520578207U CN 204856471 U CN204856471 U CN 204856471U
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- 8639pcie
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- 238000012360 testing method Methods 0.000 title abstract description 6
- 238000005259 measurement Methods 0.000 claims abstract description 17
- 238000011161 development Methods 0.000 abstract description 7
- 230000005540 biological transmission Effects 0.000 description 4
- 235000008429 bread Nutrition 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000004083 survival effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- Testing Electric Properties And Detecting Electric Faults (AREA)
Abstract
The utility model provides a simple and easy 8639PCIE test fixture, including the double-deck PCB board of upper and lower layering, wherein upper PCB board is the signal layer, and lower floor's PCB board is the GND layer, has seted up fixed orifices and signal mouth on the signal layer, and this fixed orifices and signal mouth install PCIESSD interface and SMA interface respectively, this PCIESSD interface wiring connection SMA interface. Compared with the prior art, the simple 8639PCIE test fixture can realize 8639 PCIESSD? The interface is connected with the test equipment, so that measurement of PCIE signals is realized, and PCIE is ensured? The reliability of the hard disk connection provides a powerful technical guarantee for the research, development and debugging of the PCIESSD; the practicability is strong, the application range is wide, and the popularization is easy.
Description
Technical field
The utility model relates to computer hardware equipment technical field of measurement and test, specifically simple, the easy 8639PCIE measurement jig of a kind of structure.
Background technology
Hard disk is as conventional memory device, development in recent years is not very rapid, but along with the appearance of solid state hard disc, start the development making people joyful, the thing followed has driven the hard-disk interface speed of development, the rule of development of things is exactly that old thing breeds new things in innovation, selects best replacement old thing in the survival of the fittest.
The interface development of hard disk too in this way, needs the development accelerated to adapt to the progress of other products.The interface that current solid state hard disc is applied is mainly based on SAS, SAS bus uses embedded clock signal, possesses stronger error correcting capability, its maximum difference compared with the past is to check transfer instruction (being not only data), if find mistake meeting automatic straightening, something which increases the reliability of data transmission.
Serial line interface also has the advantage that structure is simple, support hot plug.But the transmission speed of hard disk is all limited in 300MB/s(and writes by SAS), 500MB/s(reads) this rank is difficult to again promote, and cannot meet the expectation of consumer to hard disk speed.
And PCIE interface can bring up to a very high frequency data transmission rate, reaches the high bandwidth that SAS can not provide, so SSD walks PCIE interface and has a benefit the most direct, breaks through the transmission speed of current SAS6.0Gbps mono-600MB/s.
Nowadays, adopt the product of PCIESSD to be proposed much, in performance, have the ultimate attainment read-write usefulness surmounting imagination.Chip manufacturer is also doing one's utmost to promote PCIESSD, and following employing PCIESSD has been trend of the times, but industry does not also provide the PCIESSD measurement jig of standard at present.
Based on this, now provide a kind of easy 8639PCIE measurement jig.
Summary of the invention
Technical assignment of the present utility model solves the deficiencies in the prior art, provides the easy 8639PCIE measurement jig that a kind of structure is simple, result of use is desirable.
The technical solution of the utility model realizes in the following manner, a kind of easy 8639PCIE measurement jig, comprise the double-layer PCB board of lower leaf, its at the middle and upper levels pcb board be signals layer, lower floor's pcb board is GND layer, signals layer offers fixed orifice and signal port, and this fixed orifice and signal port install PCIESSD interface and SMA interface respectively, the wiring of this PCIESSD interface connects SMA interface.
Described PCIESSD interface is provided with PCIETX, PCIERX signal pins, and this PCIETX, PCIERX signal pins is connected to SMA interface by differential signal line.
The often group differential signal line that described SMA interface connects includes positive pole and two, negative pole, and the length difference between two differential signal lines is 0 ~ 1mil.
In sum, the beneficial effect that the utility model is compared with prior art produced is:
One of the present utility model easy 8639PCIE measurement jig has the features such as structure is simple, easy to use, novel, the connection of 8639PCIESSD interface and testing apparatus can be realized, thus realize the measurement of PCIE signal, and then guarantee the reliability that PCIE hard disk connects, for the research and development of PCIESSD and debugging provide strong technical guarantee; Practical, applied widely, be easy to promote.
Accompanying drawing explanation
Accompanying drawing 1 is structural representation of the present utility model.
Mark in accompanying drawing represents respectively:
1, pcb board, 1.1, signals layer, 1.2, GND layer, 2, PCIESSD interface, 3, SMA interface, 4, differential signal line.
Embodiment
Below in conjunction with accompanying drawing, the easy 8639PCIE measurement jig of one of the present utility model is described in detail below.
As shown in Figure 1, a kind of easy 8639PCIE measurement jig is now provided, comprise the double-layer PCB board 1 of lower leaf, its at the middle and upper levels pcb board 1 be signals layer 1.1, lower floor's pcb board 1 is GND layer 1.2, signals layer 1.1 offers fixed orifice and signal port, these two perforates do not mark out in the drawings, its position is the lay down location of PCIESSD interface 2 and SMA interface 3, and this fixed orifice and signal port install PCIESSD interface 2 and SMA interface 3 respectively, the wiring of this PCIESSD interface 2 connects SMA interface 3.
Described PCIESSD interface 2 is provided with PCIETX, PCIERX signal pins, and this PCIETX, PCIERX signal pins is connected to SMA interface 3 by differential signal line 4.
The often group differential signal line 4 that described SMA interface 3 connects includes positive pole and two, negative pole, and the length difference between two differential signal lines 4 is 0 ~ 1mil.
When reality uses, directly can be connected on this measurement jig by SMA cable, realize 8639PCIESSD signal and be connected with oscillographic, thus realize the measurement of PCIE signal quality, debugging.
When actual fabrication, complete in the following order:
First the bread board that preparation one is double-deck, i.e. pcb board 1, one deck is as signals layer 1.1, and another layer is GND layer 1.2, as the reference surface of signals layer 1.1.On bread board, reserve PCIESSD interface 2 and the fixed orifice required for SMA interface 3 and signal port;
PCIESSD interface 2 is welded on the fixed orifice of bread board;
Wires design, according to the pin sequence of PCIESSD interface 2, connects the differential signal line 4 of the 100ohm of PCIETX+, TX-, RX+, RX-signal impedance matching, and is connected to P, N end of corresponding SMA interface 3.The Length discrepancy of often couple of differential signal line P, N controls within 1mil;
The SMA interface 3 of standard in signal line terminal welding;
Differentiate for convenience of when measuring, indicate the title of signal wire respectively at board SMA interface 3 place, as TX0+, TX0-, RX0+, RX0-.
Above embodiment is only for illustration of the utility model, and be not limitation of the utility model, the those of ordinary skill of relevant technical field, without departing from the spirit and scope of the present invention, can also make a variety of changes and modification, therefore all equivalent technical schemes also belong to category of the present utility model.
Claims (3)
1. an easy 8639PCIE measurement jig, comprise PCB printed circuit board, it is characterized in that: the double-layer PCB board comprising lower leaf, its at the middle and upper levels pcb board be signals layer, lower floor's pcb board is GND layer, signals layer offers fixed orifice and signal port, and this fixed orifice and signal port install PCIESSD interface and SMA interface respectively, the wiring of this PCIESSD interface connects SMA interface.
2. the easy 8639PCIE measurement jig of one according to claim 1, it is characterized in that: described PCIESSD interface is provided with PCIETX, PCIERX signal pins, and this PCIETX, PCIERX signal pins is connected to SMA interface by differential signal line.
3. the easy 8639PCIE measurement jig of one according to claim 2, is characterized in that: the often group differential signal line that described SMA interface connects includes positive pole and two, negative pole, and the length difference between two differential signal lines is 0 ~ 1mil.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520578207.7U CN204856471U (en) | 2015-08-04 | 2015-08-04 | Simple 8639PCIE test fixture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520578207.7U CN204856471U (en) | 2015-08-04 | 2015-08-04 | Simple 8639PCIE test fixture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204856471U true CN204856471U (en) | 2015-12-09 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520578207.7U Expired - Fee Related CN204856471U (en) | 2015-08-04 | 2015-08-04 | Simple 8639PCIE test fixture |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204856471U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107390065A (en) * | 2017-08-04 | 2017-11-24 | 郑州云海信息技术有限公司 | A kind of PCH method of testings |
-
2015
- 2015-08-04 CN CN201520578207.7U patent/CN204856471U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107390065A (en) * | 2017-08-04 | 2017-11-24 | 郑州云海信息技术有限公司 | A kind of PCH method of testings |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151209 Termination date: 20170804 |