CN204740521U - Quick transient response's no electric capacity type LDO - Google Patents

Abstract

The utility model discloses a quick transient response's no electric capacity type LDO introduces adjustable cascode feedback loop through drain terminal at the LDO the power adjustment pipe and bars end, makes the LDO output constitute an emitter follower who has degree of depth negative feedback, and consequently, LDO has ultralow interchange output impedance at the full load within range, has guaranteed that the output limit is in the high frequency all the time. Even LDO load capacitance and electric current are when changing in a big way, the big electric capacity type LDO of no -output has only a dominant pole within the unity -gain bandwidth, guaranteed system stability, because quick transient response has been realized to no extra building -out capacitor.

Description

A kind of fast transient response without capacitor type LDO

Technical field

The utility model relates to a kind of without capacitor type LDO, belongs to circuit engineering field.

Background technology

LDO (Low Dropout Voltage Regulator: low pressure difference linear voltage regulator) is the simplest linear stabilized power supply, and it has, and volume is little, noise is little, output ripple is low, without electromagnetic interference (EMI) and the advantage such as simplicity of design, peripheral original paper be few.

If the LDO module in VLSI (very large scale integrated circuit) or SoC system, at Embedded bulky capacitor, significantly can increase chip area; If the outer electric capacity of employing sheet, then need the pin increasing chip.So, no matter from application cost, complexity or LDO own reliability, need design a kind of without the need to outside bulky capacitor just can realize self-stabilization without capacitor type LDO.

Compare with traditional LDO, the maximum difference without capacitor type LDO is bulky capacitor circuit structure having lacked output terminal parallel connection.In traditional LDO, the bulky capacitor of this output terminal is an important charge storage and provides device, can effectively reduce the change due to output voltage when load current step changes; The secondary dominant pole that the low frequency simultaneously relying on the resistance in series of this electric capacity and its equivalence to form Left half-plane offsets LDO loop inside zero point realizes the stability of system.And in stability and transient response, there is larger defect without capacitor type LDO, be the difficult point in design.

Realize LDO in full sheet, the technology extensively adopted at present is that the multistage nested type Miller compensation of dependence realizes limit division and zero pole point is offset, but complex structure, and building-out capacitor is larger.

Utility model content

Technical problem to be solved in the utility model is the defect overcoming prior art, provide a kind of fast transient response without capacitor type LDO.

For solving the problems of the technologies described above, the utility model provide a kind of fast transient response without capacitor type LDO, it is characterized in that, introduce adjustable cascade feedback control loop at the drain terminal of power Correctional tube and grid end, make the output voltage of power Correctional tube source form the emitter follower that has profound and negative feedbck.

The variable quantity of output voltage feeds back to the grid end of power Correctional tube after adjustable common source and common grid amplifier is amplified.

Adjustable cascade feedback control loop comprises two adjustable cascode amplifiers.

One of them adjustable cascode amplifier is connected to the drain terminal of power Correctional tube, and this adjustable cascode amplifier comprises transistor seconds, third transistor, the 4th transistor and the 5th transistor; Second current source and the first transistor provide grid bias for transistor seconds; The drain terminal of third transistor is connected to the grid end of power Correctional tube, and the grid end of third transistor is connected to the drain terminal of transistor seconds and the drain terminal of the 4th transistor, the source ground connection of transistor seconds simultaneously; The source of the 4th transistor is connected to power vd D, and the grid end of the 4th transistor is connected to the source of third transistor and the drain terminal of the 5th transistor simultaneously, and the source of the 5th transistor is connected to power vd D.

Wherein another adjustable cascode amplifier is connected to the grid end of power Correctional tube, and this adjustable cascode amplifier comprises the tenth transistor, the 11 transistor, the tenth two-transistor and the 13 transistor; First current source and the 14 transistor provide grid bias for the 13 transistor; The drain terminal of the 13 transistor is connected to the grid end of the 11 transistor and the drain terminal of the tenth two-transistor simultaneously, the source ground connection of the tenth two-transistor; The grid end of the tenth two-transistor is connected to the drain terminal of the source of the 11 transistor, the drain terminal of the 8th transistor and the tenth transistor, the source ground connection of the tenth transistor simultaneously.

The source of power Correctional tube drain terminal and the 8th transistor is connected to output voltage altogether;

The grid end of the 8th transistor and the grid end of the 7th transistor, drain terminal connect altogether; The source of the 8th transistor is connected to adjustable cascade feedback control loop;

The source of the 7th transistor is connected to the output terminal of amplifier, and the positive input of amplifier is reference voltage end, and the reverse input end of amplifier, respectively through the first resistance eutral grounding, is connected to the output terminal of amplifier through the second resistance.

The beneficial effect that the utility model reaches:

The utility model is by introducing adjustable cascade feedback control loop at the drain terminal of LDO power Correctional tube and grid end, LDO output terminal is formed emitter follower that one has profound and negative feedbck, therefore, LDO has ultralow AC output impedance in full-load range, ensure that exporting limit is in high frequency all the time.Even if LDO load capacitance and electric current are when changing in a big way, no-output bulky capacitor type LDO only has a dominant pole within unity gain bandwidth, ensure that system stability; Due to without extra building-out capacitor, achieve transient response fast.

Accompanying drawing explanation

Fig. 1 the utility model LDO;

The load current of Fig. 2 the utility model LDO and the relation (200pF load capacitance) of phase margin;

The load transient response of Fig. 3 the utility model LDO.

Embodiment

Below in conjunction with accompanying drawing, the utility model is further described.Following examples only for clearly the technical solution of the utility model being described, and can not limit protection domain of the present utility model with this.

As shown in Figure 1, fast transient response of the present utility model without capacitor type LDO, introduce adjustable cascade feedback control loop at the drain terminal of power Correctional tube Q6 and grid end, make LDO output voltage OUT (i.e. the drain terminal of power Correctional tube Q6) form the emitter follower that has profound and negative feedbck.

Transistor Q2, Q3, Q4, Q5 form an adjustable cascode amplifier structure.Current source IB2 and transistor Q1 provides grid bias for transistor Q2.Setting voltage VB2 is the grid bias of transistor Q5.The drain terminal of transistor Q3 is connected to the grid end A of power Correctional tube Q6, and the grid end of transistor Q3 is connected to the drain terminal of transistor Q2 and the drain terminal of transistor Q4, the source ground connection of transistor Q2 simultaneously; The source of transistor Q4 is connected to power vd D, and the grid end of transistor Q4 is connected to the source of transistor Q3 and the drain terminal of transistor Q5 simultaneously, and the source of transistor Q5 is connected to power vd D;

Transistor Q10, Q11, Q12, Q13 form another adjustable cascode amplifier structure.Current source IB1 and transistor Q14 provides grid bias for transistor Q13.The drain terminal of transistor Q13 is connected to the grid end of transistor Q11 and the drain terminal of transistor Q12, the source ground connection of transistor Q12 simultaneously; The grid end of transistor Q12 is connected to the drain terminal of the source of transistor Q11, the drain terminal B of transistor Q8 and transistor Q10, the source ground connection of transistor Q10 simultaneously.Setting voltage VB1 is the grid bias of transistor Q10.

Source, the power Correctional tube Q6 drain terminal of transistor Q8 are connected to output voltage OUT altogether.The grid end of transistor Q8 and the grid end of transistor Q7, drain terminal connect altogether.The source of transistor Q7 is connected to the output terminal C of amplifier OP, and the positive input of amplifier OP is VREF end, and the reverse input end of amplifier OP, respectively through resistance R1 ground connection, is connected to output terminal C through resistance R2.

As load R _lthere is transition, cause output voltage OUT to change, and then same phase change occurs Node B.The variable quantity of Node B feeds back to the grid end of power Correctional tube Q6 after the adjustable cascade of transistor Q10 ~ Q13 amplifies, due to the grid end of power Correctional tube Q6 to drain terminal through 180 degree of phase shifts, and then inhibit the change of output voltage OUT, make the output voltage OUT fast and stable of LDO.Wherein the high impedance load of adjustable common source and common grid amplifier is made up of transistor Q2 ~ Q5.

If mutual conductance and the intrinsic impedance of transistor Qi are respectively g _miand r _0i, then the adjustable cascade (RGC) be made up of transistor Q2 ~ Q5 is g in the impedance of A point _m4r _o4g _m3r _o3× r _o5.In like manner, the RGC be made up of transistor Q10 ~ Q13 is g at A point impedance _m12r _o12g _m11r _o11× (r _o10//r _o10),

A point resulting impedance r _afor:

r _A＝(g _m4r _o4g _m3r _o3×r _o5)//[g _m12r _o12g _m11r _o11×(r _o10//r _o10)] (1)

Formula (1) promotes nearly 2 orders of magnitude than the output impedance of traditional cathode-input amplifier.

The stray capacitance C of power Correctional tube Q6 _gd6, form miller compensation electric capacity.Therefore the limit of A:

$P_A=\frac{1}{r_A\×\[C_{gs6}+(1+A_6)C_{gd6}\]}---\left(2\right)$

Wherein, A ₆for the voltage gain of power Correctional tube Q6.

Disconnect at B point, calculate the open-loop gain A of LDO _open:

A _open＝g _m11r _o11g _m12r _o12×-g _m6(r _o10//g _m8r _o8r _o6) (3)

At the open loop impedance r of the OUT that B point disconnects _open:

$r_{open}=r_{o6}//(1+\frac{r_{o10}}{r_{o8}})\×\frac{1}{g_{m8}}---\left(4\right)$

Closed loop output impedance r _closed:

$r_{closed}=\frac{r_{open}}{1+\left|A_{open}\right|}\≈\frac{1}{g_{m11}{r}_{o11}{g}_{m12}{r}_{o12}}\×\frac{1}{g_{m8}(r_{o8}//r_{o10})}\×\frac{1}{g_{m6}}---\left(5\right)$

By (4) and (5), output impedance about 3 orders of magnitude less of traditional emitter follower output impedance of the utility model LDO circuit, therefore output voltage OUT place is low-impedance node.Even if load capacitance is comparatively large, also can ensure to export limit outside unity gain bandwidth.Known by (2) and (5), P _afor the dominant pole of system.

Parasitic Right-half-plant zero is wherein C _gd6and g _m6be respectively drain-gate capacitance and the mutual conductance of power Correctional tube Q6, because OUT is low-impedance node, even if when underloading, Q6 has certain bias current, therefore relative g _m6comparatively large, z ₀for high frequency zero point, can ignore.

The biased reference voltage VREF end by transistor Q7 and setting of transistor Q8 provides, the therefore output voltage OUT of LDO:

$OUT\≈VC=VREF(1+\frac{R2}{R1})---\left(6\right)$

Fig. 2 is the relation between LDO load current and loop phase nargin, and when load capacitance is 200pF, during load current change, phase margin is greater than 45 degree.

As Fig. 3, the rising edge of load current and negative edge are 50ns, and load current minimum value is 0.1mA, and load current maximal value is 100mA, and due to the output AC impedance that LDO is minimum, load capacitance is that under 200pF, LDO still has good phase margin.When load current saltus step, falling of LDO output voltage is all less than 50mV with overshoot.

The above is only preferred implementation of the present utility model; should be understood that; for those skilled in the art; under the prerequisite not departing from the utility model know-why; can also make some improvement and distortion, these improve and distortion also should be considered as protection domain of the present utility model.

Claims (1)

1. fast transient response without a capacitor type LDO, it is characterized in that, introduce adjustable cascade feedback control loop at the drain terminal of power Correctional tube and grid end, make the output voltage of power Correctional tube source form the emitter follower that has profound and negative feedbck;

The variable quantity of output voltage feeds back to the grid end of power Correctional tube after adjustable common source and common grid amplifier is amplified;

Adjustable cascade feedback control loop comprises two adjustable cascode amplifiers;

One of them adjustable cascode amplifier is connected to the drain terminal of power Correctional tube, and this adjustable cascode amplifier comprises transistor seconds, third transistor, the 4th transistor and the 5th transistor; Second current source and the first transistor provide grid bias for transistor seconds; The drain terminal of third transistor is connected to the grid end of power Correctional tube, and the grid end of third transistor is connected to the drain terminal of transistor seconds and the drain terminal of the 4th transistor, the source ground connection of transistor seconds simultaneously; The source of the 4th transistor is connected to power vd D, and the grid end of the 4th transistor is connected to the source of third transistor and the drain terminal of the 5th transistor simultaneously, and the source of the 5th transistor is connected to power vd D;

Wherein another adjustable cascode amplifier is connected to the grid end of power Correctional tube, and this adjustable cascode amplifier comprises the tenth transistor, the 11 transistor, the tenth two-transistor and the 13 transistor; First current source and the 14 transistor provide grid bias for the 13 transistor; The drain terminal of the 13 transistor is connected to the grid end of the 11 transistor and the drain terminal of the tenth two-transistor simultaneously, the source ground connection of the tenth two-transistor; The grid end of the tenth two-transistor is connected to the drain terminal of the source of the 11 transistor, the drain terminal of the 8th transistor and the tenth transistor, the source ground connection of the tenth transistor simultaneously;

The source of power Correctional tube drain terminal and the 8th transistor is connected to output voltage altogether;

The grid end of the 8th transistor and the grid end of the 7th transistor, drain terminal connect altogether; The source of the 8th transistor is connected to adjustable cascade feedback control loop;

The source of the 7th transistor is connected to the output terminal of amplifier, and the positive input of amplifier is reference voltage end, and the reverse input end of amplifier, respectively through the first resistance eutral grounding, is connected to the output terminal of amplifier through the second resistance.