CN204578695U - A kind of multifunctional image processing platform of infrared and visible ray binary channels high frame rate - Google Patents
A kind of multifunctional image processing platform of infrared and visible ray binary channels high frame rate Download PDFInfo
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- CN204578695U CN204578695U CN201520145086.7U CN201520145086U CN204578695U CN 204578695 U CN204578695 U CN 204578695U CN 201520145086 U CN201520145086 U CN 201520145086U CN 204578695 U CN204578695 U CN 204578695U
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Abstract
The utility model relates to a kind of multifunctional image processing platform of infrared and visible ray binary channels high frame rate, video image pretreatment module can be decoded the high frame rate vedio data of different-format, Computer Vision module adopts the first chip of DAVINCI framework and the second chip to build multifunctional image processing platform, and in the first chip and the second chip, the inside of any one is integrated with DSP kernel, HDVICP coprocessor and ARM kernel.According to multifunctional image processing platform of the present utility model, this locality that can complete mass data stores and Internet Transmission, and image coding and decoding ability is strong, operational capability and adaptability good.
Description
Technical field
The utility model relates to photovoltaic applied technical field, particularly relates to a kind of multifunctional image processing platform of infrared and visible ray binary channels high frame rate.
Background technology
Below background of related of the present utility model is described, but these explanations might not form prior art of the present utility model.
Need to carry out reprocessing after the image information of photovoltaic is acquired, image processing platform is the important carrier image information of photovoltaic being carried out to reprocessing, can realize the functions such as the collection of image information, preliminary treatment, image procossing, compression, local storage and remote transmission.At present, multifunctional image processing platform has been successfully applied to space base electro-optical system, high frame rate observation system and Compressed video supervisal system etc. round the clock.
At present, image processing platform generally carries out specialized designs for a certain image processing function, its processor many employings FPGA, DSP, ARM, multimedia SOC etc.FPGA can improve parallel data processing ability greatly, but functional realiey is complicated, secondary R&D costs are high.DSP is the image processing platform acp chip comparatively commonly used, and operational capability is strong, strong adaptability, but along with the continuous lifting of compress technique and image resolution ratio, and simple to use DSP to reduce the staff code to vedio data more and more difficult.The rich interface of ARM, inner integrated codec, can complete image coding and decoding preferably, but operational capability is weak.
Therefore, a kind of can solution due to the single kernel of image processing platform is needed and the solution of the restricted problem of image-capable of image processing platform in prior art, play the advantage of each processor, form a kind of multifunctional image processing platform of infrared and visible ray binary channels high frame rate.
Utility model content
The purpose of this utility model is the technical scheme of the multifunctional image processing platform proposing the infrared and visible ray binary channels high frame rate that a kind of image-capable is strong, adaptability is good.
According to the multifunctional image processing platform of infrared and visible ray binary channels high frame rate of the present utility model, comprising: video image acquisition module, video image pretreatment module, Computer Vision module, peripheral interface module and power management module; High frame rate vedio data is transferred to video image pretreatment module after video image acquisition module acquires, decoding and is carried out preliminary treatment; Computer Vision module carries out image procossing to what receive through the pretreated high frame rate vedio data of video image pretreatment module, and the high frame rate vedio data after image procossing is transferred to the peripheral interface module of the first chip;
Image pre-processing module comprises: high performance programmable logical block FPGA and Double Data Rate synchronous DRAM DDR; FPGA in image pre-processing module is used for carrying out preliminary treatment to what receive through the decoded high frame rate vedio data of described video image acquisition module, and the DDR in image pre-processing module is used for the data in cache image preprocessing process; Comprise through the pretreated high frame rate vedio data of described video image pretreatment module: the first vedio data and the second vedio data;
Image processing module comprises: the first chip, the second chip, and connects the twoport of the first chip and the second chip; First chip is for receiving the first vedio data and carrying out image procossing; Second chip is for receiving the second vedio data and carrying out image procossing; Described twoport is for completing the information interaction of the first chip and the second chip;
Peripheral interface module comprises: the peripheral interface module of the first chip, and the peripheral interface module of the second chip;
The second vedio data after image procossing is transferred to the first chip by twoport by the second chip; The first vedio data after image procossing and transfer to the first chip image procossing after the second vedio data gathered by the first chip after, the peripheral interface module transferring to the first chip carries out storing and Internet Transmission.
Wherein, video image acquisition module comprises: video image interface, and decoding chip; Video image interface comprises: CVBS video interface, SDI video interface, HDMI video interface, infrared Camerlink video interface, and visible ray Camerlink video interface; Decoding chip comprises: TVP5150 chip, SII9125 chip, GS2970 chip, and SN65LVDS94 chip; TVP5150 chip decoding CVBS video, SII9125 chip decoding HDMI video, GS2970 chip decoding SDI video, SN65LVDS94 receives infrared Camerlink video and visible ray Camerlink video.
Wherein, any one in the first chip and the second chip is the chip of DAVINCI framework.
Wherein, the C64x+DSP kernel of the integrated 1GHz in inside of any one in the first chip and the second chip.
Wherein, H.264 any one the integrated HDVICP coprocessor in inside in the first chip and the second chip, compress pretreated high frame rate vedio data with collaborative DSP, reach hi-vision compression ratio and good image visual effect.
Wherein, image processing module also comprises: two Double Data Rate synchronous DRAM DDR, two NAND FLASH and two SPI type EEPROM; The program when DDR of the first chip periphery runs for DSP and ARM storing the first chip; The NAND FLASH of the first chip periphery is for storing operating system and the application program of the first chip; The SPI type EEPROM of the first chip periphery, for storing the startup-program code of the first chip, completes the guiding startup work of the first stage of the first chip operating system; The program when DDR of the second chip periphery runs for DSP and ARM storing the second chip; The NAND FLASH of the second chip periphery is for storing operating system and the application program of the second chip; The SPI type EEPROM of the second chip periphery, for storing the startup-program code of the second chip, completes the guiding startup work of the first stage of the second chip operating system.
Wherein, the peripheral interface module of the first chip periphery comprises: debugging interface, network interface, communication interface, and hard-disk interface; The peripheral interface module of the second chip periphery comprises: debugging interface and network interface; Debugging interface is for debugging multifunctional image processing platform, comprise: jtag interface and terminal serial ports, wherein, jtag interface is used for the programming of application program and the interior driver code stored of NAND FLASH stored in bare machine debugging, SPI type EEPROM and NAND FLASH, and terminal serial ports is used for the information interaction of commissioning staff and operating system; Network interface is used for carry file in the process of debugging multifunctional image processing platform, and realizes the Internet Transmission of the high frame rate vedio data after described Computer Vision resume module; Communication interface is used for communicating with the superior system of multifunctional image processing platform, receives the order request of superior system, and the processing result image of multifunctional image processing platform is transferred to superior system; Hard-disk interface is for storing the high frame rate vedio data after Computer Vision module image procossing.
According to the multifunctional image processing platform of infrared and visible ray binary channels high frame rate of the present utility model, video image pretreatment module can be decoded the high frame rate vedio data of different-format, Image semantic classification and data buffering ability strong.Computer Vision module adopts the first chip of DAVINCI framework and the second chip to build multifunctional image processing platform, carries out image procossing to pretreated high frame rate vedio data.In first chip and the second chip, the inside of any one is integrated with DSP kernel, HDVICP coprocessor and ARM kernel.First chip receives the first vedio data and carries out image procossing; Second chip receives the second vedio data, carries out image procossing, and the second vedio data after image procossing is transferred to the first chip by twoport; First chip by the first vedio data after process and transfer to the first chip process after the second vedio data gather after, transfer to the peripheral interface module of the first chip.According to multifunctional image processing platform of the present utility model, image coding and decoding ability is strong, operational capability and adaptability good.
Accompanying drawing explanation
By the embodiment part provided referring to accompanying drawing, feature and advantage of the present utility model will become easier to understand, in the accompanying drawings:
Fig. 1 illustrates the schematic diagram according to multifunctional image processing platform of the present utility model;
Fig. 2 illustrates the first embodiment schematic diagram according to multifunctional image processing platform of the present utility model.
Embodiment
With reference to the accompanying drawings illustrative embodiments of the present utility model is described in detail.Be only for demonstration object to the description of illustrative embodiments, and be never the restriction to the utility model and application or usage.
According to the multifunctional image processing platform of infrared and visible ray binary channels high frame rate of the present utility model, comprising: video image acquisition module 1, video image pretreatment module 2, Computer Vision module 3, peripheral interface module 4 and power management module 5.High frame rate vedio data is gathered by video image acquisition module 1, decode after, transfer to video image pretreatment module 2; After video image pretreatment module 2 preliminary treatment, transferred to peripheral interface module 4 by Computer Vision module 3 image procossing.
Be described in detail to according to multifunctional image processing platform that is infrared and visible ray binary channels high frame rate of the present utility model below in conjunction with Fig. 1-2.
Video image acquisition module 1 for gathering the vedio data of multiple format, and transfers to video image pretreatment module 2 after being decoded by the high frame rate vedio data collected.Video image acquisition module 1 comprises: video image interface and decoding chip.According to the preferred embodiment of multifunctional image processing platform of the present utility model, video image interface comprises: CVBS video interface CVBS-IN, for gathering CVBS video; SDI video interface SDI-IN, for gathering SDI video; HDMI video interface HDMI-IN, for gathering HDMI video; Infrared Camerlink video interface Camerlink-IN1, for gathering infrared Camerlink video; And visible ray Camerlink video interface Camerlink-IN2, for gathering visible ray Camerlink video.Infrared video view data and the visible light video image data of distinct interface form can be gathered according to the video image acquisition module 1 of multifunctional image processing platform of the present utility model, and transfer to decoding chip and decode.Wherein, decoding chip comprises: TVP5150 chip, for CVBS video of decoding; SII9125 chip, for HDMI video of decoding; GS2970 chip, for; And SN65LVDS94 chip, for decoding IR Camerlink video and visible ray Camerlink video.Video image acquisition module 1 according to multifunctional image processing platform of the present utility model can to the infrared video view data of distinct interface form and visible light video image decoding data, and decoded vedio data transfers to video image pretreatment module 2 after drive circuit drives.
Image pre-processing module 2 for carrying out preliminary treatment to decoded vedio data, thus makes vedio data meet the timing requirements of image processing module 3.Image pre-processing module 2 comprises: programmable logic cells FPGA, and Double Data Rate synchronous DRAM DDR; Programmable logic cells FPGA is used for carrying out preliminary treatment to decoded vedio data, and the DDR in image pre-processing module 2 is used for the data in cache image preprocessing process.Preferably, programmable logic cells FPGA in image pre-processing module 2 is FPGA:V4SX25, DDR in image pre-processing module 2 is 256M DDR, according to multifunctional image processing platform of the present utility model, Image semantic classification ability and data buffering ability by force, can reduce the load of image processing module 3.The first vedio data and the second vedio data is comprised through the pretreated high frame rate vedio data of video image pretreatment module 2, first vedio data the first chip 31, second vedio data transferred in image processing module 3 transfers to the second chip 32 in image processing module 3.
Image processing module 3 is for carrying out image procossing to through the pretreated high frame rate vedio data of video image pretreatment module 2.Comprise: the first chip 31, second chip 32, and connect the twoport 33 of the first chip and the second chip.The operational capability of DSP kernel is strong, strong adaptability, but the interface of DSP kernel is single, and when being subsequently processed image resolution ratio and frequency increases, the processing speed of DSP kernel is slow.The rich interface of ARM kernel, and inner integrated codec, can complete image coding and decoding preferably, but the operational capability of ARM kernel is weak.According to the preferred embodiment of multifunctional image processing platform of the present utility model, in the first chip 31 and the second chip 32, the inside of any one is all integrated with DSP kernel and ARM kernel, thus improves graphics capability and the adaptability of image processing module 3.In addition, in first chip 31 and the second chip 32, the inside of any one is also integrated with HDVICP coprocessor, complete with collaborative DSP and H.264 pretreated high frame rate vedio data is compressed, reach hi-vision compression ratio and good image visual effect.By the integrated HDVICP coprocessor in inside at the first chip 31 and the second chip 32, while the high definition encoding and decoding completing high frame rate vedio data, the load of DSP kernel greatly can be reduced.
The chip of DAVINCI framework is according to any one in preferred embodiment first chip 31 of multifunctional image processing platform of the present utility model and the second chip 32, the C64x+DSP kernel of all integrated 1GHz in inside of any one in first chip 31 and the second chip 32, and include two multipliers, the level system buffer memory of a 64KBytes and the level two buffer memory of a 12Kbytes.
Preferably, image procossing mould 3 pieces also comprises: two Double Data Rate synchronous DRAM DDR, two NAND FLASH and two SPI type EEPROM; The program when DDR of the first chip 31 periphery runs for DSP and ARM storing the first chip 31; The NAND FLASH of the first chip 31 periphery is for storing operating system and the application program of the first chip 31; The SPI type EEPROM of the first chip 31 periphery, for storing the startup-program code of the first chip 31, completes the guiding startup work of the first stage of the operating system of the first chip 31; Program when the peripheral DDR of second 32, core runs for DSP and ARM storing the second chip 32; The NAND FLASH of the second chip 32 periphery is for storing operating system and the application program of the second chip 32; The SPI type EEPROM of the second chip 32 periphery, for storing the startup-program code of the second chip 32, completes the guiding startup work of the first stage of the first chip operating system.
First chip 31 receives the first vedio data and carries out image procossing, HDVICP coprocessor collaborative under H.264 pretreated first vedio data is compressed; Second chip 32 receives the second vedio data and carries out image procossing, HDVICP coprocessor collaborative under H.264 pretreated second vedio data is compressed.The second vedio data after image procossing transfers to the first chip 31 by twoport 33, after the second vedio data after the process that the first vedio data after compression and twoport 33 transmit by the first chip 31 gathers, transfer to the peripheral interface module 41 of the first chip 31.
Peripheral interface module 4 comprises: the peripheral interface module 41 of the first chip 31, and the peripheral interface module 42 of the second chip 32.The peripheral interface module 41 of the first chip 31 comprises: debugging interface, network interface, communication interface, and hard-disk interface; The peripheral interface module 42 of the second chip 32 comprises: debugging interface and network interface.
Debugging interface is for debugging multifunctional image processing platform, comprise: jtag interface and terminal serial ports, wherein, jtag interface is used for the programming of application program and the interior driver code stored of NAND FLASH stored in bare machine debugging, SPI type EEPROM and NAND FLASH, and terminal serial ports is used for the information interaction of commissioning staff and operating system.Network interface is used for carry file in the process of debugging multifunctional image processing platform, and realizes the Internet Transmission of the high frame rate vedio data after Computer Vision module 3 image procossing.Communication interface is used for communicating with the superior system of multifunctional image processing platform, realizes information interaction.Hard-disk interface is for storing the high frame rate vedio data after Computer Vision module 3 image procossing.First chip 31 is received by the hard-disk interface in the communication interface in peripheral interface module 41 and peripheral interface module 41 after the high frame rate vedio data after gathering is transferred to peripheral interface module 41; Communication interface in peripheral interface module 41 carries out Internet Transmission after receiving the vedio data after gathering, and the hard-disk interface in peripheral interface module 41 carries out local mass data storage after receiving the vedio data after gathering.
Power management module 5 for generation of reset signal, and is other module for power supply in multifunctional image processing platform.Power management module 5 adopts multilayer circuit to design, and uses Switching Power Supply, thus improves the service efficiency of power supply, reduces the loss in Power convert process.
According to multifunctional image processing platform of the present utility model when carrying out board design, high-speed PCB principle should be deferred to.
According to the multifunctional image processing platform of infrared and visible ray binary channels high frame rate of the present utility model, video image pretreatment module 2 can be decoded the vedio data of different-format.Computer Vision module 3 adopts the first chip 31 of DAVINCI framework and the second chip 32 to build multifunctional image processing platform, and in the first chip 31 and the second chip 32, the inside of any one is integrated with DSP kernel, HDVICP coprocessor and ARM kernel.First chip 31 receives the first vedio data and carries out image procossing; Second chip 32 receives, image procossing second vedio data, and the second vedio data after image procossing is transferred to the first chip 31 by twoport 33; First chip 31 by the first vedio data after image procossing and transfer to the first chip 31 image procossing after the second vedio data gather after, transfer to the peripheral interface module 41 of the first chip 31.According to multifunctional image processing platform of the present utility model, this locality that can complete mass data stores and Internet Transmission, and image coding and decoding ability is strong, operational capability and adaptability good.
Although be described the utility model with reference to illustrative embodiments, but be to be understood that, the utility model is not limited in literary composition the embodiment described in detail and illustrate, when not departing from claims limited range, those skilled in the art can make various change to described illustrative embodiments.
Claims (7)
1. a multifunctional image processing platform for infrared and visible ray binary channels high frame rate, comprising: video image acquisition module, video image pretreatment module, Computer Vision module, peripheral interface module and power management module; High frame rate vedio data is transferred to described video image pretreatment module after described video image acquisition module acquires, decoding and is carried out preliminary treatment; Described Computer Vision module carries out image procossing to what receive through the pretreated high frame rate vedio data of described video image pretreatment module, and the high frame rate vedio data after image procossing is transferred to described peripheral interface module;
It is characterized in that,
Described image pre-processing module comprises: high performance programmable logical block FPGA and Double Data Rate synchronous DRAM DDR; FPGA in described image pre-processing module is used for carrying out preliminary treatment to what receive through the decoded high frame rate vedio data of described video image acquisition module, and the DDR in image pre-processing module is used for the data in cache image preprocessing process; Comprise through the pretreated high frame rate vedio data of described video image pretreatment module: the first vedio data and the second vedio data;
Described image processing module comprises: the first chip, the second chip, and connects the twoport of the first chip and the second chip; First chip is for receiving the first vedio data and carrying out image procossing; Second chip is for receiving the second vedio data and carrying out image procossing; Described twoport is for completing the information interaction of the first chip and the second chip;
Described peripheral interface module comprises: the peripheral interface module of the first chip, and the peripheral interface module of the second chip;
The second vedio data after image procossing is transferred to the first chip by described twoport by the second chip; The first vedio data after image procossing and transfer to the first chip image procossing after the second vedio data gathered by the first chip after, the peripheral interface module transferring to the first chip carries out storing and Internet Transmission.
2. multifunctional image processing platform as claimed in claim 1, is characterized in that,
Described video image acquisition module comprises: video image interface, and decoding chip;
Described video image interface comprises: CVBS video interface, SDI video interface, HDMI video interface, infrared Camerlink video interface, and visible ray Camerlink video interface;
Described decoding chip comprises: TVP5150 chip, SII9125 chip, GS2970 chip, and Camerlink interface chip SN65LVDS94; Wherein,
TVP5150 chip decoding CVBS video, SII9125 chip decoding HDMI video, GS2970 chip decoding SDI video, SN65LVDS94 chip completes infrared and visible ray Camerlink video reception.
3. multifunctional image processing platform as claimed in claim 2, is characterized in that,
Any one in first chip and the second chip is the chip of DAVINCI framework.
4. multifunctional image processing platform as claimed in claim 3, is characterized in that,
The C64x+DSP kernel of the integrated 1GHz in inside of any one in first chip and the second chip.
5. multifunctional image processing platform as claimed in claim 4, is characterized in that,
H.264, any one the integrated HDVICP coprocessor in inside in first chip and the second chip, compresses pretreated high frame rate vedio data with collaborative DSP.
6. multifunctional image processing platform as claimed in claim 5, is characterized in that,
Described image processing module also comprises: two Double Data Rate synchronous DRAM DDR, two NAND FLASH and two SPI type EEPROM;
The program when DDR of the first chip periphery runs for DSP and ARM storing the first chip; The NAND FLASH of the first chip periphery is for storing operating system and the application program of the first chip; The SPI type EEPROM of the first chip periphery, for storing the startup-program code of the first chip, completes the guiding startup work of the first stage of the first chip operating system;
The program when DDR of the second chip periphery runs for DSP and ARM storing the second chip; The NAND FLASH of the second chip periphery is for storing operating system and the application program of the second chip; The SPI type EEPROM of the second chip periphery, for storing the startup-program code of the second chip, completes the guiding startup work of the first stage of the second chip operating system.
7. multifunctional image processing platform as claimed in claim 6, is characterized in that,
The described peripheral interface module of the first chip periphery comprises: debugging interface, network interface, communication interface, and hard-disk interface; The described peripheral interface module of the second chip periphery comprises: debugging interface and network interface;
Described debugging interface, for debugging described multifunctional image processing platform, comprising: jtag interface and terminal serial ports; Wherein, jtag interface is used for the programming of application program and the interior driver code stored of NAND FLASH stored in bare machine debugging, SPI type EEPROM; Terminal serial ports is used for the information interaction of commissioning staff and operating system;
Described network interface is used for carry file in the process of the described multifunctional image processing platform of debugging, and realizes the Internet Transmission of the high frame rate vedio data after described Computer Vision resume module;
Described communication interface is used for communicating with the superior system of described multifunctional image processing platform, receives the order request of described superior system, and the result of described multifunctional image processing platform is transferred to described superior system;
Described hard-disk interface is for storing the high frame rate vedio data after described Computer Vision resume module.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107292808A (en) * | 2016-03-31 | 2017-10-24 | 阿里巴巴集团控股有限公司 | Image processing method, device and image coprocessor |
| CN110381252A (en) * | 2019-07-18 | 2019-10-25 | 湖南宏动光电有限公司 | A kind of graphic system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107292808A (en) * | 2016-03-31 | 2017-10-24 | 阿里巴巴集团控股有限公司 | Image processing method, device and image coprocessor |
| CN107292808B (en) * | 2016-03-31 | 2021-01-05 | 阿里巴巴集团控股有限公司 | Image processing method and device and image coprocessor |
| CN110381252A (en) * | 2019-07-18 | 2019-10-25 | 湖南宏动光电有限公司 | A kind of graphic system |
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