CN111930663B - Mobile phone OLED screen cache chip with ultra-high speed interface - Google Patents
Mobile phone OLED screen cache chip with ultra-high speed interface Download PDFInfo
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- CN111930663B CN111930663B CN202011106267.0A CN202011106267A CN111930663B CN 111930663 B CN111930663 B CN 111930663B CN 202011106267 A CN202011106267 A CN 202011106267A CN 111930663 B CN111930663 B CN 111930663B
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- 230000005540 biological transmission Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 11
- 238000013500 data storage Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000006835 compression Effects 0.000 description 2
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- 230000006837 decompression Effects 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3265—Power saving in display device
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a mobile phone OLED screen cache chip with an ultra-high speed interface, which belongs to the technical field of data storage and comprises a cache memory chip, wherein the cache memory chip comprises a system chip bus interface connected with a main chip; the system chip bus interface comprises an input/output unit for outputting driving and receiving signals and a connector which is connected with the input/output unit and used for external circuit data transmission; the static random access unit is used for storing and reading data; the static random access unit is provided with a static storage compiler; a correction module; a control module for converting the data signal input from the device main body into the signal required by the screen driving chip; the high-speed connection interface is used for providing a data channel for the display driving chip and comprises an ultra-high speed interface circuit and a chip pin processing module; the OLED screen cache chip with the ultra-high-speed interface for the mobile phone reduces power consumption.
Description
Technical Field
The invention belongs to the technical field of data storage, and particularly relates to an OLED screen cache chip of a mobile phone with an ultra-high speed interface.
Background
The integrated DDI driving chip used by the mobile phone OLED screen comprises a single chip with an internal memory buffer, and is limited by the high-voltage process manufacturing capability (the manufacturing difficulty of the 28nm process of 8V HV is high) and the capacity limitation of the internal memory buffer (only 32M at present), so that a 3-time compression internal memory technology is used, but the power consumption of each decompression is high; with the rapid increase of the resolution of the OLED screen, the way of compressing the memory is abandoned, so as to reduce the power consumption. Secondly, the integrated DDI driving chip comprises a single chip with a memory buffer, the single chip, a high-voltage circuit and a logic circuit are integrated in the same chip, the capacity of the memory buffer is limited (only 32M at present), and with the rapid improvement of the resolution of the OLED screen, at least more than 64M of capacity is needed to be enough to deal with the middle-high order OLED screen; in addition, the single chip of the integrated DDI driving chip with the memory buffer does not have a high-speed interface and is not enough to deal with any large-screen product with high resolution and high refreshing speed. The invention mainly aims to solve the limitations of power consumption, cache capacity, bandwidth and the like.
Problem of power consumption: the integrated DDI driver chip has a single chip with memory buffer, which is limited by the high-voltage process manufacturing capability (the manufacturing difficulty of the 28nm process of 6V HV is high) and the capacity limitation of the memory buffer (currently, only 32M is available), so that the 3-time compression memory technology is used, but the power consumption of each decompression is very high; with the rapid increase of the resolution of the OLED screen, the way of compressing the memory is abandoned, so as to reduce the power consumption.
The problem of cache capacity: the integrated DDI driving chip comprises a single chip with a memory buffer, a high-voltage circuit and a logic circuit which are integrated in the same chip, the capacity of the memory buffer is limited (only 32M at present), and with the rapid improvement of the resolution of an OLED screen, the capacity of at least more than 64M is required to be enough to deal with the middle-high order OLED screen.
Bandwidth problem: the integrated DDI driving chip has a single chip with memory buffer and no high-speed interface, the requirement of total bandwidth of FHD is 8Gb/s at 120Hz, the chip of the separated SDM and the IO part adopt the design of the high-speed interface, the specification of bandwidth in Korea requires 36Gb/s, the specification is more than 4 times of the current specification, and the integrated DDI driving chip can be used for 4K panels at 120 Hz. It can be used for any large-screen products with high resolution and high refreshing speed.
With the gradual increase of the permeability of the OLED screen in the application of the mobile phone, the consumer market puts forward the requirements of larger size and higher resolution ratio on the OLED screen of the mobile phone, so that the defects of large area occupation ratio, high power consumption and the like of a chip of a current screen driving chip (DDI) embedded with a static random access cache module are gradually highlighted; the existing OLED screen is provided with a display driving chip which mainly comprises three blocks, wherein one block is a power supply module, a storage module and a logic module; the current high-resolution OLED screen driving chip has the problems of high power consumption, insufficient buffer capacity and insufficient bandwidth.
Disclosure of Invention
The invention aims to provide an OLED screen cache chip of a mobile phone with an ultra-high speed interface, which solves the problems of high power consumption, insufficient cache capacity and insufficient bandwidth of the traditional drive chip.
In order to achieve the purpose, the invention provides the following technical scheme: a mobile phone OLED screen cache chip with a super-speed interface comprises a cache memory chip, wherein the cache memory chip comprises a system chip bus interface connected with a main chip, a static random access unit used for storing and reading data, a correction module and a high-speed connection interface used for displaying a data channel provided by a driving chip; the system chip bus interface comprises an input/output unit for outputting driving and receiving signals and a connector which is connected with the input/output unit and used for external circuit data transmission;
the static random access unit is provided with a static storage compiler;
a correction module;
a control module for converting the data signal input from the device main body into the signal required by the screen driving chip;
the high-speed connection interface comprises an ultra-high speed interface circuit and a chip pin processing module;
the ultra-high speed interface circuit combines and outputs a clock signal sent by an analog signal module and an external clock signal to be processed as a system clock signal, divides the system clock signal into 1/2 and 1/4 clock signals through a digital logic module, stores the clock signals together with the system clock signal, and finally controls data to enter a static storage compiler through each clock signal.
Preferably, the control module comprises a scanning unit, a standby unit and a timing unit.
Preferably, the correction module includes a correction control module and a correction linking module.
Preferably, the chip pin processing module processes a signal of the super-high speed interface circuit and sends the processed signal to the cache memory chip, and then processes a signal output by the cache memory chip and sends the processed signal to the super-high speed interface circuit.
Preferably, the input/output unit includes an input/output library.
Preferably, the capacity of the sram is 128 MB.
Preferably, the cache memory chip is manufactured by using a 28nm process.
Preferably, the cache memory chip further comprises a customizable interconnection protocol and a portable runtime library.
The invention has the technical effects and advantages that: the OLED screen cache chip with the ultra-high-speed interface for the mobile phone reduces power consumption on one hand, and solves the problems that an existing single chip with a memory buffer does not have a high-speed interface, and is not enough to deal with any large screen, high resolution and high refreshing speed on the other hand.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a layout of the ultra high speed interface of the present invention;
FIG. 3 is a diagram of a conventional chip structure;
FIG. 4 is a block diagram of the present invention.
In the figure: 1. caching a memory chip; 3. An input/output unit; 4. a static random access unit; 5. a static storage compiler; 6. a correction module; 8. A high-speed connection interface; 81. an ultra-high speed interface circuit; 82. a chip pin processing module; 71. a scanning unit; 72. a standby unit; 73. a timing unit; 61. a correction control module; 62. a correction chaining module; 31. an input and output library; 9. a connector is provided.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a mobile phone OLED screen cache chip with a super high speed interface as shown in figures 1-4, which comprises a cache memory chip 1, wherein the cache memory chip 1 is manufactured by using a 28nm process, the cache memory chip 1 comprises a system chip bus interface connected with a main body chip, a static random access unit 4 for storing and reading data, a correction module 6 and a high speed connection interface 8 for providing a data channel for a display driving chip; the system chip bus interface comprises an input/output unit 3 for outputting driving and receiving signals and a connector 9 connected with the input/output unit 3 and used for external circuit data transmission; the input-output unit 3 includes an input-output library 31;
the capacity of the static random access unit 4 is 128MB, and the static random access unit 4 is provided with a static storage compiler 5;
the correction module 6 includes a correction control module 61 and a correction linking module 62,
a control module for converting the data signal input from the device main body into the signal required by the screen driving chip; the control module comprises a scanning unit 71, a standby unit 72 and a timing unit 73;
the high-speed connection interface 8 comprises a super-speed interface circuit 81 and a chip pin processing module 82; the chip pin processing module 82 processes the signal of the cache memory chip 81 and sends the processed signal to the cache memory chip 1, then the signal output by the cache memory chip 1 is processed and sent to the cache memory chip 81, the cache memory chip 81 combines and outputs the clock signal sent by the analog signal module and the external clock signal into a system clock signal for processing, the system clock signal is divided into 1/2 and 1/4 clock signals by the digital logic module and stored together with the system clock signal, finally, each clock signal controls data to enter the static memory compiler 5, and the cache memory chip 1 further comprises a customizable interconnection protocol and a portable operation library.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments or portions thereof without departing from the spirit and scope of the invention.
Claims (8)
1. The utility model provides a cell-phone OLED screen buffer memory chip with hypervelocity interface which characterized in that: the cache memory chip (1) comprises a system chip bus interface connected with a main chip, a static random access unit (4) used for storing and reading data, a correction module (6) and a high-speed connection interface (8) used for providing a data channel for a display driving chip; the system chip bus interface comprises an input/output unit (3) for outputting driving and receiving signals and a connector (9) connected with the input/output unit (3) and used for external circuit data transmission;
the static random access unit (4) is provided with a static storage compiler (5);
the control module is used for inputting data signals from the equipment main body and converting the data signals into signals required by the screen driving chip;
the high-speed connection interface (8) comprises a super-high speed interface circuit (81) and a chip pin processing module (82);
the ultra-high speed interface circuit (81) combines and outputs a clock signal sent by an analog signal module and an external clock signal into a system clock signal, divides the system clock signal into 1/2 and 1/4 system clock signals through a digital logic module, stores the system clock signals and the system clock signals, and finally controls data to enter a static storage compiler (5) through each clock signal.
2. The OLED screen cache chip with the ultra-high speed interface for the mobile phone according to claim 1, wherein: the control module comprises a scanning unit (71), a standby unit (72) and a timing unit (73).
3. The OLED screen cache chip with the ultra-high speed interface for the mobile phone according to claim 1, wherein: the correction module (6) comprises a correction control module (61) and a correction linking module (62).
4. The OLED screen cache chip with the ultra-high speed interface for the mobile phone according to claim 1, wherein: the chip pin processing module (82) processes and sends signals of the ultra-high speed interface circuit (81) to the cache memory chip (1), and then processes and sends signals output by the cache memory chip (1) to the ultra-high speed interface circuit (81).
5. The OLED screen cache chip with the ultra-high speed interface for the mobile phone according to claim 1, wherein: the input/output unit (3) includes an input/output library (31).
6. The OLED screen cache chip with the ultra-high speed interface for the mobile phone according to claim 1, wherein: the capacity of the SRAM (4) is 128 MB.
7. The OLED screen cache chip with the ultra-high speed interface for the mobile phone according to claim 1, wherein: the cache memory chip (1) is manufactured by using a 28nm technology.
8. The OLED screen cache chip with the ultra-high speed interface for the mobile phone according to claim 1, wherein: the cache memory chip (1) also comprises a customizable interconnection protocol and a portable running library.
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| CN202011106267.0A CN111930663B (en) | 2020-10-16 | 2020-10-16 | Mobile phone OLED screen cache chip with ultra-high speed interface |
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| CN112559413B (en) * | 2021-03-01 | 2021-05-11 | 南京初芯集成电路有限公司 | Ultra-high speed interface of OLED screen driving chip and driving chip framework |
| CN117222271B (en) * | 2023-11-07 | 2024-02-02 | 上海视涯技术有限公司 | Silicon-based display module and display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN207184718U (en) * | 2017-09-21 | 2018-04-03 | 苏州科技大学 | A kind of PC high definition video interfaces automatic detection device |
| CN108880686A (en) * | 2018-07-14 | 2018-11-23 | 苏州大学张家港工业技术研究院 | Single-chip OUN towards the FPGA transceiver for more applying PON |
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| US9530513B1 (en) * | 2015-11-25 | 2016-12-27 | Intel Corporation | Methods and apparatus to read memory cells based on clock pulse counts |
| CN106297655B (en) * | 2016-08-17 | 2019-12-31 | 南京华讯方舟通信设备有限公司 | OLED display screen and display control device thereof |
| KR102549463B1 (en) * | 2016-08-30 | 2023-06-30 | 삼성전자주식회사 | Method for Processing Image and the Electronic Device supporting the same |
| KR102611266B1 (en) * | 2016-09-02 | 2023-12-08 | 에스케이하이닉스 주식회사 | Memory system and operating method of memory system |
| KR20180046428A (en) * | 2016-10-27 | 2018-05-09 | 삼성전자주식회사 | Memory device and training method thereof |
| KR102398181B1 (en) * | 2017-07-03 | 2022-05-17 | 삼성전자주식회사 | Storage device previously managing physical address to be allocated for write data |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN207184718U (en) * | 2017-09-21 | 2018-04-03 | 苏州科技大学 | A kind of PC high definition video interfaces automatic detection device |
| CN108880686A (en) * | 2018-07-14 | 2018-11-23 | 苏州大学张家港工业技术研究院 | Single-chip OUN towards the FPGA transceiver for more applying PON |
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Application publication date: 20201113 Assignee: Nanjing Jiangbei new area Yangzi Technology Finance Leasing Co.,Ltd. Assignor: Nanjing Chuxin integrated circuit Co.,Ltd. Contract record no.: X2021320000052 Denomination of invention: A mobile phone OLED screen cache chip with ultra-high speed interface Granted publication date: 20210105 License type: Exclusive License Record date: 20210804 |
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Denomination of invention: A mobile phone OLED screen cache chip with ultra-high speed interface Effective date of registration: 20210809 Granted publication date: 20210105 Pledgee: Nanjing Jiangbei new area green Financing Guarantee Co.,Ltd. Pledgor: Nanjing Chuxin integrated circuit Co.,Ltd. Registration number: Y2021320000156 |
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Assignee: Nanjing Jiangbei new area Yangzi Technology Finance Leasing Co.,Ltd. Assignor: Nanjing Chuxin integrated circuit Co.,Ltd. Contract record no.: X2021320000052 Date of cancellation: 20220915 |
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Date of cancellation: 20220926 Granted publication date: 20210105 Pledgee: Nanjing Jiangbei new area green Financing Guarantee Co.,Ltd. Pledgor: Nanjing Chuxin integrated circuit Co.,Ltd. Registration number: Y2021320000156 |
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Address after: 530201 Unit 01-09, 38th Floor, Guangxi Hejing International Financial Plaza, No. 18 Kaixuan Road, Nanning Area, China (Guangxi) Pilot Free Trade Zone, Nanning City, Guangxi Zhuang Autonomous Region Patentee after: Nanning Chuxin Integrated Circuit Design Co.,Ltd. Country or region after: China Address before: Room 1023, Yingying building, 99 Tuanjie Road, yanchuangyuan, Jiangbei new district, Nanjing, Jiangsu 210043 Patentee before: Nanjing Chuxin integrated circuit Co.,Ltd. Country or region before: China |