CN105448223B - A kind of display control circuit and display device - Google Patents
A kind of display control circuit and display device Download PDFInfo
- Publication number
- CN105448223B CN105448223B CN201511019756.1A CN201511019756A CN105448223B CN 105448223 B CN105448223 B CN 105448223B CN 201511019756 A CN201511019756 A CN 201511019756A CN 105448223 B CN105448223 B CN 105448223B
- Authority
- CN
- China
- Prior art keywords
- frame buffer
- sequence controller
- display
- data
- display control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The present invention provides a kind of display control circuit and display device, sequence controller including being used for transmitting data-signal and be formed after handling the data-signal image information, for store described image information and after described image information is handled output to the sequence controller frame buffer, for providing data-signal to display equipment, and the data drive circuit of the display image of the display equipment is controlled, to manage the power management integrated circuit of the electric energy of the sequence controller, frame buffer and data drive circuit；On the first integrated circuit, the sequence controller and the data drive circuit integrating are on the second integrated circuit for the frame buffer and the power management integrated circuit integrating.A kind of display control circuit provided by the invention and display device display control circuit production cost are low, can better adapt to the demand of display equipment high definition resolution ratio.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of display control circuit and display device.
Background technology
For showing the sequence controller in equipment display control circuit, frame buffer be it is a kind of necessary there are device,
Such as the overdrive technique of liquid crystal display just need to be applied to so-called frame buffer (Frame Buffer) it is each to store
The image information of frame.Existing frame buffer is incorporated into sequence controller by the canned program of sequence controller,
I.e. the other parts of sequence controller and frame buffer are to separate production, are then packaged together in encapsulated program, are encapsulated
Process is numerous and diverse, of high cost.And in today that the high definition Definition TV epoch arrive, since image resolution ratio increasingly increases, many
The algorithmic technique using frame buffer is needed to be required for the data of processing flood tide, therefore frame buffer cost also greatly improves.Meanwhile
Due to sequence controller, frame buffer, power management integrated circuit and other work(of part in display equipment display control circuit
The circuit of energy is generally positioned on same circuit main board, therefore the circuit main board volume is big, needs to be placed on the display
The position that equipment is specially set shows the volume of equipment also therefore becomes much larger and heavy, of high cost.
Invention content
In view of the above problems, patent purpose of the present invention is to devise a kind of display control circuit and display device, display
Control circuit production cost is low, can better adapt to the demand of display equipment high definition resolution ratio.The present invention is by following skill
What art scheme was realized：
A kind of display control circuit, including：
Sequence controller, for transmitting data-signal and forming image information after handling the data-signal；
Frame buffer is electrically connected with the sequence controller, for storing described image information and believing described image
Breath is exported after being handled to the sequence controller；
Data drive circuit is connect with the sequence controller, for providing data-signal, and control institute to display equipment
State the display image of display equipment；
Power management integrated circuit, to manage the sequence controller, frame buffer and the electric energy of data drive circuit；
The frame buffer and the power management integrated circuit integrating on the first integrated circuit, the sequential control
Device processed and the data drive circuit integrating are on the second integrated circuit.
Further, sequence controller of the present invention includes data processing module, and the data processing module is used for institute
It states data-signal and carries out compressed encoding and compression coding processing.
Further, data processing module of the present invention is electrically connected with the frame buffer.
Further, the connection cabling quantity between sequence controller of the present invention and the frame buffer is by image information
Compression ratio and power management integrated circuit package size determine.
Further, the connection cabling quantity between sequence controller of the present invention and the frame buffer is by equation below
It determines：
C=Cs×Ctr,
C in formulatrFor the compression ratio because of frame buffer transmission rate limitation, CsFor the pressure because of frame buffer storage volume limitation
Shrinkage, NoFor former number of leads, NsQuantity after being reduced for lead, MsSize, F can be stored for frame buffersImage for every frame is big
It is small, FmoFor frame buffer transmission frequency, FraFor display image renewal frequency, δ is whether frame buffer is double data rate,
It is then 2 to be, is otherwise 1；C is compression ratio needed for final image information.
Further, the connection cabling quantity between sequence controller of the present invention and the frame buffer is less than the frame
The pin number of buffer.
Further, frame buffer of the present invention is Double Data Rate synchronous DRAM.
The present invention also provides a kind of display devices, including display screen and the display control circuit, the display control
Circuit processed is electrically connected the display screen and controls the display image of the display screen.
Display control circuit of the present invention no longer needs the envelope by the sequence controller due to the frame buffer
Dress program is encapsulated in the sequence controller, but is incorporated into the production process of power management integrated circuit, by the frame
Buffer is integrated on the same integrated circuit with the power management integrated circuit, therefore reduces the sequence controller
Packaging cost namely the cost for reducing entire display control circuit make it possible to better adapt to existing display equipment high definition
The demand of resolution ratio.
Description of the drawings
Embodiments of the present invention is further illustrated referring to the drawings, wherein：
Fig. 1 is a kind of system pie graph of display control circuit of the present invention.
Specific embodiment
The present invention is described in further detail in the following with reference to the drawings and specific embodiments.
The present invention proposes a kind of display control circuit, referring to Fig. 1, including：Sequence controller 201, frame buffer
101st, power management integrated circuit 102 and data drive circuit 202.Wherein：
Sequence controller 201, for transmitting data-signal and forming image information after handling the data-signal；
Frame buffer 101 is electrically connected with the sequence controller 201, for storing described image information and by described image information
It is exported after being handled to the sequence controller 201；Data drive circuit 202 is connect with the sequence controller 201, is used
To provide data-signal to display equipment, and control the display image of the display equipment；Power management integrated circuit 102 is used
To manage the sequence controller 201, frame buffer 101 and the electric energy of data drive circuit 202.
The frame buffer 101 and 102 integrating of the power management integrated circuit are on the first integrated circuit 10, institute
Sequence controller 201 and 202 integrating of the data drive circuit are stated on the second integrated circuit 20.
In display control circuit described in the embodiment of the present invention, the frame buffer 101 is no longer needed by the timing control
The canned program of device 201 is encapsulated in the sequence controller 201, but is incorporated into the production of power management integrated circuit 102
In the process, the frame buffer 101 and the power management integrated circuit 102 are incorporated on first integrated circuit 10,
It reduces the packaging cost of the sequence controller 201 namely reduces the cost of entire display control circuit, make it possible to more
The demand of existing display equipment high definition resolution ratio is adapted to well.Simultaneously as the first integrated circuit 10 is small, do not need to specially
Circuit bearing substrate is set, any position of the display equipment using the display control circuit can flexibly be located at, had
Conducive to the flexibility for the planning arrangement for promoting the display device part, therefore the whole body of the display equipment can be reduced
Product reduces cost.
Further, since the sequence controller 201 and the data drive circuit 202 are incorporated into the second integrated electricity
On road 20, second integrated circuit 20 it is small, it is not required that specially set circuit bearing substrate, can flexibly set
In any position of the display equipment of the application display control circuit, be conducive to be promoted the planning of the display device part
The flexibility of arrangement, therefore the overall volume of the display equipment can be reduced, reduce cost.For example, the described first integrated electricity
Road 10, which can be arranged on television display system mainboard or be put in, achievees the purpose that reduction system volume on FPCA.
Display control circuit described in the present embodiment is since the sequence controller 201 and the frame buffer 101 being distinguished
It is integrated on the power management integrated circuit 102 and data drive circuit 202, and forms described the first of volume very little and integrate
Circuit 10 and second integrated circuit 20, it is no longer necessary to circuit bearing substrate be specially set, reduce the display control electricity
The packaging cost on road, simultaneously as first integrated circuit, 10 and second integrated circuit 20 can be placed on and described show
Show any position in the display equipment of control circuit, be conducive to be promoted the display device part planning arrangement it is flexible
Property, therefore the overall volume of the display equipment can be reduced, reduce cost.
In the present embodiment, data-signal is transmitted between the sequence controller 201 and the frame buffer 101.It is described
Sequence controller 201 includes data processing module, to carry out compressed encoding and compression coding to the signal, at the data
It manages module and is electrically connected the frame buffer 101.The data processing module is to described in formation after signal progress compressed encoding
Image information is transmitted into the frame buffer 101, and the frame buffer 101 stores described image information, and described image is believed
Breath is applied handled in special algorithm after output to the data processing module, by treated image information at the data
It manages module and is entered next step data processing after compression coding.
Further, the cabling quantity between the sequence controller 201 and the frame buffer 101 is delayed less than the frame
The pin number of storage 101.The cabling quantity meets equation below：
C in formulatr、CsCompression ratio (CtrFor the compression ratio because of frame buffer transmission rate limitation；CsTo be stored because of frame buffer
The compression ratio of capacity limit), NoFor former number of leads, NsQuantity after being reduced for lead, MsSize, F can be stored for frame buffers
For the image size of every frame, FmoFor for frame buffer transmission frequency, FraTo be frame buffer for display image renewal frequency, δ
Whether it is double data rate, it is then 2 to be, is otherwise 1.If CtrAnd CsCalculated value is more than 1, then CtrAnd Cs=1 (being not required to compress),
Compression ratio needed for final image information is
C=Cs×Ctr。
Hereinafter required compression ratio is brought into for data in embodiment：Assuming that NoIt is 16, NsFor 8, Ms=16Mbit, Fs=
1366x768x24bits, Fra=60Hz, Fmo=133MHz, δ=1, then
C=Cs×Ctr=73.8% × 45.1%=33.32%
In the present embodiment, the display control circuit strictly controls the sequence controller 201 and the frame buffer
Cabling quantity between 101, required for the display equipment that only retaining can meet using the display control circuit is shown
Data volume minimum cabling.It should be understood that display control circuit is by being suitably compressed image information described in the present embodiment
Content is simplified with achieving the purpose that the cabling quantity between the reduction sequence controller 201 and the frame buffer 101
The trace arrangements of the display control circuit further reduced the cost of the display control circuit.
In the present embodiment, the frame buffer 101 can be Double Data Rate synchronous DRAM (Double
Data Rate SDRAM) or flash memory or other can carry out the memory of data storage.Preferably, when the frame buffer 101
During for Double Data Rate synchronous DRAM, compression ratio requirement can be reduced.
The embodiment of the present invention also provides a kind of display equipment, and the display equipment includes described using above-described embodiment
The display control circuit and display screen, the display control circuit that technical solution is formed are electrically connected to the display screen and control institute
State the display image of display screen.
It should be understood that due to it is described display equipment used by display control circuit 10 He of the first integrated circuit
Second integrated circuit 20 can be placed on any position that should be in the display equipment of the display control circuit, be conducive to be promoted
The flexibility of the planning arrangement of the display device part, therefore the overall volume of the display equipment can be reduced, reduced
Cost.
The specific embodiment of present invention described above, is not intended to limit the scope of the present invention..Any basis
The various other corresponding changes and deformation that the technical concept of the present invention is made, should be included in the guarantor of the claims in the present invention
In the range of shield.
Claims (7)
1. a kind of display control circuit, which is characterized in that including：
Sequence controller, for transmitting data-signal and forming image information after handling the data-signal；
Frame buffer, with the sequence controller be electrically connected, for store described image information and by described image information into
It is exported after row processing to the sequence controller；
Data drive circuit is connect with the sequence controller, for providing data-signal to display equipment, and is controlled described aobvious
Show the display image of equipment；
Power management integrated circuit, to manage the sequence controller, frame buffer and the electric energy of data drive circuit；
The frame buffer and the power management integrated circuit integrating on the first integrated circuit, the sequence controller
With the data drive circuit integrating on the second integrated circuit；
Connection cabling quantity between the sequence controller and the frame buffer is determined by equation below：
C=Cs×Ctr,
C in formulatrFor the compression ratio because of frame buffer transmission rate limitation, CsFor the compression because of frame buffer storage volume limitation
Rate, NoFor former number of leads, NsQuantity after being reduced for lead, MsSize, F can be stored for frame buffersImage for every frame is big
It is small, FmoFor frame buffer transmission frequency, FraFor display image renewal frequency, δ is whether frame buffer is double data rate,
It is then 2 to be, is otherwise 1；C is compression ratio needed for final image information.
2. a kind of display control circuit according to claim 1, which is characterized in that the sequence controller is included at data
Module is managed, the data processing module is used for carrying out compressed encoding to the data-signal and compression coding is handled.
3. a kind of display control circuit according to claim 2, which is characterized in that the data processing module and the frame
Buffer is electrically connected.
4. a kind of display control circuit according to claim 1, which is characterized in that the sequence controller delays with the frame
Connection cabling quantity between storage is determined by image information compression ratio and power management integrated circuit package size.
5. a kind of display control circuit according to claim 4, which is characterized in that the sequence controller delays with the frame
Connection cabling quantity between storage is less than the pin number of the frame buffer.
6. a kind of display control circuit according to claim 4, which is characterized in that the frame buffer is same for Double Data Rate
Walk dynamic RAM.
7. a kind of display device, which is characterized in that including the display control described in any one of display screen and claim 1-6
Circuit, the display control circuit are electrically connected the display screen and control the display image of the display screen.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511019756.1A CN105448223B (en) | 2015-12-30 | 2015-12-30 | A kind of display control circuit and display device |
| PCT/CN2016/081671 WO2017113560A1 (en) | 2015-12-30 | 2016-05-11 | Display control circuit and display apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511019756.1A CN105448223B (en) | 2015-12-30 | 2015-12-30 | A kind of display control circuit and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105448223A CN105448223A (en) | 2016-03-30 |
| CN105448223B true CN105448223B (en) | 2018-06-12 |
Family
ID=55558343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511019756.1A Expired - Fee Related CN105448223B (en) | 2015-12-30 | 2015-12-30 | A kind of display control circuit and display device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105448223B (en) |
| WO (1) | WO2017113560A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448223B (en) * | 2015-12-30 | 2018-06-12 | 荆溪瑞 | A kind of display control circuit and display device |
| CN105405384A (en) * | 2015-12-31 | 2016-03-16 | 深圳市华星光电技术有限公司 | Display control circuit and display device |
| CN106782274A (en) * | 2017-01-17 | 2017-05-31 | 京东方科技集团股份有限公司 | A kind of display device and its driving method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376279A (en) * | 2010-08-12 | 2012-03-14 | 群康科技(深圳)有限公司 | Liquid crystal display device and driving method thereof |
| CN202275592U (en) * | 2011-10-19 | 2012-06-13 | 深圳市华星光电技术有限公司 | System for controlling over driver (OD) of liquid crystal display (LCD) |
| CN102789773A (en) * | 2012-08-13 | 2012-11-21 | 深圳市华星光电技术有限公司 | Control system of liquid crystal display device and liquid crystal display device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100559229B1 (en) * | 2003-04-01 | 2006-03-15 | 비오이 하이디스 테크놀로지 주식회사 | The Tuning Device for Control signals Of LCD |
| TWI260573B (en) * | 2004-05-14 | 2006-08-21 | Au Optronics Corp | Digital video signal processing device for LCD |
| CN105448223B (en) * | 2015-12-30 | 2018-06-12 | 荆溪瑞 | A kind of display control circuit and display device |
| CN105405384A (en) * | 2015-12-31 | 2016-03-16 | 深圳市华星光电技术有限公司 | Display control circuit and display device |
-
2015
- 2015-12-30 CN CN201511019756.1A patent/CN105448223B/en not_active Expired - Fee Related
-
2016
- 2016-05-11 WO PCT/CN2016/081671 patent/WO2017113560A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376279A (en) * | 2010-08-12 | 2012-03-14 | 群康科技(深圳)有限公司 | Liquid crystal display device and driving method thereof |
| CN202275592U (en) * | 2011-10-19 | 2012-06-13 | 深圳市华星光电技术有限公司 | System for controlling over driver (OD) of liquid crystal display (LCD) |
| CN102789773A (en) * | 2012-08-13 | 2012-11-21 | 深圳市华星光电技术有限公司 | Control system of liquid crystal display device and liquid crystal display device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2017113560A1 (en) | 2017-07-06 |
| CN105448223A (en) | 2016-03-30 |
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