WO2017113560A1 - Display control circuit and display apparatus - Google Patents

Display control circuit and display apparatus Download PDF

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Publication number
WO2017113560A1
WO2017113560A1 PCT/CN2016/081671 CN2016081671W WO2017113560A1 WO 2017113560 A1 WO2017113560 A1 WO 2017113560A1 CN 2016081671 W CN2016081671 W CN 2016081671W WO 2017113560 A1 WO2017113560 A1 WO 2017113560A1
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Prior art keywords
frame buffer
timing controller
control circuit
display
display control
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PCT/CN2016/081671
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French (fr)
Chinese (zh)
Inventor
荆溪瑞
黄浩
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荆溪瑞
黄浩
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Publication of WO2017113560A1 publication Critical patent/WO2017113560A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/16—Determination of a pixel data signal depending on the signal applied in the previous frame
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display control circuit and a display device.
  • the frame buffer is a necessary presence device.
  • the overdrive technology of the liquid crystal display needs to be applied to a so-called frame buffer to store each frame. Image information.
  • the current frame buffers are integrated into the timing controller by the timing controller's package program, that is, the other parts of the timing controller and the frame buffer are separately produced, and then packaged together by the packaged program. Complex and costly.
  • the timing controller, the frame buffer, the power management integrated circuit, and some other functions of the display device display control circuit are usually placed on the same circuit board, the circuit board is bulky and needs to be placed in the The position of the display device is specifically set, and the volume of the display device is thus made larger and cumbersome and costly.
  • the purpose of the present invention is to design a display control circuit and
  • the display device and the display control circuit have low production cost and can better meet the requirements of the high resolution of the display device.
  • the invention is achieved by the following technical solutions:
  • a display control circuit comprising:
  • timing controller for transmitting a data signal and processing the data signal to form image information
  • a frame buffer electrically connected to the timing controller for storing the image information and processing the image information to be output to the timing controller;
  • a data driving circuit coupled to the timing controller for providing a data signal to the display device and controlling a display image of the display device
  • a power management integrated circuit for managing power of the timing controller, the frame buffer, and the data driving circuit
  • the frame buffer and the power management integrated circuit are integrated on the first integrated circuit, and the timing controller and the data driving circuit are integrated and integrated on the second integrated circuit.
  • the timing controller of the present invention includes a data processing module, and the data processing module is configured to perform compression coding and compression decoding processing on the data signal.
  • the data processing module of the present invention is electrically connected to the frame buffer.
  • connection traces between the timing controller and the frame buffer of the present invention is determined by an image information compression ratio and a power management integrated circuit package size.
  • connection traces between the timing controller and the frame buffer of the present invention is determined by the following formula:
  • C tr is the compression ratio due to a frame buffer transfer rate limits
  • C s is the result of the compression rate frame buffer storage capacity limits
  • N o is the original number of leads
  • N s is the lead number
  • M s is the frame buffer
  • F s is the image size of each frame
  • F mo is the frame buffer transmission frequency
  • F ra is the display image update frequency
  • ⁇ is the frame buffer is double the data rate, is 2; otherwise 1
  • C is the compression ratio required for the final image information.
  • connection traces between the timing controller and the frame buffer of the present invention is less than the number of pins of the frame buffer.
  • the frame buffer of the present invention is a double rate synchronous dynamic random access memory.
  • the invention also provides a display device comprising a display screen and the display control circuit, the display control circuit electrically connecting the display screen and controlling a display image of the display screen.
  • the display control circuit of the present invention is integrated in the production process of the power management integrated circuit because the frame buffer is no longer required to be packaged in the timing controller by the package program of the timing controller.
  • the frame buffer is integrated with the power management integrated circuit on the same integrated circuit, thereby reducing the packaging cost of the timing controller, that is, reducing the cost of the entire display control circuit, so that it can better adapt to the present There is a need for display device HD resolution.
  • FIG. 1 is a system configuration diagram of a display control circuit of the present invention.
  • the present invention provides a display control circuit.
  • a timing controller 201 a frame buffer 101, a power management integrated circuit 102, and a data driving circuit 202 are provided. among them:
  • the timing controller 201 is configured to transmit a data signal and process the data signal to form image information.
  • the frame buffer 101 is electrically connected to the timing controller 201 for storing the image information and The image information is processed and output to the timing controller 201;
  • the data driving circuit 202 is connected to the timing controller 201 for providing a data signal to the display device and controlling the display image of the display device; power management integration
  • the circuit 102 is configured to manage power of the timing controller 201, the frame buffer 101, and the data driving circuit 202.
  • the frame buffer 101 and the power management integrated circuit 102 are integrated on the first integrated circuit 10, and the timing controller 201 and the data driving circuit 202 are integrated and integrated on the second integrated circuit 20.
  • the frame buffer 101 is no longer required to be encapsulated in the timing controller 201 by the package program of the timing controller 201, but integrated in the power management integrated circuit 102.
  • the frame buffer 101 and the power management integrated circuit 102 are integrated on the first integrated circuit 10, which reduces the packaging cost of the timing controller 201, that is, reduces the entire display control circuit. of The cost makes it better suited to the HD resolution of existing display devices.
  • the first integrated circuit 10 is small in size, it is not necessary to specifically set the circuit carrying substrate, and can be flexibly disposed at any position of the display device to which the display control circuit is applied, which is advantageous for improving the planning arrangement of the components in the display device. The flexibility makes it possible to reduce the overall size and cost of the display device.
  • the second integrated circuit 20 has a small volume, and does not need to specifically set the circuit carrying substrate, and can be flexibly Providing the arbitrary position of the display device to which the display control circuit is applied is advantageous for improving the flexibility of planning the arrangement of the components in the display device, thereby reducing the overall volume and cost of the display device.
  • the first integrated circuit 10 can be disposed on the main board of the television display system or placed on the FPCA to achieve the purpose of reducing the volume of the system.
  • the display control circuit of the embodiment integrates the timing controller 201 and the frame buffer 101 on the power management integrated circuit 102 and the data driving circuit 202, respectively, and forms the first volume having a small volume.
  • the integrated circuit 10 and the second integrated circuit 20 no longer need to specifically set the circuit carrying substrate, which reduces the packaging cost of the display control circuit, and at the same time, since the first integrated circuit 10 and the second integrated circuit 20 can be placed Any position on the display device that should be the display control circuit facilitates the flexibility of planning the arrangement of the components within the display device, thereby reducing the overall size and cost of the display device.
  • the timing controller 201 and the frame buffer 101 transmit data signals.
  • the timing controller 201 includes a data processing module for the letter The number is subjected to compression coding and compression decoding, and the data processing module is electrically connected to the frame buffer 101.
  • the data processing module compresses and encodes the signal to form the image information and transmits the image information into the frame buffer 101.
  • the frame buffer 101 stores the image information, and applies the image information to a specific algorithm. After processing, the image data is output to the data processing module, and the processed image information is compressed and decoded by the data processing module to enter the next data processing.
  • the number of traces between the timing controller 201 and the frame buffer 101 is less than the number of pins of the frame buffer 101.
  • the number of traces conforms to the following formula:
  • C tr C s compression ratio
  • C tr is due to limitations in the frame buffer the transmission rate of the compression ratio; C s as a result of the frame buffer storage compression rate capacity limits
  • N o is the number of primary leads
  • N s is the lead Reduce the number
  • M s is the frame buffer can store the size
  • F s is the image size of each frame
  • F mo is the frame buffer transmission frequency
  • F ra is the display image update frequency
  • ⁇ the frame buffer is double
  • the display control circuit strictly controls the number of traces between the timing controller 201 and the frame buffer 101, and only needs to retain the display device that can satisfy the application of the display control circuit for display. The minimum amount of data is traced. It can be understood that the display control circuit of the embodiment achieves the purpose of reducing the number of traces between the timing controller 201 and the frame buffer 101 by appropriately compressing the image information content, and simplifies the display. The circuit arrangement of the control circuit further reduces the cost of the display control circuit.
  • the frame buffer 101 may be a double rate synchronous dynamic random access memory (Double Data Rate SDRAM) or a flash memory or other memory that can perform data storage.
  • Double Data Rate SDRAM Double Data Rate SDRAM
  • the compression ratio requirement can be reduced.
  • An embodiment of the present invention further provides a display device including a display control circuit and a display screen formed by using the technical solution described in the foregoing embodiments, the display control circuit being electrically connected to the display screen and controlling the The display image of the display.
  • first integrated circuit 10 and the second integrated circuit 20 of the display control circuit used by the display device can be placed at any position on the display device that should be the display control circuit, it is advantageous to promote the The flexibility of the planned arrangement of the components within the device is shown, thereby reducing the overall size and cost of the display device.

Abstract

A display control circuit and a display apparatus, comprising: a timing controller (201) for transmitting a data signal and forming image information after processing the data signal; a frame buffer (101) for storing the image information and processing the image information and outputting same to the timing controller (201); a data drive circuit (202) for providing the data signal to a display device, and controlling a display image of the display device; and a power supply management integrated circuit (102) for managing the electric energy of the timing controller (201), the frame buffer (101) and the data drive circuit (202). The frame buffer (101) and the power supply management integrated circuit (102) are integrated on a first integrated circuit (10), and the timing controller (201) and the data drive circuit (202) are integrated on a second integrated circuit (20). The display control circuit and the display apparatus are low in production cost, and can be better adapted to the demands of high-definition resolution of a display device.

Description

一种显示控制电路及显示装置Display control circuit and display device 技术领域Technical field
本发明涉及显示技术领域，特别涉及一种显示控制电路及显示装置。The present invention relates to the field of display technologies, and in particular, to a display control circuit and a display device.
背景技术Background technique
用于显示设备显示控制电路中的时序控制器，帧缓存器是一种必要的存在装置，例如液晶显示屏的过驱动技术便需要应用到所谓的帧缓存器(Frame Buffer)来储存每一帧的图像信息。现行的帧缓存器都是由时序控制器的封装程序整合在时序控制器内的，也即时序控制器的其他部分和帧缓存器是分开生产，而后在经封装程序封装在一起的，封装过程繁杂、成本高。而在高清分辨率电视时代来临的今日，由于图像分辨率日益增加，许多需要利用帧缓存器的算法技术都需要处理巨量的数据，故帧缓存器成本也大幅提高。同时，由于显示设备显示控制电路中的时序控制器、帧缓存器、电源管理集成电路及部分其他功能的电路通常放置在同一块电路主板上，因此所述电路主板体积大，需要放置在所述显示设备特地设置的位置，显示设备的体积也因此变得更大且笨重、成本高。For the timing controller in the display device display control circuit, the frame buffer is a necessary presence device. For example, the overdrive technology of the liquid crystal display needs to be applied to a so-called frame buffer to store each frame. Image information. The current frame buffers are integrated into the timing controller by the timing controller's package program, that is, the other parts of the timing controller and the frame buffer are separately produced, and then packaged together by the packaged program. Complex and costly. Today, in the era of HD resolution TV, due to the increasing resolution of images, many algorithm technologies that need to use frame buffers need to process huge amounts of data, so the cost of frame buffers is also greatly increased. Meanwhile, since the timing controller, the frame buffer, the power management integrated circuit, and some other functions of the display device display control circuit are usually placed on the same circuit board, the circuit board is bulky and needs to be placed in the The position of the display device is specifically set, and the volume of the display device is thus made larger and cumbersome and costly.
发明内容Summary of the invention
针对以上问题，本发明专利目的在于设计了一种显示控制电路及 显示装置，显示控制电路生产成本低，可以更好地适应显示设备高清分辨率的需求。本发明是通过以下技术方案实现的：In view of the above problems, the purpose of the present invention is to design a display control circuit and The display device and the display control circuit have low production cost and can better meet the requirements of the high resolution of the display device. The invention is achieved by the following technical solutions:
一种显示控制电路，包括：A display control circuit comprising:
时序控制器，用来传输数据信号并对所述数据信号进行处理后形成图像信息；a timing controller for transmitting a data signal and processing the data signal to form image information;
帧缓存器，与所述时序控制器电性连接，用来存储所述图像信息并将所述图像信息进行处理后输出至所述时序控制器；a frame buffer electrically connected to the timing controller for storing the image information and processing the image information to be output to the timing controller;
数据驱动电路，与所述时序控制器连接，用来向显示设备提供数据信号，并控制所述显示设备的显示图像；a data driving circuit coupled to the timing controller for providing a data signal to the display device and controlling a display image of the display device;
电源管理集成电路，用以管理所述时序控制器、帧缓存器和数据驱动电路的电能；a power management integrated circuit for managing power of the timing controller, the frame buffer, and the data driving circuit;
所述帧缓存器和所述电源管理集成电路集成整合在第一集成电路上，所述时序控制器和所述数据驱动电路集成整合在第二集成电路上。The frame buffer and the power management integrated circuit are integrated on the first integrated circuit, and the timing controller and the data driving circuit are integrated and integrated on the second integrated circuit.
进一步，本发明所述时序控制器包括数据处理模块，所述数据处理模块用来对所述数据信号进行压缩编码和压缩解码处理。Further, the timing controller of the present invention includes a data processing module, and the data processing module is configured to perform compression coding and compression decoding processing on the data signal.
进一步，本发明所述数据处理模块与所述帧缓存器电性连接。Further, the data processing module of the present invention is electrically connected to the frame buffer.
进一步，本发明所述时序控制器与所述帧缓存器之间的连接走线数量由图像信息压缩率和电源管理集成电路封装大小决定。Further, the number of connection traces between the timing controller and the frame buffer of the present invention is determined by an image information compression ratio and a power management integrated circuit package size.
进一步，本发明所述时序控制器与所述帧缓存器之间的连接走线数量由如下公式决定：Further, the number of connection traces between the timing controller and the frame buffer of the present invention is determined by the following formula:
Figure PCTCN2016081671-appb-000001
Figure PCTCN2016081671-appb-000001
C＝Cs×Ctr，C=C s ×C tr ,
式中Ctr为因帧缓存器传输速率限制之压缩率，Cs为因帧缓存器储存容量限制之压缩率，No为原引线数量，Ns为引线减少后数量，Ms为帧缓存器可储存大小，Fs为每帧之影像大小，Fmo为帧缓存器传输频率，Fra为显示器影像更新频率，δ为帧缓存器是否为双倍资料率，是则为2，否则为1；C为最终图像信息所需压缩率。Where C tr is the compression ratio due to a frame buffer transfer rate limits, C s is the result of the compression rate frame buffer storage capacity limits, N o is the original number of leads, after reduction N s is the lead number, M s is the frame buffer The device can store the size, F s is the image size of each frame, F mo is the frame buffer transmission frequency, F ra is the display image update frequency, δ is the frame buffer is double the data rate, is 2; otherwise 1; C is the compression ratio required for the final image information.
进一步，本发明所述时序控制器与所述帧缓存器之间的连接走线数量少于所述帧缓存器的引脚数量。Further, the number of connection traces between the timing controller and the frame buffer of the present invention is less than the number of pins of the frame buffer.
进一步，本发明所述帧缓存器为双倍速率同步动态随机存储器。Further, the frame buffer of the present invention is a double rate synchronous dynamic random access memory.
本发明还提供一种显示装置，包括显示屏以及所述的显示控制电路，所述显示控制电路电性连接所述显示屏并控制所述显示屏的显示图像。The invention also provides a display device comprising a display screen and the display control circuit, the display control circuit electrically connecting the display screen and controlling a display image of the display screen.
本发明所述显示控制电路由于所述帧缓存器不再需要藉由所述时序控制器的封装程序封装在所述时序控制器中，而是整合在电源管理集成电路的生产过程中，将所述帧缓存器与所述电源管理集成电路整合在同一个集成电路上，因此降低了所述时序控制器的封装成本，也即降低了整个显示控制电路的成本，使之可以更好地适应现有显示设备高清分辨率的需求。The display control circuit of the present invention is integrated in the production process of the power management integrated circuit because the frame buffer is no longer required to be packaged in the timing controller by the package program of the timing controller. The frame buffer is integrated with the power management integrated circuit on the same integrated circuit, thereby reducing the packaging cost of the timing controller, that is, reducing the cost of the entire display control circuit, so that it can better adapt to the present There is a need for display device HD resolution.
附图说明DRAWINGS
以下参照附图对本发明实施例作进一步说明，其中： The embodiments of the present invention are further described below with reference to the accompanying drawings, wherein:
图1是本发明一种显示控制电路的系统构成图。BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a system configuration diagram of a display control circuit of the present invention.
具体实施方式detailed description
下面结合附图和具体实施例对本发明作进一步的详细说明。The invention will be further described in detail below with reference to the drawings and specific embodiments.
本发明提出了一种显示控制电路，请参阅图1，包括：时序控制器201、帧缓存器101、电源管理集成电路102和数据驱动电路202。其中：The present invention provides a display control circuit. Referring to FIG. 1, a timing controller 201, a frame buffer 101, a power management integrated circuit 102, and a data driving circuit 202 are provided. among them:
时序控制器201，用来传输数据信号并对所述数据信号进行处理后形成图像信息；帧缓存器101，与所述时序控制器201电性连接，用来存储所述图像信息并将所述图像信息进行处理后输出至所述时序控制器201；数据驱动电路202，与所述时序控制器201连接，用来向显示设备提供数据信号，并控制所述显示设备的显示图像；电源管理集成电路102，用以管理所述时序控制器201、帧缓存器101和数据驱动电路202的电能。The timing controller 201 is configured to transmit a data signal and process the data signal to form image information. The frame buffer 101 is electrically connected to the timing controller 201 for storing the image information and The image information is processed and output to the timing controller 201; the data driving circuit 202 is connected to the timing controller 201 for providing a data signal to the display device and controlling the display image of the display device; power management integration The circuit 102 is configured to manage power of the timing controller 201, the frame buffer 101, and the data driving circuit 202.
所述帧缓存器101和所述电源管理集成电路102集成整合在第一集成电路10上，所述时序控制器201和所述数据驱动电路202集成整合在第二集成电路20上。The frame buffer 101 and the power management integrated circuit 102 are integrated on the first integrated circuit 10, and the timing controller 201 and the data driving circuit 202 are integrated and integrated on the second integrated circuit 20.
本发明实施例所述显示控制电路中，所述帧缓存器101不再需要由所述时序控制器201的封装程序封装在所述时序控制器201中，而是整合在电源管理集成电路102的生产过程中，将所述帧缓存器101与所述电源管理集成电路102整合在所述第一集成电路10上，降低了所述时序控制器201的封装成本，也即降低了整个显示控制电路的 成本，使之可以更好地适应现有显示设备高清分辨率的需求。同时，由于第一集成电路10体积小，不需要特地设置电路承载基板，可以灵活地设置在应用所述显示控制电路的显示设备的任意位置，有利于提升所述显示设备内部件的规划排布的灵活性，因此能够减小所述显示设备的整体体积、降低成本。In the display control circuit of the embodiment of the present invention, the frame buffer 101 is no longer required to be encapsulated in the timing controller 201 by the package program of the timing controller 201, but integrated in the power management integrated circuit 102. In the production process, the frame buffer 101 and the power management integrated circuit 102 are integrated on the first integrated circuit 10, which reduces the packaging cost of the timing controller 201, that is, reduces the entire display control circuit. of The cost makes it better suited to the HD resolution of existing display devices. At the same time, since the first integrated circuit 10 is small in size, it is not necessary to specifically set the circuit carrying substrate, and can be flexibly disposed at any position of the display device to which the display control circuit is applied, which is advantageous for improving the planning arrangement of the components in the display device. The flexibility makes it possible to reduce the overall size and cost of the display device.
进一步的，由于将所述时序控制器201与所述数据驱动电路202整合在第二集成电路20上，所述第二集成电路20的体积小，也不需要特地设置电路承载基板，可以灵活地设置在应用所述显示控制电路的显示设备的任意位置，有利于提升所述显示设备内部件的规划排布的灵活性，因此能够减小所述显示设备的整体体积、降低成本。例如，所述第一集成电路10可以设置在电视显示系统主板上，或者是放于FPCA上来达到缩小系统体积的目的。Further, since the timing controller 201 and the data driving circuit 202 are integrated on the second integrated circuit 20, the second integrated circuit 20 has a small volume, and does not need to specifically set the circuit carrying substrate, and can be flexibly Providing the arbitrary position of the display device to which the display control circuit is applied is advantageous for improving the flexibility of planning the arrangement of the components in the display device, thereby reducing the overall volume and cost of the display device. For example, the first integrated circuit 10 can be disposed on the main board of the television display system or placed on the FPCA to achieve the purpose of reducing the volume of the system.
本实施例所述显示控制电路由于将所述时序控制器201和所述帧缓存器101分别集成在所述电源管理集成电路102和数据驱动电路202上，并形成体积很小的所述第一集成电路10和所述第二集成电路20，不再需要特地设置电路承载基板，降低了所述显示控制电路的封装成本，同时，由于所述第一集成电路10和第二集成电路20可以放置在应该所述显示控制电路的显示设备上的任意位置，有利于提升所述显示设备内部件的规划排布的灵活性，因此能够减小所述显示设备的整体体积、降低成本。The display control circuit of the embodiment integrates the timing controller 201 and the frame buffer 101 on the power management integrated circuit 102 and the data driving circuit 202, respectively, and forms the first volume having a small volume. The integrated circuit 10 and the second integrated circuit 20 no longer need to specifically set the circuit carrying substrate, which reduces the packaging cost of the display control circuit, and at the same time, since the first integrated circuit 10 and the second integrated circuit 20 can be placed Any position on the display device that should be the display control circuit facilitates the flexibility of planning the arrangement of the components within the display device, thereby reducing the overall size and cost of the display device.
在本实施例中，所述时序控制器201与所述帧缓存器101之间传输数据信号。所述时序控制器201包括数据处理模块，用以对所述信 号进行压缩编码和压缩解码，所述数据处理模块电连接所述帧缓存器101。所述数据处理模块对所述信号进行压缩编码后形成所述图像信息传送进所述帧缓存器101，所述帧缓存器101存储所述图像信息，并将所述图像信息应用在特定算法中处理后输出至所述数据处理模块，被处理后的图像信息在所述数据处理模块被压缩解码后进入下一步数据处理。In the embodiment, the timing controller 201 and the frame buffer 101 transmit data signals. The timing controller 201 includes a data processing module for the letter The number is subjected to compression coding and compression decoding, and the data processing module is electrically connected to the frame buffer 101. The data processing module compresses and encodes the signal to form the image information and transmits the image information into the frame buffer 101. The frame buffer 101 stores the image information, and applies the image information to a specific algorithm. After processing, the image data is output to the data processing module, and the processed image information is compressed and decoded by the data processing module to enter the next data processing.
进一步的，所述时序控制器201与所述帧缓存器101之间的走线数量少于所述帧缓存器101的引脚数量。所述走线数量符合如下公式：Further, the number of traces between the timing controller 201 and the frame buffer 101 is less than the number of pins of the frame buffer 101. The number of traces conforms to the following formula:
Figure PCTCN2016081671-appb-000002
Figure PCTCN2016081671-appb-000002
式中Ctr、Cs压缩率(Ctr为因帧缓存器传输速率限制之压缩率；Cs为因帧缓存器储存容量限制之压缩率)，No为原引线数量，Ns为引线减少后数量，Ms为帧缓存器可储存大小，Fs为每帧之影像大小，Fmo为为帧缓存器传输频率、Fra为为显示器影像更新频率、δ为帧缓存器是否为双倍资料率，是则为2，否则为1。若Ctr和Cs计算值大于1，则Ctr和Cs＝1(即不需压缩)，最终图像信息所需压缩率为Where C tr, C s compression ratio (C tr is due to limitations in the frame buffer the transmission rate of the compression ratio; C s as a result of the frame buffer storage compression rate capacity limits), N o is the number of primary leads, N s is the lead Reduce the number, M s is the frame buffer can store the size, F s is the image size of each frame, F mo is the frame buffer transmission frequency, F ra is the display image update frequency, δ is the frame buffer is double The data rate is 2, otherwise it is 1. If the calculated values of C tr and C s are greater than 1, then C tr and C s =1 (ie, no compression is required), and the required compression ratio of the final image information is
C＝Cs×Ctr。C=C s ×C tr .
以下为实施例中数据带入所需的压缩率：假设No为16，Ns为8，Ms＝16Mbit，Fs＝1366x768x24bits，Fra＝60Hz，Fmo＝133MHz，δ＝1，则The following is the compression ratio required for the data in the embodiment: assuming N o is 16, N s is 8, Ms = 16 Mbit, F s = 1366 x 768 x 24 bits, F ra = 60 Hz, F mo = 133 MHz, δ = 1, then
Figure PCTCN2016081671-appb-000003
Figure PCTCN2016081671-appb-000003
Figure PCTCN2016081671-appb-000004
Figure PCTCN2016081671-appb-000004
C＝Cs×Ctr＝73.8％×45.1％＝33.32％C=C s ×C tr =73.8%×45.1%=33.32%
在本实施例中，所述显示控制电路严格控制所述时序控制器201和所述帧缓存器101之间的走线数量，仅保留可以满足应用所述显示控制电路的显示设备进行显示所需要的数据量的最少走线。可以理解的，本实施例所述显示控制电路通过适当地压缩图像信息内容以达到降低所述时序控制器201和所述帧缓存器101之间的走线数量的目的，并简化了所述显示控制电路的线路排布，进一步降低了所述显示控制电路的成本。In this embodiment, the display control circuit strictly controls the number of traces between the timing controller 201 and the frame buffer 101, and only needs to retain the display device that can satisfy the application of the display control circuit for display. The minimum amount of data is traced. It can be understood that the display control circuit of the embodiment achieves the purpose of reducing the number of traces between the timing controller 201 and the frame buffer 101 by appropriately compressing the image information content, and simplifies the display. The circuit arrangement of the control circuit further reduces the cost of the display control circuit.
在本实施例中，所述帧缓存器101可以为双倍速率同步动态随机存储器(Double Data Rate SDRAM)或闪存或其他可以进行数据存储的存储器。优选的，当所述帧缓存器101为双倍速率同步动态随机存储器时，可降低压缩率要求。In this embodiment, the frame buffer 101 may be a double rate synchronous dynamic random access memory (Double Data Rate SDRAM) or a flash memory or other memory that can perform data storage. Preferably, when the frame buffer 101 is a double rate synchronous dynamic random access memory, the compression ratio requirement can be reduced.
本发明实施例还提供一种显示设备，所述显示设备包括采用上述实施例所描述的技术方案形成的显示控制电路和显示屏，所述显示控制电路电连接至所述显示屏并控制所述显示屏的显示图像。An embodiment of the present invention further provides a display device including a display control circuit and a display screen formed by using the technical solution described in the foregoing embodiments, the display control circuit being electrically connected to the display screen and controlling the The display image of the display.
可以理解的，由于所述显示设备所采用的显示控制电路的所述第一集成电路10和第二集成电路20可以放置在应该所述显示控制电路的显示设备上的任意位置，有利于提升所述显示设备内部件的规划排布的灵活性，因此能够减小所述显示设备的整体体积、降低成本。It can be understood that, since the first integrated circuit 10 and the second integrated circuit 20 of the display control circuit used by the display device can be placed at any position on the display device that should be the display control circuit, it is advantageous to promote the The flexibility of the planned arrangement of the components within the device is shown, thereby reducing the overall size and cost of the display device.
以上所述本发明的具体实施方式，并不构成对本发明保护范围的限定。任何根据本发明的技术构思所做出的各种其他相应的改变与变 形，均应包含在本发明权利要求的保护范围内。 The specific embodiments of the invention described above are not intended to limit the scope of the invention. Any other various changes and changes made in accordance with the technical idea of the present invention The form should be included in the scope of protection of the claims of the present invention.

Claims (8)

  1. 一种显示控制电路，其特征在于，包括：A display control circuit, comprising:
    时序控制器，用来传输数据信号并对所述数据信号进行处理后形成图像信息；a timing controller for transmitting a data signal and processing the data signal to form image information;
    帧缓存器，与所述时序控制器电性连接，用来存储所述图像信息并将所述图像信息进行处理后输出至所述时序控制器；a frame buffer electrically connected to the timing controller for storing the image information and processing the image information to be output to the timing controller;
    数据驱动电路，与所述时序控制器连接，用来向显示设备提供数据信号，并控制所述显示设备的显示图像；a data driving circuit coupled to the timing controller for providing a data signal to the display device and controlling a display image of the display device;
    电源管理集成电路，用以管理所述时序控制器、帧缓存器和数据驱动电路的电能；a power management integrated circuit for managing power of the timing controller, the frame buffer, and the data driving circuit;
    所述帧缓存器和所述电源管理集成电路集成整合在第一集成电路上，所述时序控制器和所述数据驱动电路集成整合在第二集成电路上。The frame buffer and the power management integrated circuit are integrated on the first integrated circuit, and the timing controller and the data driving circuit are integrated and integrated on the second integrated circuit.
  2. 根据权利要求1所述的一种显示控制电路，其特征在于，所述时序控制器包括数据处理模块，所述数据处理模块用来对所述数据信号进行压缩编码和压缩解码处理。A display control circuit according to claim 1, wherein said timing controller comprises a data processing module, said data processing module for performing compression encoding and compression decoding processing on said data signal.
  3. 根据权利要求2所述的一种显示控制电路，其特征在于，所述数据处理模块与所述帧缓存器电性连接。The display control circuit according to claim 2, wherein the data processing module is electrically connected to the frame buffer.
  4. 根据权利要求1所述的一种显示控制电路，其特征在于，所述时序控制器与所述帧缓存器之间的连接走线数量由图像信息压缩率和电源管理集成电路封装大小决定。The display control circuit according to claim 1, wherein the number of connection traces between the timing controller and the frame buffer is determined by an image information compression ratio and a power management integrated circuit package size.
  5. 根据权利要求4所述的一种显示控制电路，其特征在于，所述时序控制器与所述帧缓存器之间的连接走线数量由如下公式 决定：A display control circuit according to claim 4, wherein the number of connection traces between said timing controller and said frame buffer is as follows Decided:
    Figure PCTCN2016081671-appb-100001
    Figure PCTCN2016081671-appb-100001
    C＝Cs×Ctr，C=C s ×C tr ,
    式中Ctr为因帧缓存器传输速率限制之压缩率，Cs为因帧缓存器储存容量限制之压缩率，No为原引线数量，Ns为引线减少后数量，Ms为帧缓存器可储存大小，Fs为每帧之影像大小，Fmo为帧缓存器传输频率，Fra为显示器影像更新频率，δ为帧缓存器是否为双倍资料率，是则为2，否则为1；C为最终图像信息所需压缩率。Where C tr is the compression ratio due to a frame buffer transfer rate limits, C s is the result of the compression rate frame buffer storage capacity limits, N o is the original number of leads, after reduction N s is the lead number, M s is the frame buffer The device can store the size, F s is the image size of each frame, F mo is the frame buffer transmission frequency, F ra is the display image update frequency, δ is the frame buffer is double the data rate, is 2; otherwise 1; C is the compression ratio required for the final image information.
  6. 根据权利要求4所述的一种显示控制电路，其特征在于，所述时序控制器与所述帧缓存器之间的连接走线数量少于所述帧缓存器的引脚数量。The display control circuit according to claim 4, wherein the number of connection traces between the timing controller and the frame buffer is less than the number of pins of the frame buffer.
  7. 根据权利要求4所述的一种显示控制电路，其特征在于，所述帧缓存器为双倍速率同步动态随机存储器。A display control circuit according to claim 4, wherein said frame buffer is a double rate synchronous dynamic random access memory.
  8. 一种显示装置，其特征在于，包括显示屏以及权利要求1-7中任一项所述的显示控制电路，所述显示控制电路电性连接所述显示屏并控制所述显示屏的显示图像。 A display device, comprising: a display screen and the display control circuit according to any one of claims 1 to 7, wherein the display control circuit is electrically connected to the display screen and controls a display image of the display screen .
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