CN204538023U - A kind of memory - Google Patents
A kind of memory Download PDFInfo
- Publication number
- CN204538023U CN204538023U CN201520276582.6U CN201520276582U CN204538023U CN 204538023 U CN204538023 U CN 204538023U CN 201520276582 U CN201520276582 U CN 201520276582U CN 204538023 U CN204538023 U CN 204538023U
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- China
- Prior art keywords
- memory
- lead
- insulating substrate
- passive storage
- control chip
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Abstract
The utility model relates to memory technology.The utility model solves the monocrystalline silicon substrate that the existing memory comprising passive storage circuit consumes larger area, and composite lase bafer read-only memory makes the problem of difficulty, provide a kind of memory, its technical scheme can be summarized as: a kind of memory, comprise insulating substrate, passive storage matrix circuit, lead and at least one control chip, passive storage matrix circuit and lead are surperficial on an insulating substrate, control chip is connected with passive storage matrix circuit by lead, and described control chip upside-down mounting is surperficial on an insulating substrate.The beneficial effects of the utility model are, manufacturing than being easier to, being applicable to read-only memory.
Description
Technical field
The utility model relates to memory technology.
Background technology
Common memory, as included the random asccess memory of Src StUnit circuit, read-only memory and flash memory, comprise the Memister of passive storage circuit, the memories such as phase transition storage, be manufactured on bulk single-crystal silicon chip, its storage unit circuit, drive circuit, peripheral circuit etc. are all positioned on a monocrystalline silicon substrate.If Chinese Patent Application No. is a kind of mask ROM disclosed in " 92109280.6 ", Chinese Patent Application No. for the multi-layer cross point resistive memory device disclosed in " 201010175802.8 " and manufacture method etc. be all that circuit is integrated on a monocrystalline silicon substrate, although so more easily make, but will consume the monocrystalline silicon substrate of larger area, cost is higher.
And as Chinese Patent Application No. be the composite lase bafer read-only memory disclosed in " 97107683.9 " and manufacture method thereof, it is the memory comprising passive storage circuit, structure as shown in Figure 1, sectional view as shown in Figure 2, composite lase bafer read-only memory, there is the first monocrystalline silicon substrate 5, second monocrystalline silicon substrate 5 and insulating substrate 4, and the word line driving circuit be positioned on the first monocrystalline silicon substrate 5 and wordline drive peripheral circuit (the first circuit unit 6), be positioned at the bit line drive circuit on the second monocrystalline silicon substrate 5 and bit-line drive peripheral circuit (second circuit unit 6), be positioned at the passive storage matrix circuit 1 on described insulating substrate 4, two adjacent side of described insulating substrate 4 are combined with a side of described first monocrystalline silicon substrate 5 and a side of described second monocrystalline silicon substrate 5 respectively, word line driving circuit and bit line drive circuit (circuit unit 6) are by the metal word lines in lead 2 respectively connected with passive memory cell matrix circuit 1 and metal bit line.The wordline control section that first monocrystalline silicon substrate 5, word line driving circuit and wordline drive peripheral circuit (the first circuit unit 6) to form can be described as the first control chip, and the bit line control section that the second monocrystalline silicon substrate 5, bit line drive circuit and bit-line drive peripheral circuit (second circuit unit 6) form can be described as the second control chip.Although do not take monocrystalline silicon substrate below its passive storage matrix circuit, but owing to needing two of insulating substrate 4 adjacent side to be combined with a side of described first monocrystalline silicon substrate 5 and a side of described second monocrystalline silicon substrate 5 respectively, and due to after being divided into the first monocrystalline silicon substrate 5 and the second monocrystalline silicon substrate 5, each monocrystalline silicon substrate 5 is the substrate of strip, its side is narrower, the side of insulating substrate 4 is also narrower relative to its top and bottom, is combined the side of monocrystalline silicon substrate 5 make comparatively difficulty with the side of insulating substrate 4.
Utility model content
The purpose of this utility model to overcome the monocrystalline silicon substrate that the memory comprising passive storage circuit consumes larger area, and composite lase bafer read-only memory makes the shortcoming of difficulty, provides a kind of memory.
The utility model solves its technical problem, the technical scheme adopted is, a kind of memory, comprise insulating substrate, passive storage matrix circuit, lead and at least one control chip, passive storage matrix circuit and lead are surperficial on an insulating substrate, control chip is connected with passive storage matrix circuit by lead, it is characterized in that, described control chip upside-down mounting is surperficial on an insulating substrate.
Concrete, described control chip comprises monocrystalline silicon substrate and circuit unit, and described circuit unit is arranged on monocrystalline silicon substrate, and circuit unit is connected with passive storage matrix circuit by lead.
Further, described control chip upside-down mounting refers at insulating material substrate upper surface: the circuit unit of control chip contacts with insulating substrate upper surface.
Concrete, described passive storage matrix circuit comprises metal word lines, metal bit line and the electric conducting material between metal word lines and metal bit line, and described metal word lines and metal bit line are connected with lead respectively.
Further, described lead is metal lead wire row.
Concrete, described insulating substrate is plastic substrate.
Further, described insulating substrate is glass substrate.
In the utility model scheme, because passive storage matrix circuit and passive storage matrix circuit extended line are at insulating material substrate upper surface, do not take monocrystalline silicon substrate, it can save a large amount of monocrystalline silicon substrate, control chip upside-down mounting, at insulating material substrate upper surface, manufactures than being easier to.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing composite lase bafer read-only memory.
Fig. 2 is the schematic cross-section of existing composite lase bafer read-only memory.
Fig. 3 is the structural representation of memory in the utility model embodiment.
Fig. 4 is the schematic cross-section of memory in the utility model embodiment.
Fig. 5 is the structural representation of memory in another embodiment of the utility model.
Wherein, 1 is passive storage matrix circuit, and 2 is lead, and 3 is control chip, and 4 is insulating substrate, and 5 is monocrystalline silicon substrate, and 6 is circuit unit.
Embodiment
Below in conjunction with embodiment and accompanying drawing, describe the technical solution of the utility model in detail.
Memory of the present utility model, be made up of at least one control chip 3 and the passive storage matrix circuit 1 be positioned on insulating substrate 4 and lead 2, be unlike the prior art, control chip 3 upside-down mounting is on insulating substrate 4 and be connected with passive storage matrix circuit 1 by lead 2.
Embodiment
The structural representation of the memory of the utility model embodiment is as Fig. 3, and its schematic cross-section is as Fig. 4.This memory is made up of two control chips 3 and the passive storage matrix circuit 1 be positioned on insulating substrate 4 and lead 2.
Same as the prior art, passive storage matrix circuit 1 and lead 2 are positioned on insulating substrate 4, passive storage matrix circuit 1 comprises metal word lines, metal bit line and the electric conducting material between metal word lines and metal bit line, metal word lines and metal bit line are connected with lead 2 respectively, control chip 3 comprises monocrystalline silicon substrate 5 and circuit unit 6, circuit unit 6 is arranged on monocrystalline silicon substrate 5, and circuit unit 6 is connected with passive storage matrix circuit 1 by lead 2.Here circuit unit 6 can comprise word line driving circuit and/or bit line drive circuit and corresponding peripheral circuit etc., and lead 2 can be arranged for metal lead wire, and insulating substrate 4 is plastic substrate or glass substrate.
Be unlike the prior art, control chip 3 upside-down mounting is at insulating substrate 4 upper surface, namely circuit unit 6 contacts with insulating substrate 4 upper surface, that is, if with insulating substrate 4 end of for, then insulating substrate 4 is in bottom, and circuit unit 6 is at insulating substrate 4 upper surface, be monocrystalline silicon substrate 5 above circuit unit 6, circuit unit 6 is connected with passive storage matrix circuit 1 by lead 2.
Certainly, control chip 3 also can be one, its structural representation can as shown in Figure 5 but be not limited to the shape shown in Fig. 5 and type-setting mode, only need to reach passive storage matrix circuit 1 and lead 2 is positioned on insulating substrate 4, control chip 3 upside-down mounting at insulating substrate 4 upper surface, and is connected with passive storage matrix circuit 1 by lead 2.
Because the method making passive storage matrix circuit 1 and making control chip 3 all belongs to prior art, therefore no longer describe in detail herein.
Because the utility model makes passive storage matrix circuit 1 on insulating substrate 4, monocrystalline silicon substrate 5 makes control chip 3, finally the control chip 3 completed is fixed on insulating substrate 4, doing so avoids the narrower side of the narrower side of monocrystalline silicon substrate 5 in prior art in control chip 3 and insulating substrate 4 in conjunction with relative troublesome problem.
Claims (6)
1. a memory, comprise insulating substrate, passive storage matrix circuit, lead and at least one control chip, passive storage matrix circuit and lead are surperficial on an insulating substrate, control chip is connected with passive storage matrix circuit by lead, it is characterized in that, described control chip upside-down mounting is surperficial on an insulating substrate.
2. a kind of memory as claimed in claim 1, is characterized in that, described control chip comprises monocrystalline silicon substrate and circuit unit, and described circuit unit is arranged on monocrystalline silicon substrate, and circuit unit is connected with passive storage matrix circuit by lead.
3. a kind of memory as claimed in claim 1, it is characterized in that, described passive storage matrix circuit comprises metal word lines, metal bit line and the electric conducting material between metal word lines and metal bit line, and described metal word lines and metal bit line are connected with lead respectively.
4. a kind of memory as claimed in claim 1, is characterized in that, described lead is metal lead wire row.
5. a kind of memory as claimed in claim 1 or 2 or 3 or 4, it is characterized in that, described insulating substrate is plastic substrate.
6. a kind of memory as claimed in claim 1 or 2 or 3 or 4, it is characterized in that, described insulating substrate is glass substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520276582.6U CN204538023U (en) | 2015-04-30 | 2015-04-30 | A kind of memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520276582.6U CN204538023U (en) | 2015-04-30 | 2015-04-30 | A kind of memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204538023U true CN204538023U (en) | 2015-08-05 |
Family
ID=53751993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520276582.6U Withdrawn - After Issue CN204538023U (en) | 2015-04-30 | 2015-04-30 | A kind of memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204538023U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104810361A (en) * | 2015-04-30 | 2015-07-29 | 于翔 | Storer |
-
2015
- 2015-04-30 CN CN201520276582.6U patent/CN204538023U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104810361A (en) * | 2015-04-30 | 2015-07-29 | 于翔 | Storer |
| CN104810361B (en) * | 2015-04-30 | 2019-01-29 | 于翔 | A kind of memory |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20150805 Effective date of abandoning: 20190129 |