CN204536699U - A kind of array base palte, display panel and display device - Google Patents
A kind of array base palte, display panel and display device Download PDFInfo
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- CN204536699U CN204536699U CN201520269956.1U CN201520269956U CN204536699U CN 204536699 U CN204536699 U CN 204536699U CN 201520269956 U CN201520269956 U CN 201520269956U CN 204536699 U CN204536699 U CN 204536699U
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Abstract
The utility model provides a kind of array base palte, display panel and display device.This array base palte comprises multiple pixel cells, many first grid lines and the second grid line be parallel to each other of the arrangement in matrix, many the first data lines and the second data line be parallel to each other, often row pixel cell is all divided into first group of pixel cell and second group of pixel cell, first group of pixel cell correspondence connects first grid line, and second group of pixel cell correspondence connects second grid line; The row pixel cell connecting the first grid line connects first data line with the row pixel cell correspondence being connected the second grid line, and many first grid lines and many second grid lines connect one to one with many second data lines respectively.This array base palte provides sweep signal by adopting a part of data line for pixel cell, avoids and lays scan signal line in one group of opposite side frame region of array base palte, enable array base palte realize zero frame design at one group of opposite side edge.
Description
Technical field
The utility model relates to display technique field, particularly, relates to a kind of array base palte, display panel and display device.
Background technology
Along with the development of display technique, the requirement of display device to frame of high-quality is more and more narrow, and high-end display sets all pursues ultra-narrow frame even Rimless.
As shown in Figure 1, driving chip 10 is arranged on the side non-display area of display panel to display panel in conventional display device (as mobile phone), and driving chip 10 is for providing scanning drive signal and data drive signal to the pixel being arranged on viewing area.The frame non-display area of the display panel left and right sides needs to lay the scan signal line 15 for transmitting scanning drive signal, and this makes the left and right sides of display panel cannot realize ultra-narrow frame or zero frame.
In addition, some display panel also needs the frame non-display area in its left and right sides to lay some control chips exported for gated sweep drive singal, left and right sides frame non-display area as display panel is laid with clock control chip, in order to the real-time output of gated sweep signal, to complete the driving of whole display panel.This makes the left and right sides of display panel cannot realize ultra-narrow frame or zero frame equally.
Utility model content
The utility model, for the above-mentioned technical matters existed in prior art, provides a kind of array base palte, display panel and display device.This array base palte provides sweep signal by adopting a part of data line for pixel cell, avoids and lays scan signal line in one group of opposite side frame region of array base palte, enable array base palte realize zero frame design at one group of opposite side edge.
The utility model provides a kind of array base palte, comprise multiple pixel cells, many first grid lines and the second grid line be parallel to each other of the arrangement in matrix, many the first data lines and the second data line be parallel to each other, described pixel cell of often going all is divided into first group of pixel cell and second group of pixel cell, described first group of pixel cell correspondence connects described first grid line, and described second group of pixel cell correspondence connects described second grid line; The described pixel cell of row connecting described first grid line connects described first data line with the described pixel cell correspondence of row being connected described second grid line, and described second data line connects one to one with many respectively for many described first grid lines and many described second grid lines; Described first data line is used for providing data-signal for described pixel cell, and described second data line is used for providing sweep signal for described pixel cell.
Preferably, described first group of pixel cell comprises pixel cell described in the odd number of often going in described pixel cell, and described second group of pixel cell comprises pixel cell described in the even number of often going in described pixel cell;
Adjacent odd column is connected described first data line with pixel cell correspondence described in even column.
Preferably, described first grid line and described second grid line are all parallel to described pixel cell and are expert at, and described first data line and described second data line are all parallel to described pixel cell column;
Multiple described pixel cell, many described first grid lines and described second grid line and many described first data lines and described second data line are all positioned at viewing area, scan drive cell and data drive unit is also provided with in the periphery, side along described first data line and described second data line bearing of trend of described viewing area, described first data line connects described data drive unit, and described second data line connects described scan drive cell.
Preferably, described data drive unit and described scan drive cell on a single die integrated.
Preferably, often go in described pixel cell, corresponding connect pixel cell described in odd number described first grid line and corresponding described second grid line being connected pixel cell described in even number lay respectively at every capable described pixel cell above and below its column direction;
Second data line described in first data line described in every bar and every bar is respectively described in adjacent odd column and even column between pixel cell, and described first data line and the interlaced distribution of described second data line;
Described in every bar, the second data line correspondence connects described first grid line or described second grid line.
Preferably, described pixel cell comprises transistor and pixel electrode, corresponding connect described first data line odd column and even column described in the described transistor of pixel cell near described first data line arrangement.
Preferably, the drain electrode of described transistor connects described pixel electrode;
Often go in described pixel cell, the described transistor of pixel cell described in odd number is positioned at the upper right corner of close described first data line of pixel electrode described in it, and the described transistor of pixel cell described in even number is positioned at the lower left corner of pixel electrode described in it near described first data line;
The grid of the described transistor of pixel cell described in odd number all connects described first grid line; The grid of the described transistor of pixel cell described in even number all connects described second grid line;
Be positioned at the odd number of the first data line both sides described in every bar and be all connected this described first data line with the source electrode of the described transistor of pixel cell described in even number.
Preferably, the drain electrode of described transistor connects described pixel electrode;
Often go in described pixel cell, the described transistor of pixel cell described in odd number is positioned at the lower right corner of close described first data line of pixel electrode described in it, and the described transistor of pixel cell described in even number is positioned at the upper left corner of pixel electrode described in it near described first data line;
The grid of the described transistor of pixel cell described in even number all connects described first grid line; The grid of the described transistor of pixel cell described in odd number all connects described second grid line;
Be positioned at the odd number of the first data line both sides described in every bar and be all connected this described first data line with the source electrode of the described transistor of pixel cell described in even number.
Preferably, described first grid line and described second grid line are arranged with layer, and described second data line bit is above or below described first grid line and described second grid line; Described second data line and be provided with insulation course between described first grid line and described second grid line;
Offer the first via hole with the corresponding region, folded region of covering mutually of described second data line and described first grid line one to one in described insulation course, described second data line and described first grid line are connected one to one by described first via hole;
Offer the second via hole with the corresponding region, folded region of covering mutually of described second data line and described second grid line one to one in described insulation course, described second data line and described second grid line are connected one to one by described second via hole.
The utility model also provides a kind of display panel, comprises above-mentioned array base palte.
The utility model also provides a kind of display device, comprises above-mentioned display panel.
The beneficial effects of the utility model: array base palte provided by the utility model, sweep signal is provided for pixel cell by adopting a part of data line, make this array base palte originally for laying the relative both sides frame non-display area of scan signal line without the need to laying the scan signal line for transmitting scanning drive signal again, thus the one group of opposite side frame area routing avoided at array base palte, and then array base palte is enable to realize zero frame design at one group of opposite side edge.Meanwhile, because this array base palte adopts a part of data line to provide sweep signal for pixel cell, without the need to arranging the scan signal line of transmission scanning drive signal more in addition, thus the cost of this array base palte is reduced.
Display panel provided by the utility model, by adopting above-mentioned array base palte, making this display panel achieve zero frame of relative both sides, also reducing the cost of manufacture of this display panel simultaneously.
Display device provided by the utility model, by adopting above-mentioned display panel, not only achieving relative both sides zero frame of this display device, but also reducing the cost of manufacture of this display device.
Accompanying drawing explanation
Fig. 1 is the schematic wiring diagram in prior art on display panel;
Fig. 2 is the structure vertical view of array base palte in the utility model embodiment 1;
Fig. 3 is the connection diagram of the second data line and the first grid line and the second grid line in Fig. 2.
Description of reference numerals wherein:
1. pixel cell; 11. first groups of pixel cells; 12. second groups of pixel cells; 13. transistors; 14. pixel electrodes; 2. the first grid line; 3. the second grid line; 4. the first data line; 5. the second data line; 6. scan drive cell; 7. data drive unit; 8. the first via hole; 9. the second via hole; 10. driving chip; 15. scan signal lines.
Embodiment
For making those skilled in the art understand the technical solution of the utility model better, below in conjunction with the drawings and specific embodiments, a kind of array base palte provided by the utility model, display panel and display device are described in further detail.
Embodiment 1:
The present embodiment provides a kind of array base palte, as shown in Figure 2, comprise multiple pixel cells 1, many first grid line 2 and second grid lines 3 be parallel to each other of the arrangement in matrix, many the first data line 4 and the second data lines 5 be parallel to each other, often row pixel cell 1 is all divided into first group of pixel cell 11 and second group of pixel cell 12, first group of pixel cell 11 correspondence connects first grid line 2, second group of pixel cell 12 correspondence and connects second grid line 3; The row pixel cell 1 connecting the first grid line 2 connects first data line 4 with row pixel cell 1 correspondence being connected the second grid line 3, and many first grid lines 2 and many second grid lines 3 connect one to one with many second data lines 5 respectively; First data line 4 is for providing data-signal for pixel cell 1, and the second data line 5 is for providing sweep signal for pixel cell 1.
Sweep signal is provided for pixel cell 1 by adopting a part of data line (i.e. the second data line 5), make this array base palte originally for laying the relative both sides frame non-display area of scan signal line without the need to laying the scan signal line for transmitting scanning drive signal again, thus the one group of opposite side frame area routing avoided at array base palte, and then array base palte is enable to realize zero frame design at one group of opposite side edge.Meanwhile, because this array base palte adopts the second data line 5 to provide sweep signal for pixel cell 1, without the need to arranging the scan signal line of transmission scanning drive signal more in addition, thus the cost of this array base palte is reduced.
In the present embodiment, first group of pixel cell 11 odd number of pixels unit 1, second group of pixel cell 12 comprised in every row pixel cell 1 comprises the even number pixel cell 1 in every row pixel cell 1; Adjacent odd column is connected first data line 4 with even column pixels unit 1 correspondence.
Wherein, the first grid line 2 and the second grid line 3 are all parallel to pixel cell 1 and are expert at, and the first data line 4 and the second data line 5 are all parallel to pixel cell 1 column; Multiple pixel cell 1, many first grid lines 2 and the second grid line 3 and many first data lines 4 and the second data line 5 are all positioned at viewing area, scan drive cell 6 and data drive unit 7 is also provided with in the periphery, side along the first data line 4 and the second data line 5 bearing of trend of viewing area, first data line 4 connection data driver element 7, second data line 5 connects scan drive cell 6.Setting like this, can make this array base palte along pixel cell 1 left and right sides frame non-display area in the row direction without the need to laying the scan signal line for transmitting scanning drive signal again, thus avoid array base palte along pixel cell 1 left and right sides frame non-display area wiring in the row direction, and then enable array base palte realize the left and right sides zero frame.Meanwhile, relative with the side arranging scan drive cell 6 and data drive unit 7 on array base palte opposite side also can realize zero frame.
In the present embodiment, data drive unit 7 and scan drive cell 6 on a single die integrated.Setting like this, can reduce the floor area of data drive unit 7 and scan drive cell 6 greatly, thus enables a side frame non-display area of the array base palte of setting data driver element 7 and scan drive cell 6 make narrower, realizes ultra-narrow frame.
In the present embodiment, often in row pixel cell 1, corresponding connect odd number of pixels unit 1 first grid line 2 and corresponding second grid line 3 being connected even number pixel cell 1 lay respectively at every row pixel cell 1 above and below its column direction; Every bar first data line 4 and every bar second data line 5 are respectively between adjacent odd column and even column pixels unit 1, and the first data line 4 and the interlaced distribution of the second data line 5; Every bar second data line 5 correspondence connects one first grid line 2 or the second grid line 3.Setting like this, scanning drive signal is enable to be transferred on the first grid line 2 and the second grid line 3 by a part of data line (i.e. the second data line 5), thus make this array base palte without the need to laying the scan signal line for transmitting scanning drive signal more in addition, and then the frame non-display area of array base palte originally for laying scan signal line is enable to realize zero frame.
In the present embodiment, pixel cell 1 comprises transistor 13 and pixel electrode 14, and the corresponding connection odd column of first data line 4 and the transistor 13 of even column pixels unit 1 are arranged near the first data line 4.Setting like this, can make array base palte be more prone to preparation.
Wherein, the drain electrode of transistor 13 connects pixel electrode 14; Often in row pixel cell 1, the transistor 13 of odd number of pixels unit 1 is positioned at the upper right corner near the first data line 4 of its pixel electrode 14, and the transistor 13 of even number pixel cell 1 is positioned at the lower left corner of its pixel electrode 14 near the first data line 4; The grid of the transistor 13 of odd number of pixels unit 1 all connects the first grid line 2; The grid of the transistor 13 of even number pixel cell 1 all connects the second grid line 3; The odd number being positioned at every bar first data line 4 both sides is all connected this first data line 4 with the source electrode of the transistor 13 of even number pixel cell 1.Setting like this, can make the data line of half by the scan signal line making transmission scanning drive signal of converting, thus make scan signal line without the need to laying in addition again, and then achieve zero frame of array base palte opposite side.
In the present embodiment, as shown in Figure 3, the first grid line 2 and the second grid line 3 are arranged with layer, and the second data line 5 is positioned at the top of the first grid line 2 and the second grid line 3; Second data line 5 and be provided with insulation course between the first grid line 2 and the second grid line 3; The first via hole 8, second data line 5 is offered and the first grid line 2 is connected one to one by the first via hole 8 with the corresponding region, folded region of covering mutually of the second data line 5 one to one and the first grid line 2 in insulation course; Namely every bar second data line 5 correspondence connects first grid line 2, this second data line 5 and this first grid line 2 mutually intersect and cover folded region and only have one, and this second data line 5 and this first grid line 2 are covered folded region and are connected by the first via hole 8 mutually intersecting.The second via hole 9, second data line 5 is offered and the second grid line 3 is connected one to one by the second via hole 9 with the corresponding region, folded region of covering mutually of the second data line 5 one to one and the second grid line 3 in insulation course; Namely every bar second data line 5 correspondence connects second grid line 3, this second data line 5 and this second grid line 3 mutually intersect and cover folded region and only have one, and this second data line 5 and this second grid line 3 are covered folded region and are connected by the second via hole 9 mutually intersecting.
It should be noted that, the second data line 5 also can be positioned at the below of the first grid line 2 and the second grid line 3.
Embodiment 2:
The present embodiment provides a kind of array base palte, and as different from Example 1, the drain electrode of transistor connects pixel electrode; In every brief biography of a deceased person pixel cell, the transistor of odd number of pixels unit is positioned at the lower right corner near the first data line of its pixel electrode, and the transistor of even number pixel cell is positioned at the upper left corner of its pixel electrode near the first data line; The grid of the transistor of even number pixel cell all connects the first grid line; The grid of the transistor of odd number of pixels unit all connects the second grid line; Be positioned at every odd number of bar first data line both sides and be all connected this first data line with the source electrode of the transistor of even number pixel cell.
Setting like this, can make the data line of half by the scan signal line making transmission scanning drive signal of converting, thus make scan signal line without the need to laying in addition again, and then achieve zero frame of array base palte opposite side.
In the present embodiment, other structures of array base palte are in the same manner as in Example 1, repeat no more herein.
The array base palte that the beneficial effect of embodiment 1-2: embodiment 1-2 provides, sweep signal is provided for pixel cell by adopting a part of data line, make this array base palte originally for laying the relative both sides frame non-display area of scan signal line without the need to laying the scan signal line for transmitting scanning drive signal again, thus the one group of opposite side frame area routing avoided at array base palte, and then array base palte is enable to realize zero frame design at one group of opposite side edge.Meanwhile, because this array base palte adopts a part of data line to provide sweep signal for pixel cell, without the need to arranging the scan signal line of transmission scanning drive signal more in addition, thus the cost of this array base palte is reduced.
Embodiment 3:
The present embodiment provides a kind of display panel, comprises the array base palte of embodiment 1-2 in any one.
By adopting the array base palte of embodiment 1-2 in any one, making this display panel achieve zero frame of relative both sides, also reducing the cost of manufacture of this display panel simultaneously.
Embodiment 4:
The present embodiment provides a kind of display device, comprises the display panel in embodiment 3.
By adopting the display panel in embodiment 3, not only achieving relative both sides zero frame of this display device, but also reducing the cost of manufacture of this display device.
Display device provided by the utility model can be, any product or parts with Presentation Function such as liquid crystal panel, LCD TV, display, mobile phone, navigating instrument.
Be understandable that, the illustrative embodiments that above embodiment is only used to principle of the present utility model is described and adopts, but the utility model is not limited thereto.For those skilled in the art, when not departing from spirit of the present utility model and essence, can make various modification and improvement, these modification and improvement are also considered as protection domain of the present utility model.
Claims (11)
1. an array base palte, comprise multiple pixel cells, many first grid lines and the second grid line be parallel to each other of the arrangement in matrix, many the first data lines and the second data line be parallel to each other, it is characterized in that, described pixel cell of often going all is divided into first group of pixel cell and second group of pixel cell, described first group of pixel cell correspondence connects described first grid line, and described second group of pixel cell correspondence connects described second grid line; The described pixel cell of row connecting described first grid line connects described first data line with the described pixel cell correspondence of row being connected described second grid line, and described second data line connects one to one with many respectively for many described first grid lines and many described second grid lines; Described first data line is used for providing data-signal for described pixel cell, and described second data line is used for providing sweep signal for described pixel cell.
2. array base palte according to claim 1, it is characterized in that, described first group of pixel cell comprises pixel cell described in the odd number of often going in described pixel cell, and described second group of pixel cell comprises pixel cell described in the even number of often going in described pixel cell;
Adjacent odd column is connected described first data line with pixel cell correspondence described in even column.
3. array base palte according to claim 2, is characterized in that, described first grid line and described second grid line are all parallel to described pixel cell and are expert at, and described first data line and described second data line are all parallel to described pixel cell column;
Multiple described pixel cell, many described first grid lines and described second grid line and many described first data lines and described second data line are all positioned at viewing area, scan drive cell and data drive unit is also provided with in the periphery, side along described first data line and described second data line bearing of trend of described viewing area, described first data line connects described data drive unit, and described second data line connects described scan drive cell.
4. array base palte according to claim 3, is characterized in that, described data drive unit and described scan drive cell on a single die integrated.
5. array base palte according to claim 3, it is characterized in that, often go in described pixel cell, corresponding connect pixel cell described in odd number described first grid line and corresponding described second grid line being connected pixel cell described in even number lay respectively at every capable described pixel cell above and below its column direction;
Second data line described in first data line described in every bar and every bar is respectively described in adjacent odd column and even column between pixel cell, and described first data line and the interlaced distribution of described second data line;
Described in every bar, the second data line correspondence connects described first grid line or described second grid line.
6. array base palte according to claim 5, it is characterized in that, described pixel cell comprises transistor and pixel electrode, corresponding connect described first data line odd column and even column described in the described transistor of pixel cell near described first data line arrangement.
7. array base palte according to claim 6, is characterized in that, the drain electrode of described transistor connects described pixel electrode;
Often go in described pixel cell, the described transistor of pixel cell described in odd number is positioned at the upper right corner of close described first data line of pixel electrode described in it, and the described transistor of pixel cell described in even number is positioned at the lower left corner of pixel electrode described in it near described first data line;
The grid of the described transistor of pixel cell described in odd number all connects described first grid line; The grid of the described transistor of pixel cell described in even number all connects described second grid line;
Be positioned at the odd number of the first data line both sides described in every bar and be all connected this described first data line with the source electrode of the described transistor of pixel cell described in even number.
8. array base palte according to claim 6, is characterized in that, the drain electrode of described transistor connects described pixel electrode;
Often go in described pixel cell, the described transistor of pixel cell described in odd number is positioned at the lower right corner of close described first data line of pixel electrode described in it, and the described transistor of pixel cell described in even number is positioned at the upper left corner of pixel electrode described in it near described first data line;
The grid of the described transistor of pixel cell described in even number all connects described first grid line; The grid of the described transistor of pixel cell described in odd number all connects described second grid line;
Be positioned at the odd number of the first data line both sides described in every bar and be all connected this described first data line with the source electrode of the described transistor of pixel cell described in even number.
9. the array base palte according to claim 7 or 8, described first grid line and described second grid line are arranged with layer, and described second data line bit is above or below described first grid line and described second grid line; Described second data line and be provided with insulation course between described first grid line and described second grid line;
Offer the first via hole with the corresponding region, folded region of covering mutually of described second data line and described first grid line one to one in described insulation course, described second data line and described first grid line are connected one to one by described first via hole;
Offer the second via hole with the corresponding region, folded region of covering mutually of described second data line and described second grid line one to one in described insulation course, described second data line and described second grid line are connected one to one by described second via hole.
10. a display panel, is characterized in that, comprises the array base palte described in claim 1-9 any one.
11. 1 kinds of display device, is characterized in that, comprise display panel according to claim 10.
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| CN201520269956.1U CN204536699U (en) | 2015-04-29 | 2015-04-29 | A kind of array base palte, display panel and display device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105047122A (en) * | 2015-09-08 | 2015-11-11 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN108847415A (en) * | 2018-06-29 | 2018-11-20 | 厦门天马微电子有限公司 | A kind of array substrate, gate driving circuit and display panel |
| WO2019033552A1 (en) * | 2017-08-14 | 2019-02-21 | 深圳市华星光电半导体显示技术有限公司 | Organic light-emitting diode display device |
| CN111554194A (en) * | 2020-05-25 | 2020-08-18 | Tcl华星光电技术有限公司 | Display panel and display device |
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2015
- 2015-04-29 CN CN201520269956.1U patent/CN204536699U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105047122A (en) * | 2015-09-08 | 2015-11-11 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| US10026347B2 (en) | 2015-09-08 | 2018-07-17 | Boe Technology Group Co., Ltd. | Array substrate, display panel and display device |
| WO2019033552A1 (en) * | 2017-08-14 | 2019-02-21 | 深圳市华星光电半导体显示技术有限公司 | Organic light-emitting diode display device |
| CN108847415A (en) * | 2018-06-29 | 2018-11-20 | 厦门天马微电子有限公司 | A kind of array substrate, gate driving circuit and display panel |
| CN108847415B (en) * | 2018-06-29 | 2020-08-11 | 厦门天马微电子有限公司 | Array substrate, grid drive circuit and display panel |
| CN111554194A (en) * | 2020-05-25 | 2020-08-18 | Tcl华星光电技术有限公司 | Display panel and display device |
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