US20130181605A1 - Display panel - Google Patents
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- US20130181605A1 US20130181605A1 US13/733,897 US201313733897A US2013181605A1 US 20130181605 A1 US20130181605 A1 US 20130181605A1 US 201313733897 A US201313733897 A US 201313733897A US 2013181605 A1 US2013181605 A1 US 2013181605A1
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- pixel blocks
- transmission lines
- edge region
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- 239000000758 substrate Substances 0.000 claims abstract description 36
- 230000005540 biological transmission Effects 0.000 claims description 133
- 238000010586 diagram Methods 0.000 description 10
- 230000001808 coupling effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 241001270131 Agaricus moelleri Species 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Classifications
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- H05B37/00—
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13456—Cell terminals located on one side of the display only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
Definitions
- the present disclosure relates to display technology. More particularly, the present invention relates to a display panel.
- display panels have been used in various different electronic products, such as cell phones, tablet computers, and digital cameras.
- a display panel typically has a scan IC chip and a data IC chip disposed respectively to two sides of an active area.
- Wiring lines are disposed around the active area for providing signals to scan lines and data lines orthogonal to the scan lines.
- the display panel includes a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixel units, a plurality of transmission lines, and a driver IC chip.
- the substrate includes an active area, in which the active area includes a plurality of pixel blocks.
- the first signal lines are disposed parallel to each other on the substrate.
- the second signal lines are disposed parallel to each other on the substrate, and crossing over the first signal lines to define the pixel blocks, in which there are more of the second signal lines than the first signal lines.
- the pixel units are respectively disposed within the pixel blocks, and respectively electrically connected to the first signal lines and respectively electrically connected to the second signal lines.
- the transmission lines are disposed parallel to each other on the substrate, respectively electrically connected to the second signal lines, crossing two opposite sides of the active area, and parallel to the first signal lines.
- the driver IC chip includes a plurality of first pins, a plurality of second pins, and a driver circuit.
- the first pins are electrically connected to the first signal lines.
- the second pins are electrically connected to the transmission lines.
- the driver circuit is configured to generate a first signal and a second signal, and to respectively transmit the first signal and the second signal to the first pins and the second pins.
- the first pins and the second pins are evenly disposed and interleaved with each other, such that the first signal lines and the transmission lines electrically connected to the first pins and the second pins do not cross over each other, and the transmission lines are evenly disposed on the substrate.
- the display panel includes a plurality of dummy lines.
- the dummy lines are evenly disposed on the substrate, parallel to the transmission lines and crossing the two opposite sides of the active area.
- the transmission lines are divided into a to plurality of first transmission lines and a plurality of second transmission lines. The quantity of the first transmission lines passing through each pixel block is the same.
- Each pixel block is passed through by one of the second transmission lines or one of the dummy lines.
- the display panel further includes a periphery circuit and a control circuit.
- the periphery circuit is disposed on the substrate and around the active area, and configured to electrically connect the dummy lines to each other.
- the control circuit is electrically connected to the periphery circuit and the driver IC chip, and configured to provide a turn-off voltage level to the periphery circuit, and to drive the driver IC chip.
- the orthogonal projections of the dummy lines, the first transmission lines, the second transmission lines, and the first signal lines on the substrate are not overlapped.
- areas of the pixel blocks that are located between two adjacent dummy lines and that are not passed through by the dummy lines define a plurality of central regions, and the quantity of the pixel blocks within each of the central regions is the same.
- an area of the pixel blocks that are located between a first edge and one of the dummy lines which is nearest to the first edge and that are not passed through by the dummy lines defines a first edge region
- an area of the pixel blocks that are to located between a second edge and one of the dummy lines which is nearest to the second edge and that are not passed through by the dummy lines defines a second edge region
- the first edge and the second edge are two opposite edges of the active area
- the quantity of the pixel blocks within the first edge region and the quantity of the pixel blocks within the second edge region are the same.
- an area of the pixel blocks that are located between a first edge and one of the dummy lines which is nearest to the first edge and that are not passed through by the dummy lines defines a first edge region
- an area of the pixel blocks that are located between a second edge and one of the dummy lines which is nearest to the second edge and that are not passed through by the dummy lines defines a second edge region
- the first edge and the second edge are two opposite edges of the active area
- the quantity of the pixel blocks within the first edge region and the quantity of the pixel blocks within each central region are the same
- the quantity of the pixel blocks within the first edge region and the quantity of the pixel blocks within the second edge region are different.
- areas of the pixel blocks that are located between two adjacent second transmission lines and that are not passed through by the second transmission lines define a plurality of central regions, and the quantity of the pixel blocks within each of the central regions is the same.
- an area of the pixel blocks that are located between a first edge and one of the second to transmission lines which is nearest to the first edge and that are not passed through by the second transmission lines defines a first edge region
- an area of the pixel blocks that are located between a second edge and one of the second transmission lines which is nearest to the second edge and that are not passed through by the second transmission lines defines a second edge region
- the first edge and the second edge are two opposite edges of the active area
- the quantity of the pixel blocks within the first edge region and the quantity of the pixel blocks within the second edge region are the same.
- an area of the pixel blocks that are located between a first edge and one of the second transmission lines which is nearest to the first edge and that are not passed through by the second transmission lines defines a first edge region
- an area of the pixel blocks that are located between a second edge and one of the second transmission lines which is nearest to the second edge and that are not passed through by the second transmission lines defines a second edge region
- the first edge and the second edge are two opposite edges of the active area
- the quantity of the pixel blocks within the first edge region and the quantity of the pixel blocks within each central region are the same
- the quantity of the pixel blocks thin the first edge region and the quantity of the pixel blocks within the second edge region are different.
- each of the first pins and second pins selectively outputs 5 voltage levels.
- the first pins are corresponding to first voltage levels
- the second pins are corresponding to second voltage levels.
- the borders of the display panel can be thinner by using the first and second transmission lines to transmit the second signal.
- the first pins and the second pins of the driver IC chip can be evenly disposed and interleaved, so that the first signal lines and the transmission lines do not cross over each other, and the capacitance coupling effect and stray capacitance can be avoided.
- parasitic capacitance can be avoided.
- load imbalance in the active area of the display panel also can be avoided, so that the quality of the image of the display panel can be improved.
- FIG. 1 is a schematic diagram of a display panel in accordance with one embodiment of the present disclosure
- FIG. 2 is a sectional view of the display panel taken along line 2 - 2 in FIG. 1 .
- FIG. 3 is a schematic diagram illustrating the disposition of second transmission lines and dummy lines in accordance with one embodiment of the present disclosure
- FIG. 4 is a schematic diagram illustrating the disposition of the second transmission lines and the dummy lines in accordance with one embodiment of the present disclosure
- FIG. 5 is a schematic diagram illustrating the disposition of the second transmission lines and the dummy lines in accordance with one embodiment of the present disclosure.
- FIG. 6 is a schematic diagram illustrating the disposition of the second transmission lines and the dummy lines in accordance with one embodiment of the present disclosure.
- FIG. 1 is a schematic diagram of a display panel 100 in accordance with one embodiment of the present disclosure.
- the display panel 100 includes a substrate 110 , a plurality of first signal lines 120 , a plurality of second signal lines 122 , a plurality of pixel units 130 , a plurality of transmission lines 140 , 142 , and a driver IC chip 150 .
- the first signal lines 120 and the second to signal lines 122 may separately be data lines and scan lines. That is, when the first signal lines 120 are data lines, the second signal lines 122 are the scan lines, and vice versa.
- the substrate 110 includes an active area 112 including a plurality of pixel blocks 114 .
- the first signal lines 120 are disposed parallel to each other on the substrate 110 .
- the second signal lines 122 are disposed parallel to each other on the substrate 110 and crossing over the first signal lines 120 to define the pixel blocks 114 .
- the quantity of the second signal lines 122 is more than the quantity of the first signal lines 120 .
- the pixel units 130 are respectively disposed within the pixel blocks 114 , and respectively electrically connected to the first signal lines 120 and respectively electrically connected also to the second signal lines 122 .
- Each pixel unit 130 includes a switch (for example, a thin-film transistor), a storage capacitor and a pixel electrode (all not shown).
- the storage capacitor When the switch is opened by a signal (i.e., a scan signal), the storage capacitor can be charged by a data signal with a data voltage transmitted by the data line, and continuously provide the data voltage to the pixel electrode when the switch is closed.
- the transmission lines 140 , 142 are disposed parallel to each other on the substrate 110 , crossing through two opposite sides of the active area 112 , and parallel to the first signal lines 120 .
- the driver IC chip 150 can include a plurality of first pins 152 , a plurality of second pins 154 , and a driver circuit 156 .
- the first pins 152 are electrically connected to the first signal lines 120 .
- the second pins 154 are electrically connected to the transmission lines 140 , 142 .
- the driver circuit 156 can generate a first signal and a second signal, and respectively transmit the first signal and the second signal to the first to pins 152 and the second pins 154 .
- the first pins 152 and the second pins 154 are evenly disposed and interleaved with each other, such that the first signal lines 120 and the transmission lines 140 , 142 electrically connected to the first pins 152 and the second pins 154 do not cross over each other, and the transmission lines 140 , 142 can be evenly disposed on the substrate 110 .
- the wiring lines that are used to electrically connect the first pins 152 to the first signal lines 120 and electrically connect the second pins 154 to the transmission lines 140 , 142 do not cross over each other.
- the transmission lines 140 , 142 can be connected to the second signal lines 122 via through holes or contact plugs.
- the first signal and the second signal can respectively be a data signal (for supply to data lines) and a scan signal (for supply to scan lines). The data signal and the scan signal have different voltage levels.
- the voltage level of the data signal can be ⁇ 15V, 0V, and +15V, for use in representing different gray scales
- the voltage level of the scan signal can be ⁇ 20V and +22V, for use in respectively turning off or turning on transistors of a row of pixel units 130 .
- the driver IC chip 150 can be an adjustable driver IC chip.
- the driver IC chip 150 can determine any pin to serve as one of the first pins 152 or one of the second pins 154 by providing this pin a different signal, such as a data signal or a scan signal, through the driver circuit 156 . That is, each pin of the driver IC chip 150 can selectively output a data signal or a scan signal, depending on the voltage level that is provided to the pin. For example, if the driver IC chip 150 provides a scan signal, of which the voltage level may to be ⁇ 20V or +22V, to one specific pin through the driver circuit 156 , then the specific pin would serve as a scan pin used to connect to the scan lines.
- the driver IC chip 150 can provide any pin with a different voltage level through the driver circuit 156 , such that the specific pin can be used to connect to the scan lines or to the data lines depending on actual requirements.
- five voltage levels can be provided, such as ⁇ 15V, 0V, +15V, ⁇ 20V, +22V.
- the following table shows an example of a pin allocation of the driver IC chip 150 .
- G indicates a scan pin and S indicates a data pin.
- S indicates a data pin.
- pin 1 is a scan pin
- pin 2 is a data pin
- the first pins 152 and the second pins 154 can be evenly disposed and interleaved with each other, such that the first signal lines 120 and the transmission lines 140 , 142 do not cross over each other (that is, the wiring lines that are used to electrically connect the first pins 152 to the first to signal lines 120 and electrically connect the second pins 154 to the transmission lines 140 , 142 do not cross over each other), and the transmission lines 140 , 142 are evenly disposed on the substrate 110 .
- the border of the display panel 100 can become thinner.
- the pin allocation of the driver IC chip 150 mentioned above the first signal lines 120 and the transmission lines 140 , 142 do not cross over each other, such that the stray capacitance and the capacitance coupling effect can be avoided.
- the transmission lines 140 , 142 are evenly disposed on the substrate 110 , such that uneven brightness in an image caused by load imbalance of the active area 112 can be avoided.
- the load imbalance problem of the active area 112 may still occur due to the number of the transmission lines 140 passing through each pixel block 114 being different from each other.
- dummy lines 160 can be disposed to overcome such a problem in some embodiments.
- the display panel 100 further includes a plurality of dummy lines 160 .
- the dummy lines 160 are evenly disposed on the substrate 110 , parallel to the transmission lines 140 , 142 , and crossing through two opposite sides of the active area 112 .
- the transmission lines 140 , 142 can be divided into a plurality of first transmission lines 140 and a plurality of second transmission lines 142 .
- the quantity of the first transmission lines 140 passing through each of the pixel blocks 114 is the same.
- one of the second transmission lines 142 or one of the dummy lines 160 passes through each of the pixel blocks 114 .
- an equal quantity of the first transmission lines 140 are disposed on each column of pixel blocks 114 , and due to the fact that there is an insufficient quantity of the second transmission lines 142 to be disposed on each column of pixel blocks 114 , the dummy lines 160 are disposed on the columns of pixel blocks 114 not having the second transmission lines 142 passed therethrough. As a result, uneven brightness in images caused by load imbalance of the active area 112 can be avoided.
- the display panel 100 further includes a periphery circuit 170 and a control circuit 180 .
- the periphery circuit 170 is disposed on the substrate 110 and around the active area 112 , and is configured to electrically connect all the dummy lines 160 to each other.
- the control circuit 180 is electrically connected to the periphery circuit 170 and the driver IC chip 150 , and is configured to provide a turn-off voltage level to the periphery circuit 170 and to drive the driver IC chip 150 .
- the drive circuit 180 can be implemented by hardware, software, or partly by hardware and partly by software.
- the turn-off voltage level can be the voltage level in a scan signal used to turn off the switch of the pixel unit 130 , and for example, the turn-off voltage level can be ⁇ 20V.
- the dummy lines 160 can act like the first and second transmission lines 140 , 142 provided with the turn-off voltage level, such that the display panel 100 can avoid the uneven brightness problem in an image caused by load imbalance.
- the number of pins of the driver IC chip 150 can be minimized, and the cost and complexity of the driver IC chip 150 can be reduced.
- FIG. 2 is a sectional view of the display panel 100 taken along line 2 - 2 in FIG. 1 .
- the orthogonal projection of the dummy lines 160 on the substrate 110 (labeled as P 1 ), the orthogonal projection of the first transmission lines 140 on the substrate 110 (labeled as P 2 ), the orthogonal projection of the second transmission lines 142 on the substrate 110 (labeled as P 3 ), and the orthogonal projection of the first signal lines 120 on the substrate 110 (labeled as P 4 ) are not overlapped.
- parasitic capacitance and capacitance coupling effect can be avoided. It is noted that the configuration in FIG.
- first signal lines 120 , the first transmission lines 140 , the second transmission lines 142 , and the dummy lines 160 can be disposed on different circuit layers determined on the basis of actual requirements, and the present invention is not limited by the embodiment shown in FIG. 2 .
- the second transmission lines 142 are configured to transmit the second signal while the dummy lines 160 do not transmit any signal
- the second transmission lines 142 and the dummy lines 160 can be evenly disposed on the active area 112 , so as to avoid uneven brightness in an image caused by load imbalance of the active area 112 .
- FIG. 3 to FIG. 6 in which different embodiments are illustrated.
- FIG. 3 is a schematic diagram illustrating the disposition of the second transmission lines 142 and the dummy lines 160 in accordance with one embodiment of the present disclosure.
- the active area 112 is a 15 ⁇ 9 array built with the pixel blocks 114 .
- the active area 112 has a first edge 320 and a second edge 330 .
- the first edge 320 and the second edge 330 are opposite to each other, and parallel to the dummy lines 160 .
- the quantity of the first transmission lines 140 is 9, and the first transmission lines 140 are connected to some of the second signal lines 122 .
- the second transmission lines 142 are connected to the rest of the second signal lines 122 , that is, the second signal lines 122 which are not connected with the first transmission lines 140 , and therefore the quantity of the second transmission lines 142 is 6.
- the dummy lines 160 can be disposed on column 2 , 5 , and 8 of the pixel blocks 114 , and the second transmission lines 142 can be correspondingly disposed on column 1 , 3 , 4 , 6 , 7 , and 9 of the pixel blocks 114 . With such a configuration, the load imbalance problem of the active area 112 can be avoided by evenly disposing the second transmission lines 142 and dummy lines 160 .
- the areas of the pixel blocks 114 that are located between two adjacent dummy lines 160 and that are not passed through by the dummy lines 160 define a plurality of central regions 310 .
- the quantity of the pixel blocks 114 within each central region 310 is the same.
- the quantity of the pixel blocks 114 within each central region 310 is 30. With to such a configuration, the load imbalance problem of the active area 112 can be avoided.
- the area of the pixel blocks 114 that are located between the first edge 320 and one of the dummy lines 160 which is nearest to the first edge 320 and that are not passed through by the dummy lines 160 defines a first edge region 322
- the area of the pixel blocks 114 that are located between the second edge 330 and one of the dummy lines 160 which is nearest to the second edge 330 and that are not passed through by the dummy lines 160 defines a second edge region 332 .
- both of the quantities of the pixel blocks 114 within the first edge region 322 and the second edge region 332 are 15. It should be noted that although the quantity of the pixel blocks 114 within each of the first edge region 322 and the second edge region 332 is different from the quantity of the pixel blocks 114 within the central regions 310 due to the fact that uneven brightness in the first edge region 322 and the second edge region 332 is not easily visually perceivable, any negative effect that may be caused by such differences in quantities of the pixel blocks 114 in these regions is negligible. In addition, in another embodiment, the quantity of the pixel blocks 114 within each of the first edge region 322 and the second edge region 332 can be the same as the quantity of the pixel blocks 114 within the central regions 310 .
- FIG. 4 is a schematic diagram illustrating the disposition of the second to transmission lines 142 and the dummy lines 160 in accordance with one embodiment of the present disclosure.
- the active area 112 is also a 15 ⁇ 9 array built with the pixel blocks 114 , the same as the embodiment in FIG. 3 , and therefore, aspects of this embodiment that are similar to those of the previous embodiment will not be repeated herein.
- the active area 112 has a first edge 420 and a second edge 430 .
- the dummy lines 160 can be disposed on column 3 , 6 , and 9 of the pixel blocks 114
- the second transmission lines 142 can be correspondingly disposed on column 1 , 2 , 4 , 5 , 7 , and 8 of the pixel blocks 114 .
- the areas of pixel blocks 114 that are located between two adjacent dummy lines 160 and that are not passed through by the dummy lines 160 define a plurality of central regions 410 .
- the quantity of the pixel blocks 114 within each central region 410 is 30.
- the area of the pixel blocks 114 that are located between the first edge 420 and one of the dummy lines 160 which is nearest to the first edge 420 and that are not be passed by the dummy lines 160 defines a first edge region 422
- the area of the pixel blocks 114 that are located between the second edge 430 and one of the dummy lines 160 which is nearest to the second edge 430 and that are not passed through by the dummy lines 160 defines a second edge region 432 .
- the quantity of the pixel blocks 114 within the first edge region 422 is 30, and the quantity of the pixel blocks 114 within the second edge region 432 is 0.
- the quantity of the pixel blocks 114 within the first edge region 422 is the same as the quantity of the pixel blocks 114 within the central regions 410 , while is different from the quantity of the pixel blocks 114 within the second edge region 432 , due to the fact that uneven brightness in the first edge region 422 and the second edge region 432 is not easily visually perceivable, any negative effect that may be caused by such differences in quantities of the pixel blocks 114 in these regions is negligible.
- the active area 112 is divided by the dummy lines 160 .
- the active area 112 will be divided by the second transmission lines 142 .
- FIG. 5 is a diagram illustrating the disposition of the second transmission lines 142 and the dummy lines 160 in accordance with one embodiment of the present disclosure.
- the active area 112 is a 12 ⁇ 9 array built with the pixel blocks 114 .
- the active area 112 has a first edge 520 and a second edge 530 .
- the first edge 520 and the second edge 530 are opposite to each other, and parallel to the dummy lines 160 .
- the quantity of the first transmission lines 140 is 9, and the first transmission lines 140 are connected to some of the second signal lines 122 .
- the second transmission lines 142 are connected to the rest of the second signal lines 122 , that is, the second signal lines 122 which are not connected with the first transmission lines 140 , and therefore the quantity of the second transmission lines 142 is 3.
- the second transmission lines 142 can be disposed on column 2 , 5 , and 8 of the pixel blocks 114 , and the dummy lines 160 can be correspondingly disposed on column 1 , 3 , 4 , 6 , 7 , and 9 of the pixel blocks 114 . With such a configuration, the load imbalance problem of the active area 112 can be avoided by evenly disposing the second transmission lines 142 and dummy lines 160 .
- the areas of the pixel blocks 114 that are located between two adjacent second transmission lines 142 and that are not passed through by the second transmission lines 142 define a plurality of central regions 510 .
- the quantity of the pixel blocks 114 within each central region 510 is the same.
- the quantity of the pixel blocks 114 within each central region 510 is 24. With such a configuration, the load imbalance problem of the active area 112 can be avoided.
- the area of the pixel blocks 114 that are located between the first edge 520 and one of the second transmission lines 142 which is nearest to the first edge 520 and that are not passed through by the second transmission lines 142 defines a first edge region 522
- the area of the pixel blocks 114 that are located between the second edge 530 and one of the second transmission lines 142 which is nearest to the second edge 530 and that are not passed through by the second transmission lines 142 defines a second edge region 532 .
- both of the quantities of the pixel blocks 114 within the first edge region 522 and the second edge region 532 are 12. It should be noted that although the quantity of the pixel blocks 114 within each of the first edge region 522 and the second edge region 532 is different from the quantity of the pixel blocks 114 within each of the central regions 510 , due to the fact that uneven brightness in the first edge region 522 and the second edge region 532 is not easily visually perceivable, any negative effect that may be caused by such differences in quantities of the pixel blocks 114 in these regions is negligible. In addition, in another embodiment, the quantity of the pixel blocks 114 within each of the first edge region 522 and the second edge region 532 can be the same as the quantity of the pixel blocks 114 within each of the central regions 510 .
- FIG. 6 is a diagram illustrating the disposition of the second transmission lines 142 and the dummy lines 160 in accordance with one embodiment of the present disclosure.
- the active area 112 is also a 12 ⁇ 9 array built with the pixel blocks 114 , the same as the embodiment in FIG. 5 , and therefore, aspects of this embodiment that are similar to those of the previous embodiment will not be repeated herein.
- the active area 112 has a first edge 620 and a second edge 630 .
- the second transmission lines 142 can be disposed on column 3 , 6 , and 9 of the pixel blocks 114
- the dummy lines 160 can be correspondingly disposed on column 1 , 2 , 4 , 5 , 7 , and 8 of the pixel blocks 114 .
- the areas of the pixel blocks 114 that are located between two adjacent second transmission lines 142 and that are not be passed through by the second transmission lines 142 are referring to as central regions 610 .
- the quantity of the pixel blocks 114 within each central region 610 is 24.
- the area of the pixel blocks 114 that are located between the first edge to 620 and one of the second transmission lines 142 which is nearest to the first edge 620 and that are not passed through by the second transmission lines 142 defines a first edge region 622
- the area of the pixel blocks 114 that are located between the second edge 630 and one of the second transmission lines 142 which is nearest to the second edge 630 and that are not passed through by the second transmission lines 142 defines a second edge region 632 .
- the quantity of the pixel blocks 114 within the first edge region 622 is 24, and the quantity of the pixel blocks 114 within the second edge region 632 is 0.
- the quantity of the pixel blocks 114 within the first edge region 622 is the same as the quantity of the pixel blocks 114 within each of the central regions 610 , and is different from the quantity of the pixel blocks 114 within the second edge region 632 , due to the fact that uneven brightness in the first edge region 622 and the second edge region 632 is not easily visually perceivable, any negative effect that may be caused by such differences in quantities of the pixel blocks 114 in these regions is negligible.
- the second transmission lines 142 and the dummy lines 160 are evenly disposed to make the quantities of pixel blocks 114 within the central regions 310 , 410 , 510 , 610 , which are defined by the dummy lines 160 or the second transmission lines 142 , the same.
- the pixel blocks 114 can not be passed through by the dummy lines 160 and the second transmission lines 142 evenly, the pixel blocks 114 associated with such unevenness can be arranged within the first and second edge regions 322 , 332 , to 422 , 432 , 522 , 532 , 622 , 632 of the active area 112 , such that the areas of uneven brightness of the active area 112 are not visually perceivable.
- FIGS. 3 , 4 , 5 , and 6 are used to explain the idea of disposing the dummy lines 160 and the second transmission lines 142 , and this invention is not limited by these embodiments.
- first edge 320 , 420 , 520 , 620 and the second edge 330 , 430 , 530 , 630 are two opposite edges of the active area 112 , parallel to the dummy lines 160 , and are not limited by the embodiments in FIGS. 3 , 4 , 5 , and 6 .
- the borders of the display panel 100 can be made thinner by using the first and second transmission lines 140 , 142 to transmit the second signal.
- the first and second transmission lines 140 , 142 may cross over each other, causing the stray capacitance, and moreover, the first and second transmission lines 140 , 142 may cause the problem of load imbalance of the active area 112 . Therefore, the first pins 152 and the second pins 154 of the driver IC chip 150 can be evenly disposed and interleaved, so that the second transmission lines 142 can be evenly disposed on the active area 112 , and the capacitance coupling effect caused by stray capacitance can be avoided.
- the uneven brightness in an image caused by load imbalance of the active area 112 can also be avoided.
- parasitic capacitance can be avoided.
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Abstract
Description
- This application claims priority to U.S. Provisional Application Ser. No. 61/587,643, filed Jan. 17, 2012, and Taiwan Application Serial Number 101123897, filed Jul. 3, 2012, the disclosures of which are incorporated herein by reference in their entireties.
- 1. Field of Invention
- The present disclosure relates to display technology. More particularly, the present invention relates to a display panel.
- 2. Description of Related Art
- With advances in display technology, display panels have been used in various different electronic products, such as cell phones, tablet computers, and digital cameras.
- A display panel typically has a scan IC chip and a data IC chip disposed respectively to two sides of an active area. Wiring lines are disposed around the active area for providing signals to scan lines and data lines orthogonal to the scan lines. With such a configuration, a sufficient space is necessary around the active area to place the scan IC chip, the data IC chip, and the wiring lines. However, it is difficult to realize a display panel with thin borders with such a traditional approach, and this runs counter to trends of making electronic devices increasingly thinner, lighter and smaller.
- Therefore, in order to allow for more widespread use of display panels, the aforementioned problem must be solved.
- One aspect of the present invention is a display panel. In accordance with one embodiment of the present invention, the display panel includes a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixel units, a plurality of transmission lines, and a driver IC chip. The substrate includes an active area, in which the active area includes a plurality of pixel blocks. The first signal lines are disposed parallel to each other on the substrate. The second signal lines are disposed parallel to each other on the substrate, and crossing over the first signal lines to define the pixel blocks, in which there are more of the second signal lines than the first signal lines. The pixel units are respectively disposed within the pixel blocks, and respectively electrically connected to the first signal lines and respectively electrically connected to the second signal lines. The transmission lines are disposed parallel to each other on the substrate, respectively electrically connected to the second signal lines, crossing two opposite sides of the active area, and parallel to the first signal lines. The driver IC chip includes a plurality of first pins, a plurality of second pins, and a driver circuit. The first pins are electrically connected to the first signal lines. The second pins are electrically connected to the transmission lines. The driver circuit is configured to generate a first signal and a second signal, and to respectively transmit the first signal and the second signal to the first pins and the second pins. The first pins and the second pins are evenly disposed and interleaved with each other, such that the first signal lines and the transmission lines electrically connected to the first pins and the second pins do not cross over each other, and the transmission lines are evenly disposed on the substrate.
- In accordance with one embodiment of the present invention, the display panel includes a plurality of dummy lines. The dummy lines are evenly disposed on the substrate, parallel to the transmission lines and crossing the two opposite sides of the active area. The transmission lines are divided into a to plurality of first transmission lines and a plurality of second transmission lines. The quantity of the first transmission lines passing through each pixel block is the same. Each pixel block is passed through by one of the second transmission lines or one of the dummy lines.
- In accordance with one embodiment of the present invention, the display panel further includes a periphery circuit and a control circuit. The periphery circuit is disposed on the substrate and around the active area, and configured to electrically connect the dummy lines to each other. The control circuit is electrically connected to the periphery circuit and the driver IC chip, and configured to provide a turn-off voltage level to the periphery circuit, and to drive the driver IC chip.
- In accordance with one embodiment of the present invention, the orthogonal projections of the dummy lines, the first transmission lines, the second transmission lines, and the first signal lines on the substrate are not overlapped.
- In accordance with one embodiment of the present invention, areas of the pixel blocks that are located between two adjacent dummy lines and that are not passed through by the dummy lines define a plurality of central regions, and the quantity of the pixel blocks within each of the central regions is the same.
- In accordance with one embodiment of the present invention, an area of the pixel blocks that are located between a first edge and one of the dummy lines which is nearest to the first edge and that are not passed through by the dummy lines defines a first edge region, an area of the pixel blocks that are to located between a second edge and one of the dummy lines which is nearest to the second edge and that are not passed through by the dummy lines defines a second edge region, the first edge and the second edge are two opposite edges of the active area, and the quantity of the pixel blocks within the first edge region and the quantity of the pixel blocks within the second edge region are the same.
- In accordance with one embodiment of the present invention, an area of the pixel blocks that are located between a first edge and one of the dummy lines which is nearest to the first edge and that are not passed through by the dummy lines defines a first edge region, an area of the pixel blocks that are located between a second edge and one of the dummy lines which is nearest to the second edge and that are not passed through by the dummy lines defines a second edge region, the first edge and the second edge are two opposite edges of the active area, the quantity of the pixel blocks within the first edge region and the quantity of the pixel blocks within each central region are the same, and the quantity of the pixel blocks within the first edge region and the quantity of the pixel blocks within the second edge region are different.
- In accordance with one embodiment of the present invention, areas of the pixel blocks that are located between two adjacent second transmission lines and that are not passed through by the second transmission lines define a plurality of central regions, and the quantity of the pixel blocks within each of the central regions is the same.
- In accordance with one embodiment of the present invention, an area of the pixel blocks that are located between a first edge and one of the second to transmission lines which is nearest to the first edge and that are not passed through by the second transmission lines defines a first edge region, an area of the pixel blocks that are located between a second edge and one of the second transmission lines which is nearest to the second edge and that are not passed through by the second transmission lines defines a second edge region, the first edge and the second edge are two opposite edges of the active area, and the quantity of the pixel blocks within the first edge region and the quantity of the pixel blocks within the second edge region are the same.
- In accordance with one embodiment of the present invention, an area of the pixel blocks that are located between a first edge and one of the second transmission lines which is nearest to the first edge and that are not passed through by the second transmission lines defines a first edge region, an area of the pixel blocks that are located between a second edge and one of the second transmission lines which is nearest to the second edge and that are not passed through by the second transmission lines defines a second edge region, the first edge and the second edge are two opposite edges of the active area, the quantity of the pixel blocks within the first edge region and the quantity of the pixel blocks within each central region are the same, and the quantity of the pixel blocks thin the first edge region and the quantity of the pixel blocks within the second edge region are different.
- In accordance with one embodiment of the present invention, each of the first pins and second pins selectively outputs 5 voltage levels.
- In accordance with one embodiment of the present invention, the first pins are corresponding to first voltage levels, and the second pins are corresponding to second voltage levels.
- In summary, with the embodiments mentioned above, the borders of the display panel can be thinner by using the first and second transmission lines to transmit the second signal. The first pins and the second pins of the driver IC chip can be evenly disposed and interleaved, so that the first signal lines and the transmission lines do not cross over each other, and the capacitance coupling effect and stray capacitance can be avoided. In addition, by ensuring that the orthogonal projections of the first signal lines, the first transmission lines, the second transmission lines, and the dummy lines on the substrate do not overlap, parasitic capacitance can be avoided. Moreover, by evenly disposing the dummy lines and the second transmission lines, load imbalance in the active area of the display panel also can be avoided, so that the quality of the image of the display panel can be improved.
- The invention can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
-
FIG. 1 is a schematic diagram of a display panel in accordance with one embodiment of the present disclosure; -
FIG. 2 is a sectional view of the display panel taken along line 2-2 inFIG. 1 . -
FIG. 3 is a schematic diagram illustrating the disposition of second transmission lines and dummy lines in accordance with one embodiment of the present disclosure; -
FIG. 4 is a schematic diagram illustrating the disposition of the second transmission lines and the dummy lines in accordance with one embodiment of the present disclosure; -
FIG. 5 is a schematic diagram illustrating the disposition of the second transmission lines and the dummy lines in accordance with one embodiment of the present disclosure; and -
FIG. 6 is a schematic diagram illustrating the disposition of the second transmission lines and the dummy lines in accordance with one embodiment of the present disclosure. - In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to attain a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.
-
FIG. 1 is a schematic diagram of adisplay panel 100 in accordance with one embodiment of the present disclosure. Thedisplay panel 100 includes asubstrate 110, a plurality offirst signal lines 120, a plurality ofsecond signal lines 122, a plurality ofpixel units 130, a plurality oftransmission lines driver IC chip 150. It is noted that thefirst signal lines 120 and the second tosignal lines 122 may separately be data lines and scan lines. That is, when thefirst signal lines 120 are data lines, thesecond signal lines 122 are the scan lines, and vice versa. - The
substrate 110 includes anactive area 112 including a plurality of pixel blocks 114. Thefirst signal lines 120 are disposed parallel to each other on thesubstrate 110. Thesecond signal lines 122 are disposed parallel to each other on thesubstrate 110 and crossing over thefirst signal lines 120 to define the pixel blocks 114. The quantity of thesecond signal lines 122 is more than the quantity of the first signal lines 120. Thepixel units 130 are respectively disposed within the pixel blocks 114, and respectively electrically connected to thefirst signal lines 120 and respectively electrically connected also to the second signal lines 122. Eachpixel unit 130 includes a switch (for example, a thin-film transistor), a storage capacitor and a pixel electrode (all not shown). When the switch is opened by a signal (i.e., a scan signal), the storage capacitor can be charged by a data signal with a data voltage transmitted by the data line, and continuously provide the data voltage to the pixel electrode when the switch is closed. Thetransmission lines substrate 110, crossing through two opposite sides of theactive area 112, and parallel to the first signal lines 120. Thedriver IC chip 150 can include a plurality offirst pins 152, a plurality ofsecond pins 154, and adriver circuit 156. The first pins 152 are electrically connected to the first signal lines 120. The second pins 154 are electrically connected to thetransmission lines driver circuit 156 can generate a first signal and a second signal, and respectively transmit the first signal and the second signal to the first topins 152 and the second pins 154. The first pins 152 and thesecond pins 154 are evenly disposed and interleaved with each other, such that thefirst signal lines 120 and thetransmission lines first pins 152 and thesecond pins 154 do not cross over each other, and thetransmission lines substrate 110. In other words, by interleaving thefirst pins 152 and thesecond pins 154, the wiring lines that are used to electrically connect thefirst pins 152 to thefirst signal lines 120 and electrically connect thesecond pins 154 to thetransmission lines transmission lines second signal lines 122 via through holes or contact plugs. In addition, the first signal and the second signal can respectively be a data signal (for supply to data lines) and a scan signal (for supply to scan lines). The data signal and the scan signal have different voltage levels. For example, the voltage level of the data signal can be −15V, 0V, and +15V, for use in representing different gray scales, and the voltage level of the scan signal can be −20V and +22V, for use in respectively turning off or turning on transistors of a row ofpixel units 130. - In this embodiment, the
driver IC chip 150 can be an adjustable driver IC chip. Thedriver IC chip 150 can determine any pin to serve as one of thefirst pins 152 or one of thesecond pins 154 by providing this pin a different signal, such as a data signal or a scan signal, through thedriver circuit 156. That is, each pin of thedriver IC chip 150 can selectively output a data signal or a scan signal, depending on the voltage level that is provided to the pin. For example, if thedriver IC chip 150 provides a scan signal, of which the voltage level may to be −20V or +22V, to one specific pin through thedriver circuit 156, then the specific pin would serve as a scan pin used to connect to the scan lines. In other words, thedriver IC chip 150 can provide any pin with a different voltage level through thedriver circuit 156, such that the specific pin can be used to connect to the scan lines or to the data lines depending on actual requirements. For example, five voltage levels can be provided, such as −15V, 0V, +15V, −20V, +22V. - The following table shows an example of a pin allocation of the
driver IC chip 150. -
Pin Allocation Pixels 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 10 × 8 G S G S G G S G S G S G G S G S G S — — — — 12 × 8 G G S G S G G S G S G G S G S G G S G S — — 14 × 8 G G S G G S G S G G S G G S G S G G S G G S - In the table above, G indicates a scan pin and S indicates a data pin. For example, when the size of the display panel is 10×8,
pin 1 is a scan pin,pin 2 is a data pin, and so on. - Therefore, by utilizing this ability of the
driver IC chip 150 to perform control so that any specific pin can serve as a data pin or a scan pin based on actual requirements, thefirst pins 152 and thesecond pins 154 can be evenly disposed and interleaved with each other, such that thefirst signal lines 120 and thetransmission lines first pins 152 to the first to signallines 120 and electrically connect thesecond pins 154 to thetransmission lines transmission lines substrate 110. - With such a configuration of the
transmission lines display panel 100 can become thinner. Moreover, by the pin allocation of thedriver IC chip 150 mentioned above, thefirst signal lines 120 and thetransmission lines driver IC chip 150, thetransmission lines substrate 110, such that uneven brightness in an image caused by load imbalance of theactive area 112 can be avoided. - However, even with the even disposition of the
transmission lines active area 112 may still occur due to the number of thetransmission lines 140 passing through each pixel block 114 being different from each other. Hence,dummy lines 160 can be disposed to overcome such a problem in some embodiments. - In one embodiment of the present disclosure, the
display panel 100 further includes a plurality of dummy lines 160. The dummy lines 160 are evenly disposed on thesubstrate 110, parallel to thetransmission lines active area 112. In this embodiment, thetransmission lines first transmission lines 140 and a plurality ofsecond transmission lines 142. The quantity of thefirst transmission lines 140 passing through each of the pixel blocks 114 is the same. Moreover, one of thesecond transmission lines 142 or one of thedummy lines 160 passes through each of the pixel blocks 114. In other words, an equal quantity of thefirst transmission lines 140 are disposed on each column of pixel blocks 114, and due to the fact that there is an insufficient quantity of thesecond transmission lines 142 to be disposed on each column of pixel blocks 114, thedummy lines 160 are disposed on the columns of pixel blocks 114 not having thesecond transmission lines 142 passed therethrough. As a result, uneven brightness in images caused by load imbalance of theactive area 112 can be avoided. - In one embodiment of the present disclosure, the
display panel 100 further includes aperiphery circuit 170 and acontrol circuit 180. Theperiphery circuit 170 is disposed on thesubstrate 110 and around theactive area 112, and is configured to electrically connect all thedummy lines 160 to each other. Thecontrol circuit 180 is electrically connected to theperiphery circuit 170 and thedriver IC chip 150, and is configured to provide a turn-off voltage level to theperiphery circuit 170 and to drive thedriver IC chip 150. It is noted that thedrive circuit 180 can be implemented by hardware, software, or partly by hardware and partly by software. In addition, the turn-off voltage level can be the voltage level in a scan signal used to turn off the switch of thepixel unit 130, and for example, the turn-off voltage level can be −20V. - Through providing the turn-off voltage level to all the
dummy lines 160, thedummy lines 160 can act like the first andsecond transmission lines display panel 100 can avoid the uneven brightness problem in an image caused by load imbalance. In addition, by connecting all thedummy lines 160 to theperiphery circuit 170, the number of pins of thedriver IC chip 150 can be minimized, and the cost and complexity of thedriver IC chip 150 can be reduced. -
FIG. 2 is a sectional view of thedisplay panel 100 taken along line 2-2 inFIG. 1 . The orthogonal projection of the dummy lines 160 on the substrate 110 (labeled as P1), the orthogonal projection of thefirst transmission lines 140 on the substrate 110 (labeled as P2), the orthogonal projection of thesecond transmission lines 142 on the substrate 110 (labeled as P3), and the orthogonal projection of thefirst signal lines 120 on the substrate 110 (labeled as P4) are not overlapped. With such a configuration, parasitic capacitance and capacitance coupling effect can be avoided. It is noted that the configuration inFIG. 2 is just an example, and thefirst signal lines 120, thefirst transmission lines 140, thesecond transmission lines 142, and thedummy lines 160 can be disposed on different circuit layers determined on the basis of actual requirements, and the present invention is not limited by the embodiment shown inFIG. 2 . - In one embodiment of the present disclosure, due to the fact that the
second transmission lines 142 are configured to transmit the second signal while thedummy lines 160 do not transmit any signal, thesecond transmission lines 142 and thedummy lines 160 can be evenly disposed on theactive area 112, so as to avoid uneven brightness in an image caused by load imbalance of theactive area 112. - To better explain such disposition, reference will be made to
FIG. 3 toFIG. 6 , in which different embodiments are illustrated. -
FIG. 3 is a schematic diagram illustrating the disposition of thesecond transmission lines 142 and thedummy lines 160 in accordance with one embodiment of the present disclosure. Theactive area 112 is a 15×9 array built with the pixel blocks 114. Theactive area 112 has afirst edge 320 and asecond edge 330. Thefirst edge 320 and thesecond edge 330 are opposite to each other, and parallel to the dummy lines 160. In this embodiment, corresponding to the quantity of the columns of the pixel blocks 114, the quantity of thefirst transmission lines 140 is 9, and thefirst transmission lines 140 are connected to some of the second signal lines 122. Thesecond transmission lines 142 are connected to the rest of thesecond signal lines 122, that is, thesecond signal lines 122 which are not connected with thefirst transmission lines 140, and therefore the quantity of thesecond transmission lines 142 is 6. The dummy lines 160 can be disposed oncolumn second transmission lines 142 can be correspondingly disposed oncolumn active area 112 can be avoided by evenly disposing thesecond transmission lines 142 and dummy lines 160. - In this embodiment, the areas of the pixel blocks 114 that are located between two
adjacent dummy lines 160 and that are not passed through by thedummy lines 160 define a plurality ofcentral regions 310. By evenly disposing thesecond transmission lines 142 anddummy lines 160, the quantity of the pixel blocks 114 within eachcentral region 310 is the same. In this embodiment, the quantity of the pixel blocks 114 within eachcentral region 310 is 30. With to such a configuration, the load imbalance problem of theactive area 112 can be avoided. - In this embodiment, the area of the pixel blocks 114 that are located between the
first edge 320 and one of thedummy lines 160 which is nearest to thefirst edge 320 and that are not passed through by the dummy lines 160 defines afirst edge region 322, and the area of the pixel blocks 114 that are located between thesecond edge 330 and one of thedummy lines 160 which is nearest to thesecond edge 330 and that are not passed through by the dummy lines 160 defines asecond edge region 332. By evenly disposing thesecond transmission lines 142 anddummy lines 160, the quantity of the pixel blocks 114 within thefirst edge region 322 and that within thesecond edge region 332 are the same. In this embodiment, both of the quantities of the pixel blocks 114 within thefirst edge region 322 and thesecond edge region 332 are 15. It should be noted that although the quantity of the pixel blocks 114 within each of thefirst edge region 322 and thesecond edge region 332 is different from the quantity of the pixel blocks 114 within thecentral regions 310 due to the fact that uneven brightness in thefirst edge region 322 and thesecond edge region 332 is not easily visually perceivable, any negative effect that may be caused by such differences in quantities of the pixel blocks 114 in these regions is negligible. In addition, in another embodiment, the quantity of the pixel blocks 114 within each of thefirst edge region 322 and thesecond edge region 332 can be the same as the quantity of the pixel blocks 114 within thecentral regions 310. -
FIG. 4 is a schematic diagram illustrating the disposition of the second totransmission lines 142 and thedummy lines 160 in accordance with one embodiment of the present disclosure. In this embodiment, theactive area 112 is also a 15×9 array built with the pixel blocks 114, the same as the embodiment inFIG. 3 , and therefore, aspects of this embodiment that are similar to those of the previous embodiment will not be repeated herein. Theactive area 112 has afirst edge 420 and asecond edge 430. In this embodiment, thedummy lines 160 can be disposed oncolumn second transmission lines 142 can be correspondingly disposed oncolumn - The areas of pixel blocks 114 that are located between two
adjacent dummy lines 160 and that are not passed through by thedummy lines 160 define a plurality ofcentral regions 410. In this embodiment, the quantity of the pixel blocks 114 within eachcentral region 410 is 30. - The area of the pixel blocks 114 that are located between the
first edge 420 and one of thedummy lines 160 which is nearest to thefirst edge 420 and that are not be passed by the dummy lines 160 defines afirst edge region 422, and the area of the pixel blocks 114 that are located between thesecond edge 430 and one of thedummy lines 160 which is nearest to thesecond edge 430 and that are not passed through by the dummy lines 160 defines asecond edge region 432. In this embodiment, the quantity of the pixel blocks 114 within thefirst edge region 422 is 30, and the quantity of the pixel blocks 114 within thesecond edge region 432 is 0. It should be noted that although the quantity of the pixel blocks 114 within thefirst edge region 422 is the same as the quantity of the pixel blocks 114 within thecentral regions 410, while is different from the quantity of the pixel blocks 114 within thesecond edge region 432, due to the fact that uneven brightness in thefirst edge region 422 and thesecond edge region 432 is not easily visually perceivable, any negative effect that may be caused by such differences in quantities of the pixel blocks 114 in these regions is negligible. - In the embodiments described above in
FIG. 3 andFIG. 4 , theactive area 112 is divided by the dummy lines 160. However, in the following embodiments inFIG. 5 andFIG. 6 , theactive area 112 will be divided by thesecond transmission lines 142. -
FIG. 5 is a diagram illustrating the disposition of thesecond transmission lines 142 and thedummy lines 160 in accordance with one embodiment of the present disclosure. Theactive area 112 is a 12×9 array built with the pixel blocks 114. Theactive area 112 has afirst edge 520 and asecond edge 530. Thefirst edge 520 and thesecond edge 530 are opposite to each other, and parallel to the dummy lines 160. In this embodiment, corresponding to the quantity of the columns of the pixel blocks 114, the quantity of thefirst transmission lines 140 is 9, and thefirst transmission lines 140 are connected to some of the second signal lines 122. Thesecond transmission lines 142 are connected to the rest of thesecond signal lines 122, that is, thesecond signal lines 122 which are not connected with thefirst transmission lines 140, and therefore the quantity of thesecond transmission lines 142 is 3. Thesecond transmission lines 142 can be disposed oncolumn dummy lines 160 can be correspondingly disposed oncolumn active area 112 can be avoided by evenly disposing thesecond transmission lines 142 and dummy lines 160. - In this embodiment, the areas of the pixel blocks 114 that are located between two adjacent
second transmission lines 142 and that are not passed through by thesecond transmission lines 142 define a plurality ofcentral regions 510. By evenly disposing thesecond transmission lines 142 and thedummy lines 160, the quantity of the pixel blocks 114 within eachcentral region 510 is the same. In this embodiment, the quantity of the pixel blocks 114 within eachcentral region 510 is 24. With such a configuration, the load imbalance problem of theactive area 112 can be avoided. - In this embodiment, the area of the pixel blocks 114 that are located between the
first edge 520 and one of thesecond transmission lines 142 which is nearest to thefirst edge 520 and that are not passed through by thesecond transmission lines 142 defines afirst edge region 522, and the area of the pixel blocks 114 that are located between thesecond edge 530 and one of thesecond transmission lines 142 which is nearest to thesecond edge 530 and that are not passed through by thesecond transmission lines 142 defines asecond edge region 532. By evenly disposing thesecond transmission lines 142 anddummy lines 160, the quantity of the pixel blocks 114 within thefirst edge region 522 and that within thesecond edge region 532 are the same. In this embodiment, both of the quantities of the pixel blocks 114 within thefirst edge region 522 and thesecond edge region 532 are 12. It should be noted that although the quantity of the pixel blocks 114 within each of thefirst edge region 522 and thesecond edge region 532 is different from the quantity of the pixel blocks 114 within each of thecentral regions 510, due to the fact that uneven brightness in thefirst edge region 522 and thesecond edge region 532 is not easily visually perceivable, any negative effect that may be caused by such differences in quantities of the pixel blocks 114 in these regions is negligible. In addition, in another embodiment, the quantity of the pixel blocks 114 within each of thefirst edge region 522 and thesecond edge region 532 can be the same as the quantity of the pixel blocks 114 within each of thecentral regions 510. -
FIG. 6 is a diagram illustrating the disposition of thesecond transmission lines 142 and thedummy lines 160 in accordance with one embodiment of the present disclosure. In this embodiment, theactive area 112 is also a 12×9 array built with the pixel blocks 114, the same as the embodiment inFIG. 5 , and therefore, aspects of this embodiment that are similar to those of the previous embodiment will not be repeated herein. Theactive area 112 has afirst edge 620 and asecond edge 630. In this embodiment, thesecond transmission lines 142 can be disposed oncolumn dummy lines 160 can be correspondingly disposed oncolumn - The areas of the pixel blocks 114 that are located between two adjacent
second transmission lines 142 and that are not be passed through by thesecond transmission lines 142 are referring to ascentral regions 610. In this embodiment, the quantity of the pixel blocks 114 within eachcentral region 610 is 24. - The area of the pixel blocks 114 that are located between the first edge to 620 and one of the
second transmission lines 142 which is nearest to thefirst edge 620 and that are not passed through by thesecond transmission lines 142 defines afirst edge region 622, and the area of the pixel blocks 114 that are located between thesecond edge 630 and one of thesecond transmission lines 142 which is nearest to thesecond edge 630 and that are not passed through by thesecond transmission lines 142 defines asecond edge region 632. In this embodiment, the quantity of the pixel blocks 114 within thefirst edge region 622 is 24, and the quantity of the pixel blocks 114 within thesecond edge region 632 is 0. It should be noted that although the quantity of the pixel blocks 114 within thefirst edge region 622 is the same as the quantity of the pixel blocks 114 within each of thecentral regions 610, and is different from the quantity of the pixel blocks 114 within thesecond edge region 632, due to the fact that uneven brightness in thefirst edge region 622 and thesecond edge region 632 is not easily visually perceivable, any negative effect that may be caused by such differences in quantities of the pixel blocks 114 in these regions is negligible. - In accordance with the embodiments above in
FIGS. 3 , 4, 5, and 6, it should be noted that thesecond transmission lines 142 and thedummy lines 160 are evenly disposed to make the quantities of pixel blocks 114 within thecentral regions dummy lines 160 or thesecond transmission lines 142, the same. Moreover, while the pixel blocks 114 can not be passed through by thedummy lines 160 and thesecond transmission lines 142 evenly, the pixel blocks 114 associated with such unevenness can be arranged within the first andsecond edge regions active area 112, such that the areas of uneven brightness of theactive area 112 are not visually perceivable. It should be noted that the embodiments above inFIGS. 3 , 4, 5, and 6 are used to explain the idea of disposing thedummy lines 160 and thesecond transmission lines 142, and this invention is not limited by these embodiments. In addition, thefirst edge second edge active area 112, parallel to thedummy lines 160, and are not limited by the embodiments inFIGS. 3 , 4, 5, and 6. - In summary, the borders of the
display panel 100 can be made thinner by using the first andsecond transmission lines second transmission lines second transmission lines active area 112. Therefore, thefirst pins 152 and thesecond pins 154 of thedriver IC chip 150 can be evenly disposed and interleaved, so that thesecond transmission lines 142 can be evenly disposed on theactive area 112, and the capacitance coupling effect caused by stray capacitance can be avoided. Accordingly, by evenly disposing thesecond transmission lines 142 and the dummy lines 160 on theactive area 112, the uneven brightness in an image caused by load imbalance of theactive area 112 can also be avoided. Moreover, by ensuring that the orthogonal projections of thefirst signal lines 120, thefirst transmission lines 140, thesecond transmission lines 142, and the dummy lines 160 on thesubstrate 110 do not overlap, parasitic capacitance can be avoided. - It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims.
Claims (12)
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US13/733,897 US9247615B2 (en) | 2012-01-17 | 2013-01-04 | Display panel |
US14/967,384 US9780123B2 (en) | 2012-01-17 | 2015-12-14 | Display panel |
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US201261587643P | 2012-01-17 | 2012-01-17 | |
TW101123897 | 2012-07-03 | ||
TW101123897A TWI470328B (en) | 2012-01-17 | 2012-07-03 | Display panel |
TW101123897A | 2012-07-03 | ||
US13/733,897 US9247615B2 (en) | 2012-01-17 | 2013-01-04 | Display panel |
Related Child Applications (1)
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US14/967,384 Continuation US9780123B2 (en) | 2012-01-17 | 2015-12-14 | Display panel |
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US20130181605A1 true US20130181605A1 (en) | 2013-07-18 |
US9247615B2 US9247615B2 (en) | 2016-01-26 |
Family
ID=48755460
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US13/733,897 Active 2033-04-14 US9247615B2 (en) | 2012-01-17 | 2013-01-04 | Display panel |
US14/967,384 Active US9780123B2 (en) | 2012-01-17 | 2015-12-14 | Display panel |
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US14/967,384 Active US9780123B2 (en) | 2012-01-17 | 2015-12-14 | Display panel |
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Also Published As
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US9247615B2 (en) | 2016-01-26 |
CN103208248A (en) | 2013-07-17 |
US9780123B2 (en) | 2017-10-03 |
CN103208248B (en) | 2016-02-24 |
US20160099260A1 (en) | 2016-04-07 |
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