CN113689785B - Display device - Google Patents
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- CN113689785B CN113689785B CN202110510090.9A CN202110510090A CN113689785B CN 113689785 B CN113689785 B CN 113689785B CN 202110510090 A CN202110510090 A CN 202110510090A CN 113689785 B CN113689785 B CN 113689785B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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Abstract
The invention discloses a display device which is provided with a peripheral area and a display area and comprises a plurality of data lines, a plurality of scanning lines, a plurality of patch cords, a plurality of pixels and a plurality of shielding wires. The plurality of data lines extend from the peripheral region into the display region along a first direction. The plurality of scanning lines are located in the display area and extend along a second direction staggered with the first direction. The plurality of patch cords extend from the peripheral area into the display area and are respectively and electrically connected to the scanning lines. The plurality of pixels are electrically connected to the scanning line and the data line respectively, wherein the first data line and the at least two patch cords are located between two adjacent pixels. A first shielding wire of the plurality of shielding wires is positioned between the first data wire and at least two patch wires, and a second shielding wire of the plurality of shielding wires is positioned between adjacent two of the at least two patch wires.
Description
Technical Field
The present invention relates to a display device, and more particularly, to a display device having a stable data line potential.
Background
In displays produced in a profile cut, the signal sources for the gate and source need to be placed on the same side to facilitate cutting. Therefore, there are vertical gate-switching lines disposed between adjacent pixels in the display area of the display, and the gate-switching lines are generally parallel to the data lines. However, a fixed capacitance exists between the parallel and adjacent data lines and the gate patch cord, and the capacitance may cause capacitive coupling of signals, and when the gate signal is turned on or off, the potential of the data line is affected, so that the potential of the data line is changed and unstable, resulting in abnormal display brightness.
Disclosure of Invention
The invention provides a display device having a stable data line potential.
An embodiment of the present invention provides a display device having a peripheral region and a display region, and including: a plurality of data lines extending from the peripheral region into the display region, wherein the data lines extend along a first direction; the scanning lines are positioned in the display area and extend along a second direction staggered in the first direction; the plurality of patch cords extend into the display area from the peripheral area and are respectively and electrically connected to the scanning lines; the pixels are electrically connected to the scanning lines and the data lines respectively, wherein the first data line and the at least two patch cords are positioned between two adjacent pixels; and a plurality of shielding wires, wherein the first shielding wire is positioned between the first data wire and the at least two patch cords, and the second shielding wire is positioned between two adjacent patch cords.
In an embodiment of the invention, the shielding wires are electrically connected to each other.
In an embodiment of the invention, the second shielding wire has an opening.
In an embodiment of the present invention, four patch cords and five shielding wires are disposed between two adjacent pixels.
In an embodiment of the invention, the pixel includes a plurality of sub-pixels, each sub-pixel includes a switching element and a pixel electrode, the pixel electrode is electrically connected to the switching element, and the shielding wire and the pixel electrode belong to the same film layer.
In an embodiment of the invention, the display device further includes a common electrode, wherein the shielding wire is electrically connected to the common electrode.
In an embodiment of the invention, the display device further includes a dummy data line, wherein at least two patch cords are located between the first data line and the dummy data line.
In an embodiment of the invention, a third shielding wire of the shielding wires is located between the dummy data line and the patch cord.
In an embodiment of the invention, the dummy data line and the first data line are connected through a conductive layer, and the conductive layer and the scan line belong to the same film layer.
In an embodiment of the present invention, the data line, the patch cord and the dummy data line belong to the same layer.
In an embodiment of the present invention, the data line, the patch cord and the dummy data line belong to different layers.
In an embodiment of the invention, the at least two patch cords belong to different film layers.
An embodiment of the invention provides a display device having a peripheral region and a display region, the display region having a patch cord region, the patch cord region having a side region and a central region, the side region being located between the peripheral region and the central region, wherein the display device comprises: a plurality of data lines extending from the peripheral region into the display region, wherein the data lines extend along a first direction; the scanning lines are positioned in the display area and extend along a second direction staggered in the first direction; the plurality of patch cords extend into the patch cord region from the peripheral region and are respectively and electrically connected to the scanning lines; the pixels are electrically connected to the scanning lines and the data lines respectively, wherein the first data line and the at least two patch cords are positioned between two adjacent pixels; a plurality of shielding wires located in the central region; and a plurality of shielding patterns located in the central region; the first shielding wire is positioned between the first data wire and at least two patch cords, the second shielding wire is positioned between adjacent two of the at least two patch cords, each shielding pattern is positioned at the connection position of each patch cord and the corresponding scanning line, and each shielding pattern is overlapped with at least two patch cords and the corresponding scanning line at the same time.
In an embodiment of the invention, each of the shielding patterns connects the first shielding conductive line and the second shielding conductive line.
In an embodiment of the invention, the display device further includes a dummy data line, wherein at least two patch cords are located between the first data line and the dummy data line.
In an embodiment of the invention, the first data line and the dummy data line are connected in a side area.
In an embodiment of the invention, the display area further has a non-patch cord area, the non-patch cord area is located between the patch cord area and the peripheral area, and the dummy data line and the second data line are located between adjacent two of the pixels in the non-patch cord area.
In an embodiment of the invention, the second data line is electrically connected to the dummy data line.
In an embodiment of the invention, the display device further includes a plurality of common electrode lines, wherein at least two common electrode lines are located between the second data line and the dummy data line.
In an embodiment of the invention, the number of the at least two common electrode lines is the same as the number of the at least two patch cords.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic top view of a display device 10 according to an embodiment of the invention;
FIG. 2 is an enlarged view of region I of FIG. 1;
fig. 3 is a schematic top view of a display device 20 according to an embodiment of the invention;
fig. 4A is a schematic top view of a display device 30 according to an embodiment of the invention;
fig. 4B is an enlarged schematic view of a region V of the display device 30 of fig. 4A;
FIG. 4C isbase:Sub>A schematic cross-sectional view taken along section line A-A' of FIG. 4B;
fig. 5 is an enlarged view of the display device 30 of fig. 4A in the region II shown in fig. 1;
FIG. 6 is an enlarged view of the display device 30 of FIG. 4A in the area III shown in FIG. 1;
fig. 7 is an enlarged view of the display device 30 of fig. 4A in the area IV shown in fig. 1;
fig. 8A is a schematic top view of a display device 40 according to an embodiment of the invention;
FIG. 8B is a schematic cross-sectional view taken along section line B-B' of FIG. 8A;
FIG. 8C is a schematic cross-sectional view taken along section line C-C' of FIG. 8A;
fig. 9 is a schematic cross-sectional view of a display device 50 according to an embodiment of the invention.
Symbol description
10. 20, 30, 40, 50: display device
A-A ', B-B ', C-C ': section line
AA: display area
BF: buffer layer
BP: insulating layer
CA1, CA2: central zone
CH: semiconductor layer
CL, CL1, CL2: common electrode
CM1, CM2, CM3, CM4: common electrode wire
D1: first direction
D2: second direction
DC: driving circuit
DDL: dummy data line
DE: drain electrode
DL, DL1, DL2: data line
EA1, EA2: side edge region
G1, G2, G3, G4, gn: patch cord
GE: grid electrode
GI: gate insulating layer
GL, GL1: scanning line
I. II, III, IV, V, VI: region(s)
M0, M1, M2, M3, M4: conductive layer
ML1, ML2, ML3: conducting wire
NA: peripheral region
NTA: non-patch cord region
O2, O4: an opening
P1: conductive pattern
P2: conductive pattern
PE: pixel electrode
PV: passivation layer
PX, PX1, PX2: pixel arrangement
S1, S2, S3, S4, S5, S6, S7, sn: shielded conductor
S21, S22, S41, S42: sub-wire
SB: substrate board
SE: source electrode
SM: shielding pattern
SM1, SM2: shielding block
SP: sub-pixel
SW: switching element
TA: patch cord region
V1, V2, V3, V4, V5, V6: through hole
Detailed Description
Fig. 1 is a schematic top view of a display device 10 according to an embodiment of the invention. Fig. 2 is an enlarged view of region I in fig. 1. The display device 10 has a peripheral area NA and a display area AA. The display device 10 includes a plurality of data lines DL, a plurality of scan lines GL, a plurality of transfer lines Gn, a plurality of pixels PX, and a plurality of shielding wires Sn. The data lines DL extend from the peripheral area NA into the display area AA, wherein the data lines DL extend along the first direction D1. The scan lines GL are disposed in the display area AA and extend along a second direction D2, wherein the second direction D2 is staggered with the first direction D1. The plurality of patch cords Gn extend from the peripheral area NA into the display area AA and are electrically connected to the scan lines GL, respectively. The plurality of pixels PX are electrically connected to the scan line GL and the data line DL, respectively, wherein the data line DL1 and the at least two switching lines Gn are located between two adjacent pixels PX in the plurality of pixels PX. The shielding wire S1 of the plurality of shielding wires Sn is located between the data line DL1 and the patch cords Gn, and the shielding wire S2 is located between two adjacent patch cords Gn.
In the present embodiment, the shielding wire S1 is used to separate the patch cord Gn from the data line DL1, so as to reduce capacitive coupling between the patch cord Gn and the data line DL1, thereby avoiding variation in the potential of the data line DL1 and enabling the data line DL1 to have a stable potential. In addition, the shielding wires S2 between the adjacent patch cords Gn can make the loads of the patch cords Gn relatively similar, so as to avoid uneven brightness of the display device 10.
Hereinafter, embodiments of the respective elements and the film layers of the display device 10 will be described with reference to the drawings, but the present invention is not limited thereto.
Referring to fig. 1, in the present embodiment, the display device 10 is circular in shape, but the present invention is not limited thereto. In some embodiments, the display device 10 may have a rectangular, oval, polygonal, or irregular shape, and the shape of the display device 10 may be selected as desired.
The display device 10 may have a peripheral area NA and a display area AA, and the peripheral area NA surrounds the display area AA. In the present embodiment, the display device 10 further includes a driving circuit DC located in the peripheral area NA. In the embodiment, the display device 10 is driven on a single side, and the driving circuit DC is located on the upper side of the display area AA, but the invention is not limited thereto. In some embodiments, the display device 10 may be dual-sided driving, and the driving circuit DC may be located at the upper and lower sides or the left and right sides of the display area AA.
In this embodiment, the display area AA may have a patch cord area TA and a non-patch cord area NTA, where the patch cord area TA is an area where the patch cord Gn is disposed, and the patch cord Gn is not disposed in the non-patch cord area NTA. In this embodiment, the patch cord area TA is located in the central area of the display area AA, and the non-patch cord area NTA is located at two sides of the patch cord area TA, but the present invention is not limited thereto, and the configuration of the patch cord area TA and the non-patch cord area NTA may be changed as required. In this embodiment, the patch cord area TA may have a side area EA1 and a central area CA1, wherein the side area EA1 is located between the peripheral area NA and the central area CA 1. The non-patch cord region NTA may have a side region EA2 and a central region CA2, and the side region EA2 may be located between the peripheral region NA and the central region CA 2.
Referring to fig. 1 and 2, the display device 10 includes a plurality of data lines DL, a plurality of scan lines GL, a plurality of patch cords Gn, a plurality of pixels PX, and a plurality of shielding wires Sn on a substrate SB. The data line DL is electrically connected to the driving circuit DC. For example, the data line DL is electrically connected to a source driving element (not depicted) in the driving circuit DC. The data lines DL extend from the peripheral area NA into the display area AA, the data lines DL located in the display area AA extend along the first direction D1, and the data lines DL located in the peripheral area NA may not be parallel to each other.
The scanning line GL is located in the display area AA and extends along a second direction D2 that is staggered with the first direction D1. The transfer lines Gn extend from the peripheral area NA into the transfer line area TA of the display area AA, and one ends of the transfer lines Gn are electrically connected to the scan lines GL, respectively, and the other ends of the transfer lines Gn are electrically connected to the driving circuit DC, for example, the transfer lines Gn may be electrically connected to gate driving elements (not shown) in the driving circuit DC. In this way, the patch lines Gn can respectively transmit the gate driving signals from the driving circuits DC to the corresponding scan lines GL.
Referring to fig. 2, in the present embodiment, the display device 10 includes a plurality of sub-pixels SP, and each sub-pixel SP is electrically connected to a corresponding scan line GL and a data line DL. For example, each sub-pixel SP includes a switching element SW and a pixel electrode PE electrically connected to the switching element SW, wherein the switching element SW is electrically connected to a corresponding one of the scan lines and a corresponding one of the data lines. In the present embodiment, the sub-pixels SP include red sub-pixels, green sub-pixels, and blue sub-pixels. For example, the sub-pixel SP overlapping the red filter element (not shown) is a red sub-pixel, the sub-pixel SP overlapping the green filter element (not shown) is a green sub-pixel, and the sub-pixel SP overlapping the blue filter element (not shown) is a blue sub-pixel. In the present embodiment, the sub-pixels SP are arrayed into a plurality of pixels PX. For example, each pixel PX includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel. In some embodiments, each pixel PX may also include sub-pixels of other colors. In the present embodiment, each pixel PX includes three sub-pixels SP, and each pixel PX is electrically connected to one scan line and three data lines.
In the patch cord area TA, one data line DL and at least two patch cords Gn may be disposed between two adjacent pixels PX. For example, in the present embodiment, one data line DL1 and four patch cords G1 to G4 are disposed between two adjacent pixels PX1, PX 2. In some embodiments, one data line DL1 and three patch lines Gn may be disposed between adjacent pixels PX1 and PX 2. In some embodiments, one data line DL and five patch lines Gn may be disposed between adjacent pixels PX1 and PX 2.
In the present embodiment, the data line DL1 is located between the pixel PX1 and the patch cord G1. The display device 10 may further include a dummy data line DDL, and the switching lines G1 to G4 are located between the data line DL1 and the dummy data line DDL, and the dummy data line DDL is located between the switching line G4 and the pixel PX 2. In the embodiment, the data line DL1, the patch cords G1 to G4 and the dummy data line DDL may belong to the same layer, but the invention is not limited thereto. By providing the dummy data line DDL, the capacitive coupling generated between the data line DL1 and the pixel PX1 can be offset by the capacitive coupling between the dummy data line DDL and the pixel PX 2.
In the central area CA1 of the patch cord area TA, a plurality of shielding wires Sn of the display device 10 may be disposed between the data lines DL1, the patch cords G1 to G4, and the dummy data line DDL, respectively. For example, in the present embodiment, the display device 10 includes three shielding wires S1 to S3, wherein the shielding wire S1 is located between the data line DL1 and the patch cord G1; the shielding wire S2 is positioned between the patch cord G2 and the patch cord G3; and the shielding wire S3 is located between the patch cord G4 and the dummy data line DDL, but the invention is not limited thereto. In this way, the shielding wire S1 can separate the data line DL1 from the patch cord G1 to reduce capacitive coupling between the data line DL1 and the patch cord G1, and the shielding wire S2 and the shielding wire S3 can make loads of the patch cords G2 to G4 close to the patch cord G1, so as to avoid uneven brightness.
Fig. 3 is a schematic top view of a display device 20 according to an embodiment of the invention. The display device 20 shown in fig. 3 is different from the display device 10 shown in fig. 1 to 2 in that: the display device 20 includes five shielding wires S1 to S5, wherein the shielding wire S1 is located between the data line DL1 and the patch cord G1; the shielding wire S2 is positioned between the patch cord G1 and the patch cord G2; the shielding wire S3 is positioned between the patch cord G2 and the patch cord G3; the shielding wire S4 is positioned between the patch cord G3 and the patch cord G4; and the shielding conductive line S5 is located between the patch cord G4 and the dummy data line DDL. The shielding wires Sn are arranged among any two of the data line DL1, the switching wires G1-G4 and the dummy data line DDL, so that the loads of the switching wires G1-G4 can be comprehensively homogenized, and the situation that uneven loads are caused by slight alignment deviation in the manufacturing process is avoided.
Fig. 4A is a schematic top view of a display device 30 according to an embodiment of the invention. Fig. 4B is an enlarged schematic view of region V of the display device 30 of fig. 4A. Fig. 4C isbase:Sub>A schematic cross-sectional view taken along section linebase:Sub>A-base:Sub>A' of fig. 4B. The display device 30 shown in fig. 4A to 4C is different from the display device 20 of fig. 3 in that: the shielding wire S2 has an opening O2, the shielding wire S4 has an opening O4, wherein the shielding wire S2 includes a sub-wire S21 and a sub-wire S22, and the opening O2 is located between the sub-wire S21 and the sub-wire S22; meanwhile, the shielding wire S4 includes a sub-wire S41 and a sub-wire S42, and the opening O4 is located between the sub-wire S41 and the sub-wire S42. In the present embodiment, the openings O2, O4 can reduce the capacitance between the shielding wire S2 and the shielding wire S4 and the nearby conductive layer, and avoid the occurrence of short-circuits between the shielding wire S2 and the shielding wire S4 and the nearby conductive layer.
Referring to fig. 4B and fig. 4C, in the present embodiment, the switching element SW includes a gate electrode GE, a semiconductor layer CH, a source electrode SE and a drain electrode DE. The region of the gate electrode GE overlapping the semiconductor layer CH overlapping the gate electrode GE may be regarded as a channel region of the switching element SW. The source SE and the drain DE of the switching element SW are separated from each other, and the source SE and the drain DE are respectively in contact with the semiconductor layer CH. The pixel electrode PE is electrically connected to the drain electrode DE. The switching element SW may be turned on or off by a signal transmitted from the scan line GL, and the switching element SW may transmit a signal transmitted from the data line DL to the pixel electrode PE when turned on.
The source SE and the drain DE of the switching element SW may belong to the same layer, and the materials of the source SE, the drain DE and the gate GE of the switching element SW may include metals with good conductivity, such as metals of aluminum, molybdenum, titanium, etc., but the invention is not limited thereto. In order to avoid unnecessary short circuit between the respective members, a gate insulating layer GI is provided between the gate electrode GE and the semiconductor layer CH, and a passivation layer PV is provided between the pixel electrode PE and the film layer forming the source electrode SE and the drain electrode DE. Although the gate electrode GE in the present embodiment is located under the semiconductor layer CH, the switching element SW is a bottom gate transistor. However, in other embodiments, the gate electrode GE may also be located above the semiconductor layer CH, so that the switching element SW is a top gate transistor.
In this embodiment, the shielding wires S1 to S5 and the pixel electrode PE belong to the same film layer, and the shielding wires S1 to S5 are made of transparent conductive material. In some embodiments, the shielding wires S1 to S5 may use an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material or other suitable materials, or a stacked layer of the above conductive materials, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide or other suitable oxides, or a stacked layer of at least two of the above, but the present invention is not limited thereto.
The display device 30 further includes a common electrode CL, and the shield wires S1 to S5 are electrically connected to the common electrode CL, respectively, and thus, the shield wires S1 to S5 have the same potential as the common electrode CL. For example, in the present embodiment, the common electrode CL includes a common electrode CL1 and a common electrode CL2, and the common electrode CL1 and the common electrode CL2 are respectively located at two sides of the scan line GL. The shield wires S1 to S5 may be electrically connected to each other through the wire ML1, and the wire ML1 may be connected to the common electrode CL1 through the via hole V1. In addition, the conductive line ML1 may also be connected to the conductive line ML2 through the via hole V2, and the conductive line ML2 may be connected to the common electrode CL2 through the via hole V3, the conductive line ML3, and the via hole V4, so that the common electrode CL1 and the common electrode CL2 may be connected to form a mesh electrode. In this way, the common electrode CL1 and the common electrode CL2 can be electrically connected even after the display device 30 is subjected to the profile cutting.
Fig. 5 is an enlarged view of the display device 30 of fig. 4A in the region II shown in fig. 1. In the side area EA1 of the patch cord area TA of the display device 30, the dummy data line DDL and the data line DL1 are connected through the conductive layer M1 so that the dummy data line DDL and the data line DL1 have the same potential. In some embodiments, the conductive layer M1 and the scan line GL belong to the same layer, but the invention is not limited thereto. In some embodiments, the data line DL1 may be connected to the conductive layer M1 through the conductive pattern P1, and the dummy data line DDL may be connected to the conductive layer M1 through the conductive pattern P2. The conductive patterns P1 and P2 may belong to the same layer as the shielding wires S1 to S5 of the display device 30 of fig. 4A, and the shielding wires S1 to S5 do not extend to the side area EA1 to avoid short-circuiting with the conductive patterns P1 and P2.
Fig. 6 is an enlarged view of the display device 30 of fig. 4A in the area III shown in fig. 1. In this embodiment, in the central area CA1 of the patch cord area TA, the patch cords G1 to G4 may be connected to four scan lines GL, where each of the patch cords G1 to G4 is connected to a corresponding one of the scan lines GL. The four scan lines GL connected to the patch lines G1 to G4 may be sequentially arranged along the first direction D1, but the present invention is not limited thereto. In addition, a shielding pattern SM may be provided where the patch lines G1 to G4 are connected to the scanning lines GL.
For example, in the present embodiment, the shielding pattern SM is located between the data line DL1 and the dummy data line DDL, and the shielding pattern SM may include a shielding block SM1 and a shielding block SM2.
In some embodiments, the shielding block SM1 is connected to the shielding wires S1 to S5, and the shielding block SM1 overlaps the common electrode CL1, the common electrode CL2, the patch cords G1 to G4, and the scan line GL1 at the same time. The shield block SM1 is used to cover the patch cords G1 to G4, so that the electric fields of the patch cords G1 to G4 can be prevented from affecting the adjacent pixel electrodes PE. In some embodiments, the patch cord G1 may be connected to the shielding block SM2 through the via V5, and the shielding block SM2 may be connected to the scan line GL1 through the via V6. Since the via hole V5 and the via hole V6 are formed by the conventional manufacturing process, the manufacturing process step and the photomask for forming the via hole in the overlapping region VI of the interposer G1 and the scan line GL1 can be omitted.
Fig. 7 is an enlarged view of the display device 30 of fig. 4A in the area IV shown in fig. 1. In this embodiment, the non-patch cord region NTA is located between the patch cord region TA and the peripheral region NA. In the non-patch cord region NTA, a data line DL2 and a dummy data line DDL may be disposed between adjacent pixels, and the data line DL2 and the dummy data line DDL are electrically connected in the side area EA 2.
Because the non-patch cord area NTA is not provided with the patch cord Gn, a plurality of common electrode lines may be disposed between the data line DL2 and the dummy data line DDL in the non-patch cord area NTA, and the number of the common electrode lines may be the same as the number of the patch cords between adjacent pixels in the patch cord area TA, so that the capacitive load of the non-patch cord area NTA is similar to the patch cord area TA. For example, in the present embodiment, four common electrode lines CM1, CM2, CM3, CM4 are disposed between the data line DL2 and the dummy data line DDL.
In addition, a shielding wire S6 may be disposed between the data line DL2 and the common electrode line CM1, and a shielding wire S7 may be disposed between the dummy data line DDL and the common electrode line CM4 to reduce capacitive coupling between the common electrode lines CM1, CM4 and the data line DL2 and the dummy data line DDL, thereby avoiding variations in the potential of the data line DL2 and the dummy data line DDL and enabling the data line DL2 to have a stable potential.
Fig. 8A is a schematic top view of a display device 40 according to an embodiment of the invention. FIG. 8B is a schematic cross-sectional view taken along section line B-B' of FIG. 8A. Fig. 8C is a schematic cross-sectional view taken along section line C-C' of fig. 8A. The display device 40 shown in fig. 8A to 8C is different from the display device 20 shown in fig. 3 in that: in the central area CA1 of the patch cord area TA, the data line DL1, the patch cords G1 to G4, and the dummy data line DDL belong to different film layers.
For example, in the present embodiment, the patch cord G1, the patch cord G3 and the dummy data line DDL belong to the conductive layer M0, and the data line DL1, the patch cord G2 and the patch cord G4 belong to the conductive layer M2. Therefore, the patch cords G1 to G4 also belong to different film layers. The conductive layer M0 is disposed on the substrate SB, the buffer layer BF and the gate insulating layer GI are disposed between the conductive layer M0 and the conductive layer M2, and the passivation layer PV is disposed on the conductive layer M2. Any adjacent wires in the data line DL1, the switching lines G1-G4 and the dummy data line DDL all belong to different film layers, so that the possibility of short circuit of the adjacent wires due to manufacturing process errors can be eliminated, and the distance between the adjacent wires is minimized.
Referring to fig. 8C, in the side area EA1 of the patch cord area TA of the display device 40, the dummy data line DDL and the data line DL1 are connected through the conductive layer M4 so that the dummy data line DDL and the data line DL1 have the same potential.
Fig. 9 is a schematic cross-sectional view of a display device 50 according to an embodiment of the invention. The display device 50 shown in fig. 9 is different from the display device 40 shown in fig. 8B in that: the patch cords G1, G3 and DDL belong to the conductive layer M3, and the data lines DL1, G2 and G4 belong to the conductive layer M2.
In the present embodiment, the gate insulating layer GI is disposed on the substrate SB, the conductive layer M2 is disposed on the gate insulating layer GI, the passivation layer PV is disposed between the conductive layer M2 and the conductive layer M3, and the insulating layer BP is disposed on the conductive layer M3. Any adjacent wires in the data line DL1, the switching lines G1-G4 and the dummy data line DDL all belong to different film layers, so that the possibility of short circuit of the adjacent wires due to manufacturing process errors can be eliminated, and the distance between the adjacent wires is minimized.
In summary, the present invention uses the shielding wire to separate the patch cord and the data line, so as to reduce capacitive coupling between the patch cord and the data line, and avoid the potential variation of the data line, so that the potential of the data line can be kept stable. In addition, the shielding wires are arranged between the adjacent patch cords, so that the loads of the patch cords are similar, and uneven brightness of the display device can be avoided.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather, it should be apparent to those skilled in the art that various changes and modifications can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (20)
1. A display device having a peripheral region and a display region, the display device further comprising:
a plurality of data lines extending from the peripheral region into the display region, wherein the data lines extend along a first direction;
a plurality of scanning lines located in the display area and extending along a second direction staggered with the first direction;
the plurality of patch cords extend from the peripheral area into the display area and are respectively and electrically connected to the scanning lines;
the pixels are respectively and electrically connected to the scanning lines and the data lines, wherein the first data line and the at least two patch cords are positioned between two adjacent pixels; and
and the second shielding wire is positioned between two adjacent two of the at least two patch cords.
2. The display device of claim 1, wherein the shielding wires are electrically connected to each other.
3. The display device of claim 1, wherein the second shielding wire has an opening.
4. The display device of claim 1, wherein four patch cords and five shielding wires are disposed between two adjacent pixels.
5. The display device of claim 1, wherein each of the pixels comprises a plurality of sub-pixels, each of the sub-pixels comprises a switching element and a pixel electrode electrically connected to the switching element, and the shielding wires and the pixel electrode belong to the same layer.
6. The display device of claim 1, further comprising a common electrode, wherein the shielding wires are electrically connected to the common electrode.
7. The display device of claim 1, further comprising a dummy data line, wherein the at least two patch cords are located between the first data line and the dummy data line.
8. The display device of claim 7, wherein a third one of the shielding wires is located between the dummy data line and the at least two patch cords.
9. The display device of claim 7, wherein the dummy data line and the first data line are connected through a conductive layer, and the conductive layer and the scan lines belong to the same layer.
10. The display device of claim 7, wherein the data lines, the patch lines, and the dummy data lines are of the same film layer.
11. The display device of claim 7, wherein the data lines, the patch lines, and the dummy data lines belong to different layers.
12. The display device of claim 11, wherein the at least two patch cords belong to different layers.
13. A display device having a peripheral region and a display region, wherein the display region has a patch cord region having a side region and a central region, the side region being located between the peripheral region and the central region, wherein the display device comprises:
a plurality of data lines extending from the peripheral region into the display region, wherein the data lines extend along a first direction;
a plurality of scanning lines located in the display area and extending along a second direction staggered with the first direction;
the plurality of patch cords extend into the patch cord region from the peripheral region and are respectively and electrically connected to the scanning lines;
the pixels are respectively and electrically connected to the scanning lines and the data lines, wherein the first data line and the at least two patch cords are positioned between two adjacent pixels;
a plurality of shielding wires located in the central region; and
a plurality of shielding patterns located at the central region;
the first shielding wire is positioned between the first data wire and the at least two switching wires, the second shielding wire is positioned between adjacent two of the at least two switching wires, each shielding pattern is positioned at the connection position of each switching wire and the corresponding scanning wire, and each shielding pattern simultaneously overlaps the at least two switching wires and the corresponding scanning wire.
14. The display device of claim 13, wherein each of the shielding patterns connects the first shielding conductive line and the second shielding conductive line.
15. The display device of claim 13, further comprising a dummy data line, wherein the at least two patch cords are located between the first data line and the dummy data line.
16. The display device of claim 15, wherein the first data line and the dummy data line are connected at the side region.
17. The display device of claim 15, wherein the display region further has a non-patch cord region between the patch cord region and the peripheral region, the dummy data line and the second data line being between adjacent two of the pixels in the non-patch cord region.
18. The display device of claim 17, wherein the second data line is electrically connected to the dummy data line.
19. The display device of claim 17, further comprising a plurality of common electrode lines, wherein at least two common electrode lines are located between the second data line and the dummy data line.
20. The display device of claim 19, wherein the at least two common electrode lines are the same as the at least two patch cords.
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| US202063027026P | 2020-05-19 | 2020-05-19 | |
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| US63/060,259 | 2020-08-03 | ||
| TW110103330A TWI756040B (en) | 2020-05-19 | 2021-01-28 | Display device |
| TW110103330 | 2021-01-28 |
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| CN113689785A CN113689785A (en) | 2021-11-23 |
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| CN102129143A (en) * | 2010-12-15 | 2011-07-20 | 华映视讯（吴江）有限公司 | Pixel array substrate and manufacturing method thereof |
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| JP5203447B2 (en) * | 2008-02-27 | 2013-06-05 | シャープ株式会社 | Active matrix substrate |
| JP5247312B2 (en) * | 2008-09-01 | 2013-07-24 | 株式会社ジャパンディスプレイウェスト | Liquid crystal display |
| US8363192B2 (en) * | 2008-09-18 | 2013-01-29 | Japan Display Central Inc. | Liquid crystal display device |
| CN101561609B (en) * | 2009-06-08 | 2010-10-13 | 友达光电股份有限公司 | Active array substrate, liquid crystal display panel and method for manufacturing active array substrate |
| US20130100005A1 (en) * | 2011-10-19 | 2013-04-25 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | LCD Panel and Method of Manufacturing the Same |
| CN103208248B (en) * | 2012-01-17 | 2016-02-24 | 元太科技工业股份有限公司 | Display panel |
| JP6131662B2 (en) * | 2013-03-22 | 2017-05-24 | セイコーエプソン株式会社 | Display device and electronic device |
| TWI519878B (en) * | 2014-12-25 | 2016-02-01 | 友達光電股份有限公司 | Display panel and method of making the same |
| CN204331575U (en) * | 2015-01-12 | 2015-05-13 | 北京精英智通科技股份有限公司 | A kind of liquid crystal display |
| KR102528296B1 (en) * | 2015-11-18 | 2023-05-04 | 삼성디스플레이 주식회사 | Ddisplay apparatus |
| CN105372891B (en) * | 2015-12-04 | 2019-03-08 | 上海天马微电子有限公司 | A kind of array substrate and display device |
| CN105652498A (en) * | 2016-03-22 | 2016-06-08 | 上海中航光电子有限公司 | Array substrate, touch display panel and touch display device |
| TWI613487B (en) * | 2016-03-28 | 2018-02-01 | 友達光電股份有限公司 | Curved display panel |
| JP6776060B2 (en) * | 2016-08-29 | 2020-10-28 | 株式会社ジャパンディスプレイ | Display device |
| KR102544323B1 (en) * | 2016-11-08 | 2023-06-19 | 삼성디스플레이 주식회사 | Display device |
| CN113689785B (en) * | 2020-05-19 | 2023-04-25 | 友达光电股份有限公司 | Display device |
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