CN107290903B - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN107290903B CN107290903B CN201710630290.1A CN201710630290A CN107290903B CN 107290903 B CN107290903 B CN 107290903B CN 201710630290 A CN201710630290 A CN 201710630290A CN 107290903 B CN107290903 B CN 107290903B
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- source driver
- electrically connected
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
Abstract
The embodiment of the invention provides an array substrate, a display panel and a display device. On the one hand, the array substrate comprises a plurality of source electrode driving chips, a plurality of pins of one source electrode driving chip are respectively and electrically connected with different connecting wires, and different connecting wires are electrically connected with different data lines, wherein the substrate comprises a plurality of display subregions, each display subregion comprises a data line corresponding to the connecting wire electrically connected with the plurality of source electrode driving chips, namely, the data line electrically connected with each source electrode driving chip is arranged in each display subregion, after the design is adopted, because the driving signals transmitted in different display subregions are the same, when each display subregion of the display panel displays the same gray scale picture, different display subregions can display the same gray scale picture, and the display effect of the display panel is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
In the prior art, the display panel includes a plurality of source driver chips, each corresponding to a region of the display panel, and a plurality of data lines electrically connected to one of the source driver chips are located in the region corresponding to the source driver chip, for example, the display panel includes three source driver chips, namely, a source driver chip 1, a source driver chip 2, and a source driver chip 3, the display panel includes three regions, namely, a region 1, a region 2, and a region 3, the source driver chip 1 corresponds to the region 1, the source driver chip 2 corresponds to the region 2, the source driver chip 3 corresponds to the region 3, the data lines electrically connected to the source driver chip 1 are located in the region 1, the data lines electrically connected to the source driver chip 2 are located in the region 2, and the data lines electrically connected to the source driver chip 3 are located in the region 3, the voltage levels of different source electrode driving chips are different due to the process errors among different source electrode driving chips, when each area of the display panel displays the same gray scale picture, the gray scale pictures displayed by different areas are different due to the difference of driving signals provided by different source electrode driving chips, and when the load on the data line transmission line is large, the attenuation of the driving signals transmitted by the data line is large, so that the difference of the gray scale pictures displayed by different areas is more obvious, and the display effect of the display panel is influenced.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a display panel and a display device, which are used for solving the problem that in the prior art, when each area of the display panel displays the same gray scale picture, the gray scale pictures displayed in different areas are different, and the display effect of the display panel is influenced.
In one aspect, an embodiment of the present invention provides an array substrate, where the array substrate includes:
a substrate base including a display area and a non-display area surrounding the display area;
the data lines are positioned on the substrate base plate and in the display area, extend along a first direction and are arranged along a second direction, and the first direction and the second direction are perpendicular to each other;
a plurality of connection wires located on the substrate and within the non-display area, the plurality of connection wires being electrically connected to different data lines, respectively;
the source driving chips are positioned on the substrate and in the non-display area, the source driving chips are arranged along the second direction, each source driving chip comprises a plurality of pins, and each pin is electrically connected with different connecting wires;
the display area comprises a plurality of display sub-areas, the display sub-areas extend along a first direction and are arranged along a second direction, and each display sub-area comprises a data line corresponding to a connecting wire electrically connected with the source electrode driving chips.
Optionally, the data lines corresponding to the connection wires electrically connected to the plurality of pins of different source driver chips are alternately arranged in turn in each display sub-region.
Optionally, the plurality of source driver chips include a first source driver chip and a second source driver chip, and the connection wires electrically connected to the first source driver chip and the connection wires electrically connected to the second source driver chip are located in different layers.
Optionally, the connection wires electrically connected to the first source driver chip are located at the same layer as the plurality of data lines.
Optionally, the connection wires electrically connected to the second source driver chip are electrically connected to the corresponding data lines through different first via holes, respectively.
Optionally, the connecting wires electrically connected to the second source driver chips are electrically connected to the pins of the corresponding second source driver chips through different second via holes, respectively.
Optionally, the connecting wires electrically connected to the first source driver chips are electrically connected to the corresponding pins of the first source driver chips through different third via holes, respectively.
Optionally, the plurality of source driver chips are located on one side of the substrate base plate extending along the second direction.
Optionally, the plurality of source driver chips are located on two sides of the substrate base plate extending along the second direction.
Optionally, the source driver chips on the first side and the source driver chips on the second side are sequentially arranged in a staggered manner along the first direction.
Optionally, the source driver chips located on the first side and the source driver chips located on the second volume are correspondingly arranged along the first direction.
In another aspect, an embodiment of the invention provides a display panel, which includes the array substrate.
In another aspect, an embodiment of the present invention provides a display device, including the display panel as described above.
Any one of the above technical solutions has the following beneficial effects:
in the embodiment of the invention, the substrate comprises a plurality of source driving chips, a plurality of pins of one source driving chip are respectively and electrically connected with different connecting wires, and different connecting wires are electrically connected with different data lines, wherein the substrate comprises a plurality of display subregions, each display subregion comprises data lines corresponding to the connecting wires electrically connected with the plurality of source driving chips, namely, the data lines electrically connected with the source driving chips are arranged in each display subregion, after the design is adopted, the data lines arranged in each display subregion can transmit driving signals output by each source driving chip, so that the driving signals transmitted in different display subregions are the same, and further, when each display subregion of the display panel displays the same gray scale picture, different display subregions can display the same gray scale picture, and when the load on the data line transmission line is larger, the attenuation amounts of the data lines electrically connected with the same source drive chip in different display subareas are the same, so that different display subareas can display the same gray-scale picture, and the display effect of the display panel is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a top view of an array substrate according to an embodiment of the present invention;
fig. 2 is a top view of another array substrate according to an embodiment of the present invention;
fig. 3 is a top view of another array substrate according to an embodiment of the present invention;
fig. 4 is a top view of another array substrate according to an embodiment of the present invention;
fig. 5 is a top view of another array substrate according to an embodiment of the present invention;
fig. 6 is a top view of another array substrate according to an embodiment of the present invention;
fig. 7 is a schematic view of a display device according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be noted that the terms "upper", "lower", "left", "right", and the like used in the description of the embodiments of the present invention are used in the angle shown in the drawings, and should not be construed as limiting the embodiments of the present invention. In addition, in this context, it is also to be understood that when an element is referred to as being "on" or "under" another element, it can be directly formed on "or" under "the other element or be indirectly formed on" or "under" the other element through an intermediate element.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
As shown in fig. 1 (only a case that four source driver chips are included and each source driver chip is electrically connected to corresponding four data lines is illustrated), fig. 1 is a top view of an array substrate according to an embodiment of the present invention, where the array substrate includes: a substrate 11, the substrate 11 including a display region 1 and a non-display region 2 surrounding the display region 1; a plurality of data lines 12, the plurality of data lines 12 being located on the substrate 11 and in the display region 1, the plurality of data lines 12 extending along a first direction Y and being arranged along a second direction X, the first direction Y and the second direction X being perpendicular to each other; a plurality of connection wires 13, the plurality of connection wires 13 being located on the substrate 11 and in the non-display region 2, the plurality of connection wires 13 being electrically connected to different data lines 12, respectively; the source driving chips are located on the substrate 11 and in the non-display area 2, the source driving chips are arranged along the second direction X, each source driving chip comprises a plurality of pins, and each pin is electrically connected with different connecting wires 13; the display area 1 includes a plurality of display sub-areas, the display sub-areas extend along a first direction Y and are arranged along a second direction X, and each display sub-area includes a data line 12 corresponding to a connection wire 13 electrically connected to the source driver chips.
Specifically, as shown in fig. 1, the non-display area 2 of the substrate 11 includes four source driver chips, namely a source driver chip 141, a source driver chip 142, a source driver chip 143, and a source driver chip 144, each source driver chip corresponds to four data lines 12, and the display area 1 of the substrate 11 includes four display sub-areas: the display sub-region a, the display sub-region B, the display sub-region C and the display sub-region D, wherein the four data lines 12 corresponding to each source driver chip are respectively located in the four display sub-regions, that is, the display sub-region a, the display sub-region B, the display sub-region C and the display sub-region D all include a data line 12 corresponding to a source driver chip 141, a data line 12 corresponding to a source driver chip 142, a data line 12 corresponding to a source driver chip 143 and a data line 12 corresponding to a source driver chip 144, after the above design is adopted, the display sub-region a includes the four data lines 12, and the four data lines 12 can respectively transmit the driving signals output by the source driver chip 141, the driving signals output by the source driver chip 142, the driving signals output by the source driver chip 143 and the driving signals output by the source driver chip 144, similarly, the display sub-region B, the display sub-region C and the display sub-region D respectively include four data lines 12, and the four data lines 12 in each display sub-region can respectively transmit the driving signal output by the source driver chip 141, the driving signal output by the source driver chip 142, the driving signal output by the source driver chip 143 and the driving signal output by the source driver chip 144, so that the driving signals transmitted in the display sub-region a, the display sub-region B, the display sub-region C and the display sub-region D are the same, that is, the driving signals output by the source driver chip 141, the driving signals output by the source driver chip 142, the driving signals output by the source driver chip 143 and the driving signals output by the source driver chip 144 can be transmitted in the display sub-region a, the display sub-region B, the display sub-region C and the display sub-region D, so that when the display panel displays the, the display sub-area a, the display sub-area B, the display sub-area C, and the display sub-area D can display the same gray scale picture, and when the load on the transmission line of the data line 12 is large, since the driving signals transmitted in the data lines 12 electrically connected to the same source driving chip are the same, therefore, the data lines 12 electrically connected to the same source driver chip have the same attenuation amount in different display sub-regions, furthermore, different display sub-regions can still display the same gray scale picture, thereby improving the display effect of the display panel, in one display sub-area, because the data lines 12 connected with different source driving chips are alternately arranged and the gray scale picture corresponding to each data line 12 can not be identified by human eyes, therefore, when the display sub-regions of the display panel display the same gray scale image, the display effect of the display panel is not affected.
As shown in fig. 1, since the connecting wires 13 and the source driver chips are located in the non-display region 2, and the non-display region 2 is not used for displaying, the arrangement of the connecting wires 13 and the source driver chips does not affect the normal display of the display panel after the above design is adopted.
As shown in fig. 1, the array substrate further includes a plurality of scan lines (not shown) extending along the second direction X and arranged along the second direction X, the plurality of scan lines and the plurality of data lines 12 are crossed and insulated to form a plurality of sub-pixel units (not shown), each of the sub-pixel units includes a thin film transistor (not shown) and a pixel electrode (not shown), the source electrode of the thin film transistor is electrically connected to the corresponding data line 12, the drain electrode of the thin film transistor is electrically connected to the corresponding pixel electrode through a via hole, the grid electrode of the thin film transistor is electrically connected with the corresponding scanning line, after the thin film transistor switch corresponding to the pixel electrode is opened through the scanning line, the source electrode and the drain electrode of the thin film transistor are conducted, the corresponding data line 12 charges the corresponding pixel electrode via the source and drain electrodes of the thin film transistor switch, making the pixel electrode have a certain potential. The liquid crystal molecules in the liquid crystal layer can be controlled to rotate by adjusting the potential difference between the pixel electrode and the common electrode (not shown), so that the display function of the display panel is realized. When each source driver chip has no process error, the driving signals transmitted in the data lines 12 are the same when displaying the same gray scale image, and the driving signals transmitted in the data lines 12 corresponding to different gray scale images are different when displaying different gray scale images.
It should be noted that fig. 1 only shows one arrangement of the plurality of source driver chips, and other arrangements may also be included, and a specific arrangement is set according to actual needs and is not specifically limited herein. For example, as shown in fig. 1, the connection wires connected to the source driver chip 142 and the connection wires connected to the source driver chip 143 are crossed, so that the connection wires connected to the source driver chip 142 may be disposed in the first metal layer, the connection wires connected to the source driver chip 143 may be disposed in the second metal layer, and the design modes of the connection wires connected to the source driver chip 141 and the connection wires connected to the source driver chip 144 are the same as the above design modes, which is not described in detail herein, so that the connection wires connecting the two source driver chips may be crossed and insulated without complex via-hole wire-changing arrangement, the complexity of the wiring design is reduced.
Alternatively, as shown in fig. 2 (only a case that four source driver chips are included and each source driver chip is electrically connected to four corresponding data lines is illustrated), fig. 2 is a top view of another array substrate according to an embodiment of the present invention, and the data lines 12 corresponding to the connecting wires 13 electrically connected to the plurality of pins of different source driver chips are alternately arranged in each display sub-region.
Specifically, as shown in fig. 2, the non-display region 2 of the substrate 11 includes four source driver chips, namely a source driver chip 141, a source driver chip 142, a source driver chip 143, and a source driver chip 144, each source driver chip corresponds to four data lines 12, and the substrate 11 includes two display sub-regions: taking the display sub-region a as an example, the display sub-region a includes two data lines 12 corresponding to the source driver chips 141, two data lines 12 corresponding to the source driver chips 142, two data lines 12 corresponding to the source driver chips 143, and two data lines 12 corresponding to the source driver chips 144, when the data lines 12 connected to the four source driver chips are alternately arranged in the display sub-region a in sequence, the data lines 12 connected to the source driver chips 141, the source driver chips 142, the source driver chips 143, and the source driver chips 144 may be uniformly distributed in the display sub-region a, and further when the display panel displays the same gray scale picture, the gray scale pictures corresponding to the data lines 12 connected to the source driver chips 141, the source driver chips 142, the source driver chips 143, and the source driver chips 144 may be uniformly distributed in the display sub-region a, the phenomenon that different areas display different gray scale pictures due to process errors between different source electrode driving chips in the display sub-area A is improved, and the display effect of the display panel is improved.
As shown in fig. 2, there are crossing connection wires in the connection wires connected to the source driver chips 142 and the connection wires connected to the source driver chips 143, so that the connection wires connected to the source driver chips 142 may be disposed on a first metal layer, the connection wires connected to the source driver chips 143 may be disposed on a second metal layer, and the connection wires connected to the source driver chips 141 and the connection wires connected to the source driver chips 144 are designed in the same manner as the above-mentioned design, which is not described in detail herein.
Alternatively, as shown in fig. 1 and 2, the plurality of source driving chips include a first source driving chip and a second source driving chip, and the connection wire 13 electrically connected to the first source driving chip and the connection wire 13 electrically connected to the second source driving chip are located at different layers.
Specifically, when each display sub-region includes data lines 12 corresponding to connection lines 13 electrically connected to a plurality of source driver chips, orthographic projections of the connection lines 13 electrically connected to different source driver chips on the substrate 11 may overlap, and in order to achieve mutual insulation between different connection lines 13, it is necessary to dispose the connection line 13 electrically connected to a first source chip and the connection line 13 electrically connected to a second source chip in different layers, as shown in fig. 1 and 2, taking the source driver chip 141 as a first source driver chip and the source driver chip 144 as a second source driver chip as an example, in each display sub-region, there is overlap between the orthographic projections of the connection line 13 electrically connected to the source driver chip 141 and the connection line 13 electrically connected to the source driver chip 144 on the substrate 11, and thus it is necessary to dispose the connection line 13 electrically connected to the source driver chip 141 and the connection line 13 electrically connected to the source driver chip 144 on the substrate 11, and dispose the connection line 13 electrically connected to the source driver chip 141 and the connection line 13 electrically The connection wire 13 electrically connected to the source driving chip 141 and the connection wire 13 electrically connected to the source driving chip 144 are insulated from each other in different layers. The specific arrangement is described in detail above, and is not illustrated here.
Optionally, the connection wires electrically connected with the first source driving chip are located at the same layer as the plurality of data lines.
Specifically, when the connecting wire electrically connected with the first source driving chip and the plurality of data lines are located on the same layer, the connecting wire electrically connected with the first source driving chip and the data lines connected with the connecting wire can be directly and electrically connected, and the data lines and the connecting wire can be prepared on the same layer when being manufactured, so that the manufacturing process flow of the array substrate is reduced.
Optionally, the connection wires electrically connected to the second source driver chip are electrically connected to the corresponding data lines through different first via holes, respectively.
Specifically, when the connecting wires electrically connected to the first source driver chip and the plurality of data lines are located in the same layer, in order to achieve insulation between the connecting wires electrically connected to different source driver chips, the connecting wires electrically connected to the second source driver chip and the plurality of data lines need to be disposed in different layers, and the connecting wires electrically connected to the second source driver chip are electrically connected to the corresponding data lines through the first via holes.
Optionally, the connecting wires electrically connected to the second source driver chips are electrically connected to the corresponding pins of the second source driver chips through different second via holes, respectively.
Specifically, the source driver chip includes a pad, the connection wire is electrically connected to the pin of the corresponding source driver chip through the pad, the pad may be located on the same layer as the connection wire, or may be located on different layers, and when the pad and the connection wire are located on different layers, the pad and the connection wire are electrically connected through the via hole, so that when the pad of the second source driver chip and the corresponding connection wire are located on different layers, the connection wire electrically connected to the second source driver chip is electrically connected to the pin of the corresponding second source driver chip through different second via holes, respectively.
Optionally, the connecting wires electrically connected to the first source driver chips are electrically connected to the corresponding pins of the first source driver chips through different third via holes, respectively.
Specifically, the source driver chip includes a pad, the connection wire is electrically connected to the pin of the corresponding source driver chip through the pad, the pad may be located on the same layer as the connection wire, or may be located on different layers, and when the pad and the connection wire are located on different layers, the pad and the connection wire are electrically connected through the via hole, so that when the pad of the first source driver chip and the corresponding connection wire are located on different layers, the connection wire electrically connected to the first source driver chip is electrically connected to the pin of the corresponding first source driver chip through different third via holes, respectively.
Alternatively, as shown in fig. 3 (only a case that four source driver chips are included and each source driver chip is electrically connected to corresponding four data lines is illustrated), fig. 3 is a top view of another array substrate according to an embodiment of the present invention, where a plurality of source driver chips are located on one side of the substrate 11 extending along the second direction X.
Specifically, as shown in fig. 3, the non-display region 2 of the substrate 11 includes four source driver chips, namely a source driver chip 141, a source driver chip 142, a source driver chip 143, and a source driver chip 144, wherein the source driver chip 141, the source driver chip 142, the source driver chip 143, and the source driver chip 144 are all located on the upper side of the substrate 11 and are arranged along a direction perpendicular to the data line 12.
As shown in fig. 3, since the connection wires connected to the source driver chips 141, 142, 143, and 144 may cross each other, the connection wires connected to the source driver chips may be disposed in different layers, for example, the connection wires connected to the source driver chips 141 may be disposed in a first metal layer, the connection wires connected to the source driver chips 142 may be disposed in a second metal layer, the connection wires connected to the source driver chips 143 may be disposed in a third metal layer, and the connection wires connected to the source driver chips 144 may be disposed in a fourth metal layer.
Alternatively, as shown in fig. 1 and 2, a plurality of source driving chips are located on both sides of the substrate base 11 extending in the second direction X.
Specifically, as shown in fig. 1 and fig. 2, the non-display region 2 of the substrate 11 includes four source driver chips, namely, a source driver chip 141, a source driver chip 142, a source driver chip 143, and a source driver chip 144, wherein the source driver chip 141 and the source driver chip 144 are located at a lower side of the substrate 11, the source driver chip 142 and the source driver chip 143 are located at an upper side of the substrate 11, the source driver chip 141 and the source driver chip 144 are arranged along a direction perpendicular to the data line 12, and the source driver chip 142 and the source driver chip 143 are arranged along a direction perpendicular to the data line 12, the layout manner may simplify the routing on the substrate 11, and reduce the difficulty of routing design, it should be noted that the number of the source driver chips located at two sides extending in the second direction X may be the same or different, the specific situation is set according to the routing situation on the substrate base plate 11.
Alternatively, as shown in fig. 4 (only a case where four source driver chips are included and each source driver chip is electrically connected to corresponding four data lines is illustrated), fig. 4 is a top view of another array substrate provided in an embodiment of the present invention, as shown in fig. 5 (only a case where three source driver chips are included and each source driver chip is electrically connected to corresponding four data lines is illustrated), and fig. 5 is a top view of another array substrate provided in an embodiment of the present invention, wherein the source driver chips on the first side and the source driver chips on the second side are sequentially arranged in a staggered manner along the first direction Y.
Specifically, as shown in fig. 4, four source driving chips, namely, a source driving chip 141, a source driving chip 142, a source driving chip 143, and a source driving chip 144, are included in the non-display region 2 of the substrate base plate 11, wherein the source driving chip 141 and the source driving chip 144 are located at the lower side of the substrate base plate 11, the source driving chip 142 and the source driving chip 143 are located at the upper side of the substrate base plate 11, and the source driving chip 141 and the source driving chip 144 are arranged in a direction perpendicular to the data line 12, the source driving chip 142 and the source driving chip 143 are arranged in a direction perpendicular to the data line 12, and orthographic projections of the source driving chip 141, the source driving chip 142, the source driving chip 143, and the source driving chip 144 in the first direction Y do not overlap; as shown in fig. 5, three source driving chips, namely, a source driving chip 141, a source driving chip 142 and a source driving chip 143, are included in the non-display region 2 of the substrate base plate 11, wherein the source driving chip 141 and the source driving chip 143 are located at a lower side of the substrate base plate 11, the source driving chip 142 is located at an upper side of the substrate base plate 11, and the source driving chip 141 and the source driving chip 143 are arranged in a direction perpendicular to the data line 12, and forward projections of the source driving chip 141, the source driving chip 142 and the source driving chip 143 in the first direction Y do not overlap.
The design manner of the layer where the connection wires connected to the source driver chips are located in fig. 4 may be the same as that in fig. 1 and 2, and is not described in detail here. The source driving chip 141 and the source driving chip 143 in fig. 5 may be designed in the same manner as the source driving chip 141 and the source driving chip 143 in fig. 1 and 2, and are not described in detail herein.
Alternatively, as shown in fig. 1, fig. 2 and fig. 6 (only a situation that three source driver chips are included and each source driver chip is electrically connected to corresponding four data lines is illustrated), fig. 6 is a top view of another array substrate according to an embodiment of the present invention, wherein the source driver chips on the first side and the source driver chips on the second side are correspondingly arranged along the first direction Y.
Specifically, as shown in fig. 1 and fig. 2, four source driver chips, namely, a source driver chip 141, a source driver chip 142, a source driver chip 143, and a source driver chip 144, are included in the non-display region 2 of the substrate 11, wherein the source driver chip 141 and the source driver chip 144 are located at the lower side of the substrate 11, the source driver chip 142 and the source driver chip 143 are located at the upper side of the substrate 11, and the source driver chip 141 and the source driver chip 144 are arranged in a direction perpendicular to the data line 12, and the source driver chip 142 and the source driver chip 143 are arranged in a direction perpendicular to the data line 12, wherein the orthographic projections of the source driver chip 141 and the source driver chip 142 in the first direction Y completely overlap, and the orthographic projections of the source driver chip 143 and the source driver chip 144 in the first direction Y completely overlap; as shown in fig. 6, three source driving chips, namely, a source driving chip 141, a source driving chip 142 and a source driving chip 143, are included in the non-display region 2 of the substrate 11, wherein the source driving chip 141 and the source driving chip 143 are located at a lower side of the substrate 11, the source driving chip 142 is located at an upper side of the substrate 11, the source driving chip 141 and the source driving chip 143 are arranged in a direction perpendicular to the data line 12, and orthographic projections of the source driving chip 141 and the source driving chip 142 in the first direction Y completely overlap.
The source driving chip 141 and the source driving chip 143 in fig. 6 may be designed in the same manner as the source driving chip 141 and the source driving chip 143 in fig. 1 and 2, and are not described in detail herein.
An embodiment of the present invention provides a display panel, including the array substrate, where the specific structure and principle of the array substrate are the same as those of the above embodiments, and are not described herein again.
As shown in fig. 7, fig. 7 is a schematic view of a display device according to an embodiment of the present invention, wherein the display device includes the display panel 100, and the specific structure and principle of the display panel 100 are the same as those of the embodiment, which is not described herein again.
The display device according to the embodiment of the present invention may include, but is not limited to, any electronic device having a liquid crystal display function, such as a Personal Computer (PC), a Personal Digital Assistant (PDA), a wireless handheld device, a Tablet Computer (Tablet Computer), a mobile phone, an MP4 player, or a television.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. An array substrate, comprising:
a substrate base including a display area and a non-display area surrounding the display area;
the data lines are positioned on the substrate base plate and in the display area, extend along a first direction and are arranged along a second direction, and the first direction and the second direction are perpendicular to each other;
a plurality of connection wires located on the substrate and within the non-display area, the plurality of connection wires being electrically connected to different data lines, respectively;
the source driving chips are positioned on the substrate and in the non-display area, the source driving chips are arranged along the second direction, each source driving chip comprises a plurality of pins, and each pin is electrically connected with different connecting wires;
the display area comprises a plurality of display sub-areas, the display sub-areas extend along a first direction and are arranged along a second direction, and each display sub-area comprises a data line corresponding to a connecting wire electrically connected with the source electrode driving chips;
the data lines corresponding to the connecting wires electrically connected with the plurality of pins of the different source electrode driving chips are sequentially and alternately arranged in each display sub-area;
the source driving chips comprise a first source driving chip and a second source driving chip, and connecting wires electrically connected with the first source driving chip and connecting wires electrically connected with the second source driving chip are located on different layers;
the connecting wires electrically connected with the first source electrode driving chip and the plurality of data wires are positioned on the same layer;
connecting wires electrically connected with the second source electrode driving chip are electrically connected with corresponding data wires through different first via holes respectively;
the source driving chips are located on two sides of the substrate base plate extending along the second direction.
2. The array substrate of claim 1, wherein the connection wires electrically connected to the second source driver chips are electrically connected to the pins of the corresponding second source driver chips through different second vias, respectively.
3. The array substrate of claim 1, wherein the connection wires electrically connected to the first source driver chips are electrically connected to the pins of the corresponding first source driver chips through different third via holes, respectively.
4. The array substrate of claim 1, wherein the source driver chips on the first side and the source driver chips on the second side are sequentially arranged in a staggered manner along the first direction.
5. The array substrate of claim 1, wherein the source driver chips on the first side and the source driver chips on the second side are correspondingly arranged along the first direction.
6. A display panel comprising the array substrate according to any one of claims 1 to 5.
7. A display device comprising the display panel according to claim 6.
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| CN201710630290.1A CN107290903B (en) | 2017-07-28 | 2017-07-28 | Array substrate, display panel and display device |
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| KR20200101575A (en) * | 2019-02-19 | 2020-08-28 | 삼성디스플레이 주식회사 | Display device |
| CN110737140B (en) * | 2019-10-31 | 2022-12-13 | 厦门天马微电子有限公司 | Display panel, control method thereof and display device |
| CN114783363A (en) * | 2022-04-25 | 2022-07-22 | 深圳市华星光电半导体显示技术有限公司 | Display device and signal control method |
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