CN204496325U - A kind of band-gap reference circuit - Google Patents

Abstract

The utility model relates to Circuits System technical field, especially a kind of band-gap reference circuit.It comprises the second field effect transistor, the 4th field effect transistor, the 5th field effect transistor, the 6th field effect transistor, the 8th field effect transistor, the tenth field effect transistor, the first triode, the second triode, the 3rd triode, the 4th triode, the 5th triode and operational amplifier; Operational amplifier in-phase end is connected with the emitter of the second triode by the first resistance, the collector of the second triode simultaneously with the collector of the collector of the first triode, the collector of the 3rd triode, the collector of the 4th triode and the 5th triode, the drain electrode of the 5th field effect transistor simultaneously of the base stage of the 4th triode, the grid of the 6th field effect transistor, the grid of the 8th field effect transistor, the grid of the tenth field effect transistor, the grid of the 4th field effect transistor are connected with the grid of the second field effect transistor.The utility model circuit structure is simple, has very strong practicality.

Description

A kind of band-gap reference circuit

Technical field

The utility model relates to Circuits System technical field, especially a kind of band-gap reference circuit.

Background technology

As everyone knows, band-gap reference circuit is normally used to provide reference voltage.At present, be easy to cause band-gap reference circuit instability for the change of supply voltage in circuit, the electric current simultaneously exported is often not high.Therefore, be necessary that designing a kind of band-gap reference circuit solves the problems referred to above.

Utility model content

For above-mentioned the deficiencies in the prior art, the purpose of this utility model is that providing a kind of significantly can reduce the impact of supply voltage and can export the band-gap reference circuit of high-precision current.

To achieve these goals, the utility model adopts following technical scheme:

A kind of band-gap reference circuit, it comprises the first field effect transistor, the second field effect transistor, the 3rd field effect transistor, the 4th field effect transistor, the 5th field effect transistor, the 6th field effect transistor, the 7th field effect transistor, the 8th field effect transistor, the 9th field effect transistor, the tenth field effect transistor, the 11 field effect transistor, the 12 field effect transistor, the 13 field effect transistor, the first triode, the second triode, the 3rd triode, the 4th triode, the 5th triode and operational amplifier;

Described operational amplifier in-phase end is connected with the drain electrode of the first field effect transistor and passes through the first resistance and is connected with the emitter of the second triode, the base stage of described second triode is connected with the emitter of the first triode, the collector of described second triode simultaneously with the collector of the first triode, the collector of the 3rd triode, the collector of the 4th triode, the collector of the 5th triode is connected with the 14 field effect transistor source electrode, the grid of described 14 field effect transistor is connected with the drain electrode of self, the drain electrode of described 14 field effect transistor is connected with the source electrode of the 13 field effect transistor, the drain electrode of described 13 field effect transistor is connected with the grid of self and goes back and is connected with the drain electrode of the 11 field effect transistor and the grid of the 12 field effect transistor simultaneously, the source electrode of described 11 field effect transistor simultaneously with the source electrode of the second field effect transistor, the source electrode of the 4th field effect transistor, the source electrode of the 6th field effect transistor, the source electrode of the 8th field effect transistor, the source electrode of the tenth field effect transistor is connected with the source electrode of the 12 field effect transistor, the grid of described 11 field effect transistor simultaneously with the grid of the first field effect transistor, the grid of the 3rd field effect transistor, the grid of the 5th field effect transistor, the grid of the 7th field effect transistor, the grid of the 9th field effect transistor is connected with the output terminal of operational amplifier, the end of oppisite phase of described operational amplifier simultaneously with the drain electrode of the 12 field effect transistor, the drain electrode of the 7th field effect transistor is connected with the emitter of the 4th triode, the collector of described 4th triode is connected with the base stage of the 5th triode, the base stage of described 4th triode simultaneously with the emitter of the 3rd triode, the drain electrode of the 5th field effect transistor, the grid of the 6th field effect transistor, the grid of the 8th field effect transistor, the grid of the tenth field effect transistor, the grid of the 4th field effect transistor is connected with the grid of the second field effect transistor, the drain electrode of described tenth field effect transistor is connected with the source electrode of the 9th field effect transistor, the drain electrode output current of described 9th field effect transistor is also connected with the emitter of the 5th triode by the second resistance.

Owing to have employed such scheme, the voltage difference that the utility model is produced by source electrode and the grid of field effect transistor acts on the first resistance and can obtain high-precision current, simultaneously, the base-emitter being added in the 5th triode by voltage difference can obtain reference voltage, and, used by multiple triode series connection, effectively reduce the impact of supply voltage on circuit; In addition, the 11 field effect transistor, the 12 field effect transistor, the 13 field effect transistor and the 14 field effect transistor form start-up circuit, utilize start-up circuit to get off quickly after the power-up zero current condition and steady operation to guarantee circuit.

Accompanying drawing explanation

Fig. 1 is the electrical block diagram of the utility model embodiment.

Embodiment

Below in conjunction with accompanying drawing, embodiment of the present utility model is described in detail, but the multitude of different ways that the utility model can be defined by the claims and cover is implemented.

As shown in Figure 1, a kind of band-gap reference circuit of the present embodiment, it comprises the first field effect transistor M1, the second field effect transistor M2, the 3rd field effect transistor M3, the 4th field effect transistor M4, the 5th field effect transistor M5, the 6th field effect transistor M6, the 7th field effect transistor M7, the 8th field effect transistor M8, the 9th field effect transistor M9, the tenth field effect transistor M10, the 11 field effect transistor M11, the 12 field effect transistor M12, the 13 field effect transistor M13, the first triode Q1, the second triode Q2, the 3rd triode Q3, the 4th triode Q4, the 5th triode Q5 and operational amplifier U1, operational amplifier U1 in-phase end is connected with the drain electrode of the first field effect transistor M1 and passes through the first resistance R1 and is connected with the emitter of the second triode Q2, the base stage of the second triode Q2 is connected with the emitter of the first triode Q1, the collector of the second triode Q2 simultaneously with the collector of the first triode Q1, the collector of the 3rd triode Q3, the collector of the 4th triode Q4, the collector of the 5th triode Q5 is connected with the 14 field effect transistor M14 source electrode, the grid of the 14 field effect transistor M14 is connected with the drain electrode of self, the drain electrode of the 14 field effect transistor M14 is connected with the source electrode of the 13 field effect transistor M13, the drain electrode of the 13 field effect transistor M13 is connected with the grid of self and goes back and is connected with the drain electrode of the 11 field effect transistor M11 and the grid of the 12 field effect transistor M12 simultaneously, the source electrode of the 11 field effect transistor M11 simultaneously with the source electrode of the second field effect transistor M2, the source electrode of the 4th field effect transistor M4, the source electrode of the 6th field effect transistor M6, the source electrode of the 8th field effect transistor M8, the source electrode of the tenth field effect transistor M10 is connected with the source electrode of the 12 field effect transistor M12, the grid of the 11 field effect transistor M11 simultaneously with the grid of the first field effect transistor M1, the grid of the 3rd field effect transistor M3, the grid of the 5th field effect transistor M5, the grid of the 7th field effect transistor M7, the grid of the 9th field effect transistor M9 is connected with the output terminal of operational amplifier U1, the end of oppisite phase of operational amplifier U1 simultaneously with the drain electrode of the 12 field effect transistor M12, the drain electrode of the 7th field effect transistor M7 is connected with the emitter of the 4th triode Q4, the collector of the 4th triode Q4 is connected with the base stage of the 5th triode Q5, the base stage of the 4th triode Q4 simultaneously with the emitter of the 3rd triode Q3, the drain electrode of the 5th field effect transistor M5, the grid of the 6th field effect transistor M6, the grid of the 8th field effect transistor M8, the grid of the tenth field effect transistor M10, the grid of the 4th field effect transistor M4 is connected with the grid of the second field effect transistor M4, the drain electrode of the tenth field effect transistor M10 is connected with the source electrode of the 9th field effect transistor M9, the drain electrode output current of the 9th field effect transistor M9 is also connected with the emitter of the 5th triode Q5 by the second resistance R2.The voltage difference that the present embodiment is produced by the source electrode of field effect transistor and grid acts on the first resistance R1 and can obtain high-precision current, and, the base-emitter being added in the 5th triode Q5 by voltage difference can obtain reference voltage; In addition, utilize multiple triode to connect and use, effectively reduce the impact of supply voltage on circuit.The 11 field effect transistor M11 of the present embodiment, the 12 field effect transistor M12, the 13 field effect transistor M13 and the 14 field effect transistor M14 form start-up circuit, utilize start-up circuit to get off quickly after the power-up zero current condition and steady operation to guarantee circuit.

The foregoing is only preferred embodiment of the present utility model; not thereby the scope of the claims of the present utility model is limited; every utilize the utility model instructions and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present utility model.

Claims (1)

1. a band-gap reference circuit, is characterized in that: it comprises the first field effect transistor, the second field effect transistor, the 3rd field effect transistor, the 4th field effect transistor, the 5th field effect transistor, the 6th field effect transistor, the 7th field effect transistor, the 8th field effect transistor, the 9th field effect transistor, the tenth field effect transistor, the 11 field effect transistor, the 12 field effect transistor, the 13 field effect transistor, the first triode, the second triode, the 3rd triode, the 4th triode, the 5th triode and operational amplifier;

Described operational amplifier in-phase end is connected with the drain electrode of the first field effect transistor and passes through the first resistance and is connected with the emitter of the second triode, the base stage of described second triode is connected with the emitter of the first triode, the collector of described second triode simultaneously with the collector of the first triode, the collector of the 3rd triode, the collector of the 4th triode, the collector of the 5th triode is connected with the 14 field effect transistor source electrode, the grid of described 14 field effect transistor is connected with the drain electrode of self, the drain electrode of described 14 field effect transistor is connected with the source electrode of the 13 field effect transistor, the drain electrode of described 13 field effect transistor is connected with the grid of self and goes back and is connected with the drain electrode of the 11 field effect transistor and the grid of the 12 field effect transistor simultaneously, the source electrode of described 11 field effect transistor simultaneously with the source electrode of the second field effect transistor, the source electrode of the 4th field effect transistor, the source electrode of the 6th field effect transistor, the source electrode of the 8th field effect transistor, the source electrode of the tenth field effect transistor is connected with the source electrode of the 12 field effect transistor, the grid of described 11 field effect transistor simultaneously with the grid of the first field effect transistor, the grid of the 3rd field effect transistor, the grid of the 5th field effect transistor, the grid of the 7th field effect transistor, the grid of the 9th field effect transistor is connected with the output terminal of operational amplifier, the end of oppisite phase of described operational amplifier simultaneously with the drain electrode of the 12 field effect transistor, the drain electrode of the 7th field effect transistor is connected with the emitter of the 4th triode, the collector of described 4th triode is connected with the base stage of the 5th triode, the base stage of described 4th triode simultaneously with the emitter of the 3rd triode, the drain electrode of the 5th field effect transistor, the grid of the 6th field effect transistor, the grid of the 8th field effect transistor, the grid of the tenth field effect transistor, the grid of the 4th field effect transistor is connected with the grid of the second field effect transistor, the drain electrode of described tenth field effect transistor is connected with the source electrode of the 9th field effect transistor, the drain electrode output current of described 9th field effect transistor is also connected with the emitter of the 5th triode by the second resistance.