CN204442574U - A kind of coal mine downhole safety produces network video monitor and control system - Google Patents
A kind of coal mine downhole safety produces network video monitor and control system Download PDFInfo
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- CN204442574U CN204442574U CN201520190840.9U CN201520190840U CN204442574U CN 204442574 U CN204442574 U CN 204442574U CN 201520190840 U CN201520190840 U CN 201520190840U CN 204442574 U CN204442574 U CN 204442574U
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Abstract
The utility model discloses a kind of coal mine downhole safety and produce network video monitor and control system, comprise multiple stage Network Video Surveillance video camera, multiple stage Network Video Surveillance video camera is all connected to the AVB network switch by unshielded twisted pair and is connected with ground monitoring server by the AVB network switch, multiple stage Network Video Surveillance video camera includes video camera lifting plate, camera housing, camera lens and video acquisition transmission circuit plate, and camera housing and video camera lifting plate are rotationally connected; Video acquisition transmission circuit plate is integrated with video acquisition transmission circuit, and video acquisition transmission circuit comprises FPGA module, RTC real time clock circuit, FLASH flash memory circuit, DRAM memory circuitry, configuring chip, AVB ethernet module, ISP image-signal processor and imageing sensor.The utility model multiple Network Video Surveillance camera video flow transmission is synchronous, and the quality of Network Video Surveillance picture is high, practical.
Description
Technical field
The utility model relates to mine safety technical field, especially relates to a kind of coal mine downhole safety and produces network video monitor and control system.
Background technology
In the U.S., colliery realizes high mechanization, and underground work personnel are little, and job specification, tunnel is unobstructed, once have an accident, be easy to withdraw, injures and deaths are little.And in China, mining mechanization degree is only 45%, miner troop be greatly educational level lower, train limited rural migrant worker, even there is the serious violation phenomenon such as down-hole smoking.Numerous miners like this, in the operating environment of highly dangerous, very easily have an accident, create greater casualties.The reason that important coal mining accident occurs is mainly reflected in: the information communication of ground and personnel in the pit not in time, ground staff is difficult to distribution and the handling situations of dynamically grasping personnel in the pit in time, once coal mining accident occurs, the efficiency of rescue and relief work, safety first-aid is low, searches and rescues weak effect.At present, coal mine operation is because away from ground, with a varied topography, bad environments, inconvenience is linked up with ground staff, if utilize Active Eyes, ground monitoring personnel then can directly monitor down-hole situation in real time, can not only monitor and record the safety in production situation at underground work scene intuitively, and energy Timeliness coverage accident potential, prevent trouble before it happens, also relevant first-hand image document can be provided for ex-post analysis accident, meanwhile, the relevant supervision department of higher level also can be checked by network remote and carry out situation, proposes amelioration method.But also there is following defect and deficiency in the video monitoring system being used in underground coal mine in prior art:
1, CCTV camera visual angle is little.The visual angle size of CCTV camera directly determines the size of amount of information.The gun shaped camera horizon angular field of view that current underground coal mine extensively adopts generally all is less than 70 °, and vertical angle of view scope is generally all less than 30 °.And the horizontal view angle of eye is at 160 °, vertical angle of view is about 80 °.Little being easy in single CCTV camera visual angle causes monitoring dead angle, and needs more CCTV camera to obtain overall view monitoring.
2, cannot accurate synchronization between multiple CCTV camera.Current underground coal mine video monitoring system will adopt business Ethernet transmitting video-frequency flow, meets IEEE802.3 standard.Business Ethernet appears at 1972 the earliest, take office automation as target design, and do not consider the accurate synchronization problem between multiple terminal, transmission delay has uncertainty.Multiple CCTV camera carries out the nonsynchronous problem of video-splicing life period, cannot realize real seamless spliced.
3, operating temperature range is narrow, and hot environment cannot normally work.Current CCTV camera grade is generally business level, and maximum operating temperature is less than 70 degree, and under some particular surroundingss of underground coal mine, equipment cannot normally use.As accident rescue is on-the-spot, before ambient temperature does not drop to normal range (NR), more early obtain live video data better.
4, wiring cost is high.Current underground coal mine video monitoring system wiring adopts optical fiber or fire-retardant netting twine, and cost is higher, is unfavorable for large-scale use.
5, CCTV camera dynamic range is inadequate.Current CCTV camera is dynamically generally all less than 90db, if CCTV camera installation site is not chosen, is easy to the phenomenon occurring that dynamic range is inadequate, there is the problem that partial exposure is not enough and local is over-exposed simultaneously, affects the quality of monitored picture.
Utility model content
Technical problem to be solved in the utility model is for above-mentioned deficiency of the prior art, a kind of coal mine downhole safety is provided to produce network video monitor and control system, its realization is convenient and cost is low, the accurate synchronization of multiple Network Video Surveillance camera video flow transmission can be ensured, the dynamic range of Network Video Surveillance video camera is large, ensure that the quality of Network Video Surveillance picture, practical, application value is high.
For solving the problems of the technologies described above, the technical solution adopted in the utility model is: a kind of coal mine downhole safety produces network video monitor and control system, it is characterized in that: comprise the multiple stage Network Video Surveillance video camera being laid in underground coal mine, multiple stage Network Video Surveillance video camera is all connected to the AVB network switch by unshielded twisted pair and is connected with ground monitoring server by the AVB network switch, multiple stage Network Video Surveillance video camera includes video camera lifting plate, camera housing, embed the camera lens be arranged on camera housing and the video acquisition transmission circuit plate being arranged on camera housing inside, the top of described camera housing is provided with housing contiguous block, the geometric center position of described housing contiguous block is provided with housing contiguous block centre bore, the bottom of described video camera lifting plate is provided with the lifting plate contiguous block that two pieces lay respectively at housing contiguous block both sides, the geometric center position of two pieces of described lifting plate contiguous blocks is provided with lifting plate contiguous block centre bore, described camera housing and video camera lifting plate are by being connected through the axis of rotation of described housing contiguous block centre bore with two described lifting plate contiguous block centre bores, described video acquisition transmission circuit plate is integrated with video acquisition transmission circuit, described video acquisition transmission circuit comprises FPGA module and the power module for each electricity consumption module for power supply in described video acquisition transmission circuit, and RTC real time clock circuit, FLASH flash memory circuit, DRAM memory circuitry, configuring chip and the AVB ethernet module to connect with FPGA module, the input of described FPGA module is connected to ISP image-signal processor, and the input of described ISP image-signal processor is connected to imageing sensor, described ISP image-signal processor is the ISP image-signal processor AP0101AT that Aptina company produces, described imageing sensor is the imageing sensor AR0132AT that Aptina company produces, described AVB ethernet module being connected with the twisted-pair feeder interface for connecting unshielded twisted pair, being exposed on the outer surface of camera housing outside described twisted-pair feeder interface.
Above-mentioned a kind of coal mine downhole safety produces network video monitor and control system, it is characterized in that: described camera lens is fish eye lens.
Above-mentioned a kind of coal mine downhole safety produces network video monitor and control system, it is characterized in that: described FPGA module is fpga chip EP3C5E144C8N.
Above-mentioned a kind of coal mine downhole safety produces network video monitor and control system, it is characterized in that: DO0 ~ DO6 pin of described ISP image-signal processor AP0101AT is corresponding in turn to and connects with 73rd ~ 80 pins of described fpga chip EP3C5E144C8N, the DO7 pin of described ISP image-signal processor AP0101AT connects with the 83rd pin of described fpga chip EP3C5E144C8N, the SCLK pin of described ISP image-signal processor AP0101AT connects with the 84th pin of described fpga chip EP3C5E144C8N, and connected with+3.3V the voltage output end of power module by resistance R3, the SDA pin of described ISP image-signal processor AP0101AT connects with the 85th pin of described fpga chip EP3C5E144C8N, and is connected with+3.3V the voltage output end of power module by resistance R2, the PCLK pin of described ISP image-signal processor AP0101AT connects with the 86th pin of described fpga chip EP3C5E144C8N, the ECLK pin of described ISP image-signal processor AP0101AT connects with the 87th pin of described fpga chip EP3C5E144C8N, the VS pin of described ISP image-signal processor AP0101AT connects with the 69th pin of described fpga chip EP3C5E144C8N, and the HS pin of described ISP image-signal processor AP0101AT connects with the 70th pin of described fpga chip EP3C5E144C8N, the NRST pin of described ISP image-signal processor AP0101AT is connected with+3.3V the voltage output end of power module by resistance R1, the MSCLK pin of described ISP image-signal processor AP0101AT is connected with+1.8V the voltage output end of power module by resistance R6, the MSDA pin of described ISP image-signal processor AP0101AT is connected with+1.8V the voltage output end of power module by resistance R5, the STANDBY pin of described ISP image-signal processor AP0101AT is by resistance R7 ground connection, the FS pin of described ISP image-signal processor AP0101AT is by resistance R8 ground connection.
Above-mentioned a kind of coal mine downhole safety produces network video monitor and control system, it is characterized in that: DO0 ~ DO11 pin of described imageing sensor AR0132AT is corresponding in turn to and connects with DI0 ~ DI11 pin of described ISP image-signal processor AP0101AT, the EXTCLK pin of described imageing sensor AR0132AT connects with the ECO pin of described ISP image-signal processor AP0101AT, the RST pin of described imageing sensor AR0132AT connects with the RSTO pin of described ISP image-signal processor AP0101AT, and connected with+1.8V the voltage output end of power module by resistance R31, the SCLK pin of described imageing sensor AR0132AT connects with the MSCLK pin of described ISP image-signal processor AP0101AT, the SDA pin of described imageing sensor AR0132AT connects with the MSDA pin of described ISP image-signal processor AP0101AT, the PCLK pin of described imageing sensor AR0132AT connects with the PCLKI pin of described ISP image-signal processor AP0101AT, the FV pin of described imageing sensor AR0132AT connects with the FVI pin of described ISP image-signal processor AP0101AT, the LV pin of described imageing sensor AR0132AT connects with the LVI pin of described ISP image-signal processor AP0101AT, the TRIGGER pin of described imageing sensor AR0132AT connects with the TO pin of described ISP image-signal processor AP0101AT, the SADDR pin of described imageing sensor AR0132AT is connected with+1.8V the voltage output end of power module by resistance R32, the OE pin of described imageing sensor AR0132AT is by resistance R33 ground connection.
Above-mentioned a kind of coal mine downhole safety produces network video monitor and control system, it is characterized in that: described RTC real time clock circuit comprises real-time timepiece chip ISL1208 and crystal oscillator Y1, 1st pin of described real-time timepiece chip ISL1208 connects with one end of crystal oscillator Y1, 2nd pin of described real-time timepiece chip ISL1208 connects with the other end of crystal oscillator Y1, 3rd pin of described real-time timepiece chip ISL1208 connects with+3.3V the voltage output end of power module, the 4th pin ground connection of described real-time timepiece chip ISL1208, 5th pin of described real-time timepiece chip ISL1208 connects with the 110th pin of described fpga chip EP3C5E144C8N, and connected with+3.3V the voltage output end of power module by resistance R21, 6th pin of described real-time timepiece chip ISL1208 connects with the 111st pin of described fpga chip EP3C5E144C8N, and connected with+3.3V the voltage output end of power module by resistance R20,7th pin of described real-time timepiece chip ISL1208 connects with the 24th pin of described fpga chip EP3C5E144C8N, and connected with+3.3V the voltage output end of power module by resistance R19, the 8th pin of described real-time timepiece chip ISL1208 connects with+3.3V the voltage output end of power module (19).
Above-mentioned a kind of coal mine downhole safety produces network video monitor and control system, it is characterized in that: described FLASH flash memory circuit comprises chip H27U1G8F2B, 7th pin of described chip H27U1G8F2B connects with the 127th pin of described fpga chip EP3C5E144C8N, and is connected with+3.3V the voltage output end of power module by resistance R12, 8th pin of described chip H27U1G8F2B connects with the 128th pin of described fpga chip EP3C5E144C8N, 9th pin of described chip H27U1G8F2B connects with the 129th pin of described fpga chip EP3C5E144C8N, 12nd pin and the 37th pin of described chip H27U1G8F2B all connect with+3.3V the voltage output end of power module, 13rd pin of described chip H27U1G8F2B and the equal ground connection of the 36th pin, 16th ~ 19 pins of described chip H27U1G8F2B are corresponding in turn to and connect with 132nd ~ 136 pins of described fpga chip EP3C5E144C8N, 29th ~ 32 pins of described chip H27U1G8F2B are corresponding in turn to and connect with 112nd ~ 115 pins of described fpga chip EP3C5E144C8N, 41st ~ 44 pins of described chip H27U1G8F2B are corresponding in turn to and connect with 119th ~ 124 pins of described fpga chip EP3C5E144C8N.
Above-mentioned a kind of coal mine downhole safety produces network video monitor and control system, it is characterized in that: described DRAM memory circuitry comprises chip K4S641632UC-70T, the 2nd of described chip K4S641632UC-70T, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51 and 53 pins are corresponding in turn to the with described fpga chip EP3C5E144C8N the 28th, 30, 31, 32, 33, 34, 38, 39, 54, 53, 52, 51, 50, 49, 46 and 44 pins connect, 19th pin of described chip K4S641632UC-70T connects with the 7th pin of described fpga chip EP3C5E144C8N, and connected with+3.3V the voltage output end of power module by resistance R16, 16th pin of described chip K4S641632UC-70T connects with the 42nd pin of described fpga chip EP3C5E144C8N, and is connected with+3.3V the voltage output end of power module by resistance R15, 17th pin of described chip K4S641632UC-70T connects with the 11st pin of described fpga chip EP3C5E144C8N, and is connected with+3.3V the voltage output end of power module by resistance R14, 18th pin of described chip K4S641632UC-70T connects with the 10th pin of described fpga chip EP3C5E144C8N, and is connected with+3.3V the voltage output end of power module by resistance R13, the 23rd of described chip K4S641632UC-70T, 24, 25, 26, 29, 30, 31, 32, 33, 34, 22 and 35 pins are corresponding in turn to the with described fpga chip EP3C5E144C8N the 1st, 144, 143, 68, 67, 66, 65, 64, 60, 59, 2 and 58 pins connect, 20th and 21 pins of described chip K4S641632UC-70T are corresponding in turn to and connect with the 4th and 3 pins of described fpga chip EP3C5E144C8N, 37th pin of described chip K4S641632UC-70T connects with the 55th pin of described fpga chip EP3C5E144C8N, the 43rd pin that 38th pin of described chip K4S641632UC-70T is corresponding in turn to described fpga chip EP3C5E144C8N connects, and by electric capacity C22 ground connection.
Above-mentioned a kind of coal mine downhole safety produces network video monitor and control system, it is characterized in that: described configuring chip is chip EPCS64,1st pin of described chip EPCS64 connects with the 8th pin of described fpga chip EP3C5E144C8N, 2nd pin of described chip EPCS64 is connected with the 13rd pin of described fpga chip EP3C5E144C8N by resistance R35,3rd, 7 and 8 pins of described chip EPCS64 all connect with+3.3V the voltage output end of power module, and by electric capacity C27 ground connection, the 4th pin ground connection of described chip EPCS64; 5th pin of described chip EPCS64 connects with the 6th pin of described fpga chip EP3C5E144C8N, and the 6th pin of described chip EPCS64 is connected with the 12nd pin of described fpga chip EP3C5E144C8N by resistance R36.
Above-mentioned a kind of coal mine downhole safety produces network video monitor and control system, it is characterized in that: described AVB ethernet module comprises AVB Ethernet chip BCM89810 and common mode inductance T1, described twisted-pair feeder interface is four pin interface P2,8th pin of described AVB Ethernet chip BCM89810 connects with the 98th pin of described fpga chip EP3C5E144C8N, 26th pin of described AVB Ethernet chip BCM89810 connects with the 72nd pin of described fpga chip EP3C5E144C8N, 32nd pin of described AVB Ethernet chip BCM89810 and the 31st pin are corresponding in turn to and connect with the 137th pin of described fpga chip EP3C5E144C8N and the 138th pin, 28th pin of described AVB Ethernet chip BCM89810 and the 27th pin are corresponding in turn to and connect with the 141st pin of described fpga chip EP3C5E144C8N and the 142nd pin, 33rd pin of described AVB Ethernet chip BCM89810 connects with the 104th pin of described fpga chip EP3C5E144C8N, 35th pin of described AVB Ethernet chip BCM89810 connects with the 101st pin of described fpga chip EP3C5E144C8N, 39th pin of described AVB Ethernet chip BCM89810 and the 38th pin are corresponding in turn to and connect with the 105th pin of described fpga chip EP3C5E144C8N and the 106th pin, 37th pin of described AVB Ethernet chip BCM89810 and the 36th pin are corresponding in turn to and connect with the 125th pin of described fpga chip EP3C5E144C8N and the 126th pin, 40th pin of described AVB Ethernet chip BCM89810 connects with the 71st pin of described fpga chip EP3C5E144C8N, 46th pin of described AVB Ethernet chip BCM89810 connects with the 103rd pin of described fpga chip EP3C5E144C8N, 47th pin of described AVB Ethernet chip BCM89810 connects with the 99th pin of described fpga chip EP3C5E144C8N, and connected with+3.3V the voltage output end of power module by resistance R41,48th pin of described AVB Ethernet chip BCM89810 connects with the 100th pin of described fpga chip EP3C5E144C8N, 14th pin of described AVB Ethernet chip BCM89810 be connected to the resistance R45 and resistance R46 that connect between the 15th pin, the link ground connection of described resistance R45 and resistance R46, 14th pin of described AVB Ethernet chip BCM89810 is connected with first input pin of common mode inductance T1 by electric capacity C48, 15th pin of described AVB Ethernet chip BCM89810 is connected with second input pin of common mode inductance T1 by electric capacity C47, first output pin of described common mode inductance T1 connects with the 2nd pin of four pin interface P2, second output pin of described common mode inductance T1 connects with the 3rd pin of four pin interface P2, 1st pin of described four pin interface P2 connects with+12V the voltage output end of power module, the 4th pin ground connection of described four pin interface P2.
The utility model compared with prior art has the following advantages:
1, the structure of the utility model Network Video Surveillance video camera is simple, easy for installation.
2, Network Video Surveillance video camera of the present utility model have employed fish eye lens, and fish-eye visual range is large, and horizontal view angle is greater than 120 °, and vertical angle of view is greater than 120 °; And, have employed the video camera be rotationally connected with camera housing to lift plate this Network Video Surveillance video camera is installed, be convenient to regulate monitoring visual angle, decrease monitoring dead angle, and make a Network Video Surveillance video camera can monitor more interval, without the need to the overall view monitoring using more Network Video Surveillance video camera just can realize underground coal mine, that has saved supervisory control system overall view monitoring realizes cost.
3, can accurate synchronization between multiple Network Video Surveillance video camera.Network Video Surveillance video camera of the present utility model have employed AVB Ethernet chip BCM89810 and peripheral circuit forms AVB ethernet module, timestamp can be increased for message transmission, ensure that the accurate synchronization of multiple video streaming, be convenient to carry out the splicing of Multi net voting video monitoring camera.
4, operating temperature range is wide.The imageing sensor AR0132AT that the utility model Network Video Surveillance video camera adopts and ISP image-signal processor AP0101AT, and FPGA module, RTC real time clock circuit, FLASH flash memory circuit, DRAM memory circuitry, configuring chip and AVB ethernet module are wide temperature level chip, the operating temperature range making whole Network Video Surveillance video camera is-40 DEG C ~+105 DEG C, can use under rescue acquisition environment.
5, wiring cost is low.The utility model adopts unshielded twisted pair wiring, greatly reduces field wiring cost, and makes traditional unshielded twisted pair can transmit high-definition network video stream.
6, Network Video Surveillance video camera dynamic range is large.The utility model Network Video Surveillance video camera have employed wide Dynamic IS P image-signal processor AP0101AT, and dynamic range is greater than 115db, meets the requirement of subsurface environment HD video, ensure that the quality of Network Video Surveillance picture.
7, of the present utility modelly to apply, significantly can improve the monitoring effect that coal mine downhole safety is produced, be convenient to ground monitoring personnel directly monitor in real time down-hole situation, can monitor and record the safety in production situation at underground work scene intuitively, and energy Timeliness coverage accident potential, prevent trouble before it happens, also relevant first-hand image document can be provided for ex-post analysis accident, practical, result of use is good, and application value is high.
In sum, realization of the present utility model is convenient and cost is low, can ensure the accurate synchronization of multiple Network Video Surveillance camera video flow transmission, the dynamic range of Network Video Surveillance video camera is large, ensure that the quality of Network Video Surveillance picture, practical, application value is high.
Below by drawings and Examples, the technical solution of the utility model is described in further detail.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model.
Fig. 2 is the structural representation of the utility model Network Video Surveillance video camera.
Fig. 3 is the schematic block circuit diagram of the utility model video acquisition transmission circuit.
Fig. 4 A is the circuit theory diagrams of the utility model FPGA module part A.
Fig. 4 B is the circuit theory diagrams of the utility model FPGA module part B.
Fig. 4 C is the circuit theory diagrams of the utility model FPGA module C part.
Fig. 4 D is the circuit theory diagrams of the utility model FPGA module D part.
Fig. 4 E is the circuit theory diagrams of the utility model FPGA module E part.
Fig. 4 F is the circuit theory diagrams of the utility model FPGA module F part.
Fig. 4 G is the circuit theory diagrams of the utility model FPGA module G part.
Fig. 4 H is the circuit theory diagrams of the utility model FPGA module H part.
Fig. 4 I is the circuit theory diagrams of the utility model FPGA module I part.
Fig. 4 J is the circuit theory diagrams of the utility model FPGA module J part.
Fig. 4 K is the circuit theory diagrams of the utility model FPGA module K part.
Fig. 4 L is the circuit theory diagrams of the utility model FPGA module L part.
Fig. 4 M is the circuit theory diagrams of the utility model FPGA module M part.
Fig. 5 is the circuit theory diagrams of the utility model ISP image-signal processor AP0101AT.
Fig. 6 is the circuit theory diagrams of the utility model imageing sensor AR0132AT.
Fig. 7 is the circuit theory diagrams of the utility model RTC real time clock circuit.
Fig. 8 is the circuit theory diagrams of the utility model FLASH flash memory circuit.
Fig. 9 is the circuit theory diagrams of the utility model DRAM memory circuitry.
Figure 10 is the circuit theory diagrams of the utility model configuring chip.
Figure 11 is the circuit theory diagrams of the utility model AVB ethernet module.
Description of reference numerals:
1-FPGA module; 2-RTC real time clock circuit; 3-FLASH flash memory circuit;
4-DRAM memory circuitry; 5-configuring chip; 6-AVB ethernet module;
7-ISP image-signal processor; 8-imageing sensor;
9-Network Video Surveillance video camera; 10-AVB network switch;
11-ground monitoring server; 12-video camera lifting plate; 13-camera housing;
14-camera lens; 15-housing contiguous block; 16-lifting plate contiguous block;
17-rotating shaft; 18-twisted-pair feeder interface; 19-power module.
Embodiment
As shown in Figure 1, the utility model comprises the multiple stage Network Video Surveillance video camera 9 being laid in underground coal mine, multiple stage Network Video Surveillance video camera 9 is all connected to the AVB network switch 10 by unshielded twisted pair and is connected with ground monitoring server 11 by the AVB network switch 10, as shown in Figure 2, multiple stage Network Video Surveillance video camera 9 includes video camera lifting plate 12, camera housing 13, embed the camera lens 14 be arranged on camera housing 13 and the video acquisition transmission circuit plate being arranged on camera housing 13 inside, the top of described camera housing 13 is provided with housing contiguous block 15, the geometric center position of described housing contiguous block 15 is provided with housing contiguous block centre bore, the bottom of described video camera lifting plate 12 is provided with the lifting plate contiguous block 16 that two pieces lay respectively at housing contiguous block 15 both sides, the geometric center position of two pieces of described lifting plate contiguous blocks 16 is provided with lifting plate contiguous block centre bore, described camera housing 13 and video camera lifting plate 12 are rotationally connected by the rotating shaft 17 through described housing contiguous block centre bore and two described lifting plate contiguous block centre bores, described video acquisition transmission circuit plate is integrated with video acquisition transmission circuit, as shown in Figure 3, described video acquisition transmission circuit comprises FPGA module 1 and the power module 19 for each electricity consumption module for power supply in described video acquisition transmission circuit, and RTC real time clock circuit 2, FLASH flash memory circuit 3, DRAM memory circuitry 4, configuring chip 5 and the AVB ethernet module 6 to connect with FPGA module 1, the input of described FPGA module 1 is connected to ISP image-signal processor 7, and the input of described ISP image-signal processor 7 is connected to imageing sensor 8, the ISP image-signal processor AP0101AT that described ISP image-signal processor 7 is produced for Aptina company, the imageing sensor AR0132AT that described imageing sensor 8 is produced for Aptina company, described AVB ethernet module 6 being connected with the twisted-pair feeder interface 18 for connecting unshielded twisted pair, being exposed on the outer surface of camera housing 13 outside described twisted-pair feeder interface 18.
In the present embodiment, described camera lens 14 is fish eye lens.Fish-eye visual range is large, and horizontal view angle is greater than 120 °, and vertical angle of view is greater than 120 °, makes whole Network Video Surveillance video camera 9 can monitor more interval.
As shown in Fig. 4 A ~ 4M, in the present embodiment, described FPGA module 1 is fpga chip EP3C5E144C8N.
As shown in Figure 5, in the present embodiment, DO0 ~ DO6 pin of described ISP image-signal processor AP0101AT is corresponding in turn to and connects with 73rd ~ 80 pins of described fpga chip EP3C5E144C8N, the DO7 pin of described ISP image-signal processor AP0101AT connects with the 83rd pin of described fpga chip EP3C5E144C8N, the SCLK pin of described ISP image-signal processor AP0101AT connects with the 84th pin of described fpga chip EP3C5E144C8N, and is connected with+3.3V the voltage output end of power module 19 by resistance R3, the SDA pin of described ISP image-signal processor AP0101AT connects with the 85th pin of described fpga chip EP3C5E144C8N, and is connected with+3.3V the voltage output end of power module 19 by resistance R2, the PCLK pin of described ISP image-signal processor AP0101AT connects with the 86th pin of described fpga chip EP3C5E144C8N, the ECLK pin of described ISP image-signal processor AP0101AT connects with the 87th pin of described fpga chip EP3C5E144C8N, the VS pin of described ISP image-signal processor AP0101AT connects with the 69th pin of described fpga chip EP3C5E144C8N, and the HS pin of described ISP image-signal processor AP0101AT connects with the 70th pin of described fpga chip EP3C5E144C8N, the NRST pin of described ISP image-signal processor AP0101AT is connected with+3.3V the voltage output end of power module 19 by resistance R1, the MSCLK pin of described ISP image-signal processor AP0101AT is connected with+1.8V the voltage output end of power module 19 by resistance R6, the MSDA pin of described ISP image-signal processor AP0101AT is connected with+1.8V the voltage output end of power module 19 by resistance R5, the STANDBY pin of described ISP image-signal processor AP0101AT is by resistance R7 ground connection, the FS pin of described ISP image-signal processor AP0101AT is by resistance R8 ground connection.
As shown in Figure 6, in the present embodiment, DO0 ~ DO11 pin of described imageing sensor AR0132AT is corresponding in turn to and connects with DI0 ~ DI11 pin of described ISP image-signal processor AP0101AT, the EXTCLK pin of described imageing sensor AR0132AT connects with the ECO pin of described ISP image-signal processor AP0101AT, the RST pin of described imageing sensor AR0132AT connects with the RSTO pin of described ISP image-signal processor AP0101AT, and connected with+1.8V the voltage output end of power module 19 by resistance R31, the SCLK pin of described imageing sensor AR0132AT connects with the MSCLK pin of described ISP image-signal processor AP0101AT, the SDA pin of described imageing sensor AR0132AT connects with the MSDA pin of described ISP image-signal processor AP0101AT, the PCLK pin of described imageing sensor AR0132AT connects with the PCLKI pin of described ISP image-signal processor AP0101AT, the FV pin of described imageing sensor AR0132AT connects with the FVI pin of described ISP image-signal processor AP0101AT, the LV pin of described imageing sensor AR0132AT connects with the LVI pin of described ISP image-signal processor AP0101AT, the TRIGGER pin of described imageing sensor AR0132AT connects with the TO pin of described ISP image-signal processor AP0101AT, the SADDR pin of described imageing sensor AR0132AT is connected with+1.8V the voltage output end of power module 19 by resistance R32, the OE pin of described imageing sensor AR0132AT is by resistance R33 ground connection.
As shown in Figure 7, in the present embodiment, described RTC real time clock circuit 2 comprises real-time timepiece chip ISL1208 and crystal oscillator Y1, 1st pin of described real-time timepiece chip ISL1208 connects with one end of crystal oscillator Y1, 2nd pin of described real-time timepiece chip ISL1208 connects with the other end of crystal oscillator Y1, 3rd pin of described real-time timepiece chip ISL1208 connects with+3.3V the voltage output end of power module 19, the 4th pin ground connection of described real-time timepiece chip ISL1208, 5th pin of described real-time timepiece chip ISL1208 connects with the 110th pin of described fpga chip EP3C5E144C8N, and connected with+3.3V the voltage output end of power module 19 by resistance R21, 6th pin of described real-time timepiece chip ISL1208 connects with the 111st pin of described fpga chip EP3C5E144C8N, and connected with+3.3V the voltage output end of power module 19 by resistance R20,7th pin of described real-time timepiece chip ISL1208 connects with the 24th pin of described fpga chip EP3C5E144C8N, and connected with+3.3V the voltage output end of power module 19 by resistance R19, the 8th pin of described real-time timepiece chip ISL1208 connects with+3.3V the voltage output end of power module 19.
As shown in Figure 8, in the present embodiment, described FLASH flash memory circuit 3 comprises chip H27U1G8F2B, and the 7th pin of described chip H27U1G8F2B connects with the 127th pin of described fpga chip EP3C5E144C8N, and is connected with+3.3V the voltage output end of power module 19 by resistance R12, 8th pin of described chip H27U1G8F2B connects with the 128th pin of described fpga chip EP3C5E144C8N, 9th pin of described chip H27U1G8F2B connects with the 129th pin of described fpga chip EP3C5E144C8N, 12nd pin and the 37th pin of described chip H27U1G8F2B all connect with+3.3V the voltage output end of power module 19, 13rd pin of described chip H27U1G8F2B and the equal ground connection of the 36th pin, 16th ~ 19 pins of described chip H27U1G8F2B are corresponding in turn to and connect with 132nd ~ 136 pins of described fpga chip EP3C5E144C8N, 29th ~ 32 pins of described chip H27U1G8F2B are corresponding in turn to and connect with 112nd ~ 115 pins of described fpga chip EP3C5E144C8N, 41st ~ 44 pins of described chip H27U1G8F2B are corresponding in turn to and connect with 119th ~ 124 pins of described fpga chip EP3C5E144C8N.
As shown in Figure 9, in the present embodiment, described DRAM memory circuitry 4 comprises chip K4S641632UC-70T, the 2nd of described chip K4S641632UC-70T, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51 and 53 pins are corresponding in turn to the with described fpga chip EP3C5E144C8N the 28th, 30, 31, 32, 33, 34, 38, 39, 54, 53, 52, 51, 50, 49, 46 and 44 pins connect, 19th pin of described chip K4S641632UC-70T connects with the 7th pin of described fpga chip EP3C5E144C8N, and connected with+3.3V the voltage output end of power module 19 by resistance R16, 16th pin of described chip K4S641632UC-70T connects with the 42nd pin of described fpga chip EP3C5E144C8N, and is connected with+3.3V the voltage output end of power module 19 by resistance R15, 17th pin of described chip K4S641632UC-70T connects with the 11st pin of described fpga chip EP3C5E144C8N, and is connected with+3.3V the voltage output end of power module 19 by resistance R14, 18th pin of described chip K4S641632UC-70T connects with the 10th pin of described fpga chip EP3C5E144C8N, and is connected with+3.3V the voltage output end of power module 19 by resistance R13, the 23rd of described chip K4S641632UC-70T, 24, 25, 26, 29, 30, 31, 32, 33, 34, 22 and 35 pins are corresponding in turn to the with described fpga chip EP3C5E144C8N the 1st, 144, 143, 68, 67, 66, 65, 64, 60, 59, 2 and 58 pins connect, 20th and 21 pins of described chip K4S641632UC-70T are corresponding in turn to and connect with the 4th and 3 pins of described fpga chip EP3C5E144C8N, 37th pin of described chip K4S641632UC-70T connects with the 55th pin of described fpga chip EP3C5E144C8N, the 43rd pin that 38th pin of described chip K4S641632UC-70T is corresponding in turn to described fpga chip EP3C5E144C8N connects, and by electric capacity C22 ground connection.
As shown in Figure 10, in the present embodiment, described configuring chip 5 is chip EPCS64,1st pin of described chip EPCS64 connects with the 8th pin of described fpga chip EP3C5E144C8N, 2nd pin of described chip EPCS64 is connected with the 13rd pin of described fpga chip EP3C5E144C8N by resistance R35,3rd, 7 and 8 pins of described chip EPCS64 all connect with+3.3V the voltage output end of power module 19, and by electric capacity C27 ground connection, the 4th pin ground connection of described chip EPCS64; 5th pin of described chip EPCS64 connects with the 6th pin of described fpga chip EP3C5E144C8N, and the 6th pin of described chip EPCS64 is connected with the 12nd pin of described fpga chip EP3C5E144C8N by resistance R36.
As shown in figure 11, in the present embodiment, described AVB ethernet module 6 comprises AVB Ethernet chip BCM89810 and common mode inductance T1, described twisted-pair feeder interface 18 is four pin interface P2,8th pin of described AVB Ethernet chip BCM89810 connects with the 98th pin of described fpga chip EP3C5E144C8N, 26th pin of described AVB Ethernet chip BCM89810 connects with the 72nd pin of described fpga chip EP3C5E144C8N, 32nd pin of described AVB Ethernet chip BCM89810 and the 31st pin are corresponding in turn to and connect with the 137th pin of described fpga chip EP3C5E144C8N and the 138th pin, 28th pin of described AVB Ethernet chip BCM89810 and the 27th pin are corresponding in turn to and connect with the 141st pin of described fpga chip EP3C5E144C8N and the 142nd pin, 33rd pin of described AVB Ethernet chip BCM89810 connects with the 104th pin of described fpga chip EP3C5E144C8N, 35th pin of described AVB Ethernet chip BCM89810 connects with the 101st pin of described fpga chip EP3C5E144C8N, 39th pin of described AVB Ethernet chip BCM89810 and the 38th pin are corresponding in turn to and connect with the 105th pin of described fpga chip EP3C5E144C8N and the 106th pin, 37th pin of described AVB Ethernet chip BCM89810 and the 36th pin are corresponding in turn to and connect with the 125th pin of described fpga chip EP3C5E144C8N and the 126th pin, 40th pin of described AVB Ethernet chip BCM89810 connects with the 71st pin of described fpga chip EP3C5E144C8N, 46th pin of described AVB Ethernet chip BCM89810 connects with the 103rd pin of described fpga chip EP3C5E144C8N, 47th pin of described AVB Ethernet chip BCM89810 connects with the 99th pin of described fpga chip EP3C5E144C8N, and connected with+3.3V the voltage output end of power module 19 by resistance R41,48th pin of described AVB Ethernet chip BCM89810 connects with the 100th pin of described fpga chip EP3C5E144C8N, 14th pin of described AVB Ethernet chip BCM89810 be connected to the resistance R45 and resistance R46 that connect between the 15th pin, the link ground connection of described resistance R45 and resistance R46, 14th pin of described AVB Ethernet chip BCM89810 is connected with first input pin of common mode inductance T1 by electric capacity C48, 15th pin of described AVB Ethernet chip BCM89810 is connected with second input pin of common mode inductance T1 by electric capacity C47, first output pin of described common mode inductance T1 connects with the 2nd pin of four pin interface P2, second output pin of described common mode inductance T1 connects with the 3rd pin of four pin interface P2, 1st pin of described four pin interface P2 connects with+12V the voltage output end of power module 19, the 4th pin ground connection of described four pin interface P2.Wherein, AVB Ethernet chip BCM89810 be Broadcom company produce for the one in the physical layer transceiver of automotive networking, unshielded twisted pair can be adopted to connect up, reduce wiring cost.Common mode inductance T1 can attenuation common-mode electric current well, reaches the object of filtering, contributes to ensureing that unshielded twisted pair can transmit high-definition network video stream.
When the utility model uses, the video stream data that underground coal mine multiple stage Network Video Surveillance video camera 9 exports is transferred to the AVB network switch 10 by unshielded twisted pair, ground monitoring server 11 is transferred to again by the AVB network switch 10, ground monitoring personnel also at ground monitoring server 11 place can monitor and record the safety in production situation at underground work scene intuitively, carry out safety in production provide guarantee for colliery.Wherein, the operation principle of Network Video Surveillance video camera 9 is: the light signal that imageing sensor AR0132AT is received converts the current signal of light sensitive diode to, export in electrical signal form through signal condition sampling, ISP image-signal processor AP0101AT receives the signal of telecommunication that imageing sensor AR0132AT exports, control the time for exposure, export 45fps, the video data of 1280*960, FPGA module 1 receives the video data that ISP image-signal processor AP0101AT exports, carry out distortion correction, video compression, outputting video streams after coding packing, AVB ethernet module 6 receives the video flowing that FPGA module 1 exports, coding exports serial data, be connected with AVB Ethernet by unshielded twisted pair, for the monitoring host computer called data be connected on AVB Ethernet.
The above; it is only preferred embodiment of the present utility model; not the utility model is imposed any restrictions; every above embodiment is done according to the utility model technical spirit any simple modification, change and equivalent structure change, all still belong in the protection range of technical solutions of the utility model.
Claims (10)
1. a coal mine downhole safety produces network video monitor and control system, it is characterized in that: comprise the multiple stage Network Video Surveillance video camera (9) being laid in underground coal mine, multiple stage Network Video Surveillance video camera (9) is all connected to the AVB network switch (10) by unshielded twisted pair and is connected with ground monitoring server (11) by the AVB network switch (10), multiple stage Network Video Surveillance video camera (9) includes video camera lifting plate (12), camera housing (13), embedding is arranged on the camera lens (14) on camera housing (13) and is arranged on the inner video acquisition transmission circuit plate of camera housing (13), the top of described camera housing (13) is provided with housing contiguous block (15), the geometric center position of described housing contiguous block (15) is provided with housing contiguous block centre bore, the bottom of described video camera lifting plate (12) is provided with the lifting plate contiguous block (16) that two pieces lay respectively at housing contiguous block (15) both sides, the geometric center position of two pieces of described lifting plate contiguous blocks (16) is provided with lifting plate contiguous block centre bore, described camera housing (13) and video camera lifting plate (12) are rotationally connected by the rotating shaft (17) through described housing contiguous block centre bore and two described lifting plate contiguous block centre bores, described video acquisition transmission circuit plate is integrated with video acquisition transmission circuit, described video acquisition transmission circuit comprises FPGA module (1) and the power module (19) for each electricity consumption module for power supply in described video acquisition transmission circuit, and the RTC real time clock circuit (2) to connect with FPGA module (1), FLASH flash memory circuit (3), DRAM memory circuitry (4), configuring chip (5) and AVB ethernet module (6), the input of described FPGA module (1) is connected to ISP image-signal processor (7), the input of described ISP image-signal processor (7) is connected to imageing sensor (8), the ISP image-signal processor AP0101AT that described ISP image-signal processor (7) is produced for Apt ina company, the imageing sensor AR0132AT that described imageing sensor (8) is produced for Apt ina company, described AVB ethernet module (6) being connected with the twisted-pair feeder interface (18) for connecting unshielded twisted pair, being exposed on the outer surface of camera housing (13) outside described twisted-pair feeder interface (18).
2. produce network video monitor and control system according to a kind of coal mine downhole safety according to claim 1, it is characterized in that: described camera lens (14) is fish eye lens.
3. produce network video monitor and control system according to a kind of coal mine downhole safety according to claim 1, it is characterized in that: described FPGA module (1) is fpga chip EP3C5E144C8N.
4. produce network video monitor and control system according to a kind of coal mine downhole safety according to claim 3, it is characterized in that: DO0 ~ DO6 pin of described ISP image-signal processor AP0101AT is corresponding in turn to and connects with 73rd ~ 80 pins of described fpga chip EP3C5E144C8N, the DO7 pin of described ISP image-signal processor AP0101AT connects with the 83rd pin of described fpga chip EP3C5E144C8N, the SCLK pin of described ISP image-signal processor AP0101AT connects with the 84th pin of described fpga chip EP3C5E144C8N, and connected with+3.3V the voltage output end of power module (19) by resistance R3, the SDA pin of described ISP image-signal processor AP0101AT connects with the 85th pin of described fpga chip EP3C5E144C8N, and is connected with+3.3V the voltage output end of power module (19) by resistance R2, the PCLK pin of described ISP image-signal processor AP0101AT connects with the 86th pin of described fpga chip EP3C5E144C8N, the ECLK pin of described ISP image-signal processor AP0101AT connects with the 87th pin of described fpga chip EP3C5E144C8N, the VS pin of described ISP image-signal processor AP0101AT connects with the 69th pin of described fpga chip EP3C5E144C8N, and the HS pin of described ISP image-signal processor AP0101AT connects with the 70th pin of described fpga chip EP3C5E144C8N, the NRST pin of described ISP image-signal processor AP0101AT is connected with+3.3V the voltage output end of power module (19) by resistance R1, the MSCLK pin of described ISP image-signal processor AP0101AT is connected with+1.8V the voltage output end of power module (19) by resistance R6, the MSDA pin of described ISP image-signal processor AP0101AT is connected with+1.8V the voltage output end of power module (19) by resistance R5, the STANDBY pin of described ISP image-signal processor AP0101AT is by resistance R7 ground connection, the FS pin of described ISP image-signal processor AP0101AT is by resistance R8 ground connection.
5. produce network video monitor and control system according to a kind of coal mine downhole safety according to claim 4, it is characterized in that: DO0 ~ DO11 pin of described imageing sensor AR0132AT is corresponding in turn to and connects with DI 0 ~ DI11 pin of described ISP image-signal processor AP0101AT, the EXTCLK pin of described imageing sensor AR0132AT connects with the ECO pin of described ISP image-signal processor AP0101AT, the RST pin of described imageing sensor AR0132AT connects with the RSTO pin of described ISP image-signal processor AP0101AT, and connected with+1.8V the voltage output end of power module (19) by resistance R31, the SCLK pin of described imageing sensor AR0132AT connects with the MSCLK pin of described ISP image-signal processor AP0101AT, the SDA pin of described imageing sensor AR0132AT connects with the MSDA pin of described ISP image-signal processor AP0101AT, the PCLK pin of described imageing sensor AR0132AT connects with the PCLKI pin of described ISP image-signal processor AP0101AT, the FV pin of described imageing sensor AR0132AT connects with the FVI pin of described ISP image-signal processor AP0101AT, the LV pin of described imageing sensor AR0132AT connects with the LVI pin of described ISP image-signal processor AP0101AT, the TRIGGER pin of described imageing sensor AR0132AT connects with the TO pin of described ISP image-signal processor AP0101AT, the SADDR pin of described imageing sensor AR0132AT is connected with+1.8V the voltage output end of power module (19) by resistance R32, the OE pin of described imageing sensor AR0132AT is by resistance R33 ground connection.
6. produce network video monitor and control system according to a kind of coal mine downhole safety according to claim 3, it is characterized in that: described RTC real time clock circuit (2) comprises real-time timepiece chip ISL1208 and crystal oscillator Y1, 1st pin of described real-time timepiece chip ISL1208 connects with one end of crystal oscillator Y1, 2nd pin of described real-time timepiece chip ISL1208 connects with the other end of crystal oscillator Y1, 3rd pin of described real-time timepiece chip ISL1208 connects with+3.3V the voltage output end of power module (19), the 4th pin ground connection of described real-time timepiece chip ISL1208, 5th pin of described real-time timepiece chip ISL1208 connects with the 110th pin of described fpga chip EP3C5E144C8N, and connected with+3.3V the voltage output end of power module (19) by resistance R21, 6th pin of described real-time timepiece chip ISL1208 connects with the 111st pin of described fpga chip EP3C5E144C8N, and connected with+3.3V the voltage output end of power module (19) by resistance R20,7th pin of described real-time timepiece chip ISL1208 connects with the 24th pin of described fpga chip EP3C5E144C8N, and connected with+3.3V the voltage output end of power module (19) by resistance R19, the 8th pin of described real-time timepiece chip ISL1208 connects with+3.3V the voltage output end of power module (19).
7. produce network video monitor and control system according to a kind of coal mine downhole safety according to claim 3, it is characterized in that: described FLASH flash memory circuit (3) comprises chip H27U1G8F2B, 7th pin of described chip H27U1G8F2B connects with the 127th pin of described fpga chip EP3C5E144C8N, and is connected with+3.3V the voltage output end of power module (19) by resistance R12, 8th pin of described chip H27U1G8F2B connects with the 128th pin of described fpga chip EP3C5E144C8N, 9th pin of described chip H27U1G8F2B connects with the 129th pin of described fpga chip EP3C5E144C8N, 12nd pin and the 37th pin of described chip H27U1G8F2B all connect with+3.3V the voltage output end of power module (19), 13rd pin of described chip H27U1G8F2B and the equal ground connection of the 36th pin, 16th ~ 19 pins of described chip H27U1G8F2B are corresponding in turn to and connect with 132nd ~ 136 pins of described fpga chip EP3C5E144C8N, 29th ~ 32 pins of described chip H27U1G8F2B are corresponding in turn to and connect with 112nd ~ 115 pins of described fpga chip EP3C5E144C8N, 41st ~ 44 pins of described chip H27U1G8F2B are corresponding in turn to and connect with 119th ~ 124 pins of described fpga chip EP3C5E144C8N.
8. produce network video monitor and control system according to a kind of coal mine downhole safety according to claim 3, it is characterized in that: described DRAM memory circuitry (4) comprises chip K4S641632UC-70T, the 2nd of described chip K4S641632UC-70T, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51 and 53 pins are corresponding in turn to the with described fpga chip EP3C5E144C8N the 28th, 30, 31, 32, 33, 34, 38, 39, 54, 53, 52, 51, 50, 49, 46 and 44 pins connect, 19th pin of described chip K4S641632UC-70T connects with the 7th pin of described fpga chip EP3C5E144C8N, and connected with+3.3V the voltage output end of power module (19) by resistance R16, 16th pin of described chip K4S641632UC-70T connects with the 42nd pin of described fpga chip EP3C5E144C8N, and is connected with+3.3V the voltage output end of power module (19) by resistance R15, 17th pin of described chip K4S641632UC-70T connects with the 11st pin of described fpga chip EP3C5E144C8N, and is connected with+3.3V the voltage output end of power module (19) by resistance R14, 18th pin of described chip K4S641632UC-70T connects with the 10th pin of described fpga chip EP3C5E144C8N, and is connected with+3.3V the voltage output end of power module (19) by resistance R13, the 23rd of described chip K4S641632UC-70T, 24, 25, 26, 29, 30, 31, 32, 33, 34, 22 and 35 pins are corresponding in turn to the with described fpga chip EP3C5E144C8N the 1st, 144, 143, 68, 67, 66, 65, 64, 60, 59, 2 and 58 pins connect, 20th and 21 pins of described chip K4S641632UC-70T are corresponding in turn to and connect with the 4th and 3 pins of described fpga chip EP3C5E144C8N, 37th pin of described chip K4S641632UC-70T connects with the 55th pin of described fpga chip EP3C5E144C8N, the 43rd pin that 38th pin of described chip K4S641632UC-70T is corresponding in turn to described fpga chip EP3C5E144C8N connects, and by electric capacity C22 ground connection.
9. produce network video monitor and control system according to a kind of coal mine downhole safety according to claim 3, it is characterized in that: described configuring chip (5) is chip EPCS64, 1st pin of described chip EPCS64 connects with the 8th pin of described fpga chip EP3C5E144C8N, 2nd pin of described chip EPCS64 is connected with the 13rd pin of described fpga chip EP3C5E144C8N by resistance R35, the 3rd of described chip EPCS64, 7 and 8 pins all connect with+3.3V the voltage output end of power module (19), and by electric capacity C27 ground connection, the 4th pin ground connection of described chip EPCS64, 5th pin of described chip EPCS64 connects with the 6th pin of described fpga chip EP3C5E144C8N, and the 6th pin of described chip EPCS64 is connected with the 12nd pin of described fpga chip EP3C5E144C8N by resistance R36.
10. produce network video monitor and control system according to a kind of coal mine downhole safety according to claim 3, it is characterized in that: described AVB ethernet module (6) comprises AVB Ethernet chip BCM89810 and common mode inductance T1, described twisted-pair feeder interface (18) is four pin interface P2,8th pin of described AVB Ethernet chip BCM89810 connects with the 98th pin of described fpga chip EP3C5E144C8N, 26th pin of described AVB Ethernet chip BCM89810 connects with the 72nd pin of described fpga chip EP3C5E144C8N, 32nd pin of described AVB Ethernet chip BCM89810 and the 31st pin are corresponding in turn to and connect with the 137th pin of described fpga chip EP3C5E144C8N and the 138th pin, 28th pin of described AVB Ethernet chip BCM89810 and the 27th pin are corresponding in turn to and connect with the 141st pin of described fpga chip EP3C5E144C8N and the 142nd pin, 33rd pin of described AVB Ethernet chip BCM89810 connects with the 104th pin of described fpga chip EP3C5E144C8N, 35th pin of described AVB Ethernet chip BCM89810 connects with the 101st pin of described fpga chip EP3C5E144C8N, 39th pin of described AVB Ethernet chip BCM89810 and the 38th pin are corresponding in turn to and connect with the 105th pin of described fpga chip EP3C5E144C8N and the 106th pin, 37th pin of described AVB Ethernet chip BCM89810 and the 36th pin are corresponding in turn to and connect with the 125th pin of described fpga chip EP3C5E144C8N and the 126th pin, 40th pin of described AVB Ethernet chip BCM89810 connects with the 71st pin of described fpga chip EP3C5E144C8N, 46th pin of described AVB Ethernet chip BCM89810 connects with the 103rd pin of described fpga chip EP3C5E144C8N, 47th pin of described AVB Ethernet chip BCM89810 connects with the 99th pin of described fpga chip EP3C5E144C8N, and connected with+3.3V the voltage output end of power module (19) by resistance R41,48th pin of described AVB Ethernet chip BCM89810 connects with the 100th pin of described fpga chip EP3C5E144C8N, 14th pin of described AVB Ethernet chip BCM89810 be connected to the resistance R45 and resistance R46 that connect between the 15th pin, the link ground connection of described resistance R45 and resistance R46, 14th pin of described AVB Ethernet chip BCM89810 is connected with first input pin of common mode inductance T1 by electric capacity C48, 15th pin of described AVB Ethernet chip BCM89810 is connected with second input pin of common mode inductance T1 by electric capacity C47, first output pin of described common mode inductance T1 connects with the 2nd pin of four pin interface P2, second output pin of described common mode inductance T1 connects with the 3rd pin of four pin interface P2, 1st pin of described four pin interface P2 connects with+12V the voltage output end of power module (19), the 4th pin ground connection of described four pin interface P2.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112511790A (en) * | 2019-09-16 | 2021-03-16 | 国网山东省电力公司东营市河口区供电公司 | Coal mine high-speed image acquisition and noise reduction system based on FPGA and processing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112511790A (en) * | 2019-09-16 | 2021-03-16 | 国网山东省电力公司东营市河口区供电公司 | Coal mine high-speed image acquisition and noise reduction system based on FPGA and processing method |
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