CN204442573U

CN204442573U - A kind of underground coal mine network video monitor terminal circuit

Info

Publication number: CN204442573U
Application number: CN201520190839.6U
Authority: CN
Inventors: 马宪民; 景宁波
Original assignee: Xian University of Science and Technology
Current assignee: Xian University of Science and Technology
Priority date: 2015-03-31
Filing date: 2015-03-31
Publication date: 2015-07-01
Anticipated expiration: 2025-03-31

Abstract

The utility model discloses a kind of underground coal mine network video monitor terminal circuit, the RTC real time clock circuit comprising FPGA module and connect with FPGA module, FLASH flash memory circuit, DRAM memory circuitry, configuring chip and AVB ethernet module, the input of described FPGA module is connected to ISP image-signal processor, and the input of described ISP image-signal processor is connected to imageing sensor; Described ISP image-signal processor is the ISP image-signal processor AP0101AT that Aptina company produces, and described imageing sensor is the imageing sensor AR0132AT that Aptina company produces.The utility model can ensure the accurate synchronization of multiple video streaming, is convenient to carry out multiple terminals splicing, reduces the field wiring cost of network video monitor terminal, dynamic range is large, ensure that the quality of Network Video Surveillance picture, practical, application value is high.

Description

A kind of underground coal mine network video monitor terminal circuit

Technical field

The utility model belongs to Network Video Surveillance technical field, is specifically related to a kind of underground coal mine network video monitor terminal circuit.

Background technology

In the U.S., colliery realizes high mechanization, and underground work personnel are little, and job specification, tunnel is unobstructed, once have an accident, be easy to withdraw, injures and deaths are little.And in China, mining mechanization degree is only 45%, miner troop be greatly educational level lower, train limited rural migrant worker, even there is the serious violation phenomenon such as down-hole smoking.Numerous miners like this, in the operating environment of highly dangerous, very easily have an accident, create greater casualties.The reason that important coal mining accident occurs is mainly reflected in: the information communication of ground and personnel in the pit not in time, ground staff is difficult to distribution and the handling situations of dynamically grasping personnel in the pit in time, once coal mining accident occurs, the efficiency of rescue and relief work, safety first-aid is low, searches and rescues weak effect.At present, coal mine operation is because away from ground, with a varied topography, bad environments, inconvenience is linked up with ground staff, if utilize Active Eyes, ground monitoring personnel then can directly monitor down-hole situation in real time, can not only monitor and record the safety in production situation at underground work scene intuitively, and energy Timeliness coverage accident potential, prevent trouble before it happens, also relevant first-hand image document can be provided for ex-post analysis accident, meanwhile, the relevant supervision department of higher level also can be checked by network remote and carry out situation, proposes amelioration method.But also there is following defect and deficiency in the Video Monitoring Terminal being used in underground coal mine in prior art:

1, cannot accurate synchronization between multiple terminal.When current underground coal mine network video monitor terminal carries out networking, main employing business Ethernet transmitting video-frequency flow, meet IEEE802.3 standard.Business Ethernet appears at 1972 the earliest, take office automation as target design, and do not consider the accurate synchronization problem between multiple terminal, transmission delay has uncertainty.Multiple terminal carries out the nonsynchronous problem of video-splicing life period, cannot realize real seamless spliced.

2, operating temperature range is narrow, and hot environment cannot normally work.Current underground coal mine network video monitor terminal circuit grade is generally business level, and maximum operating temperature is less than 70 degree, and under some particular surroundingss of underground coal mine, equipment cannot normally use.As accident rescue is on-the-spot, before ambient temperature does not drop to normal range (NR), more early obtain live video data better.

3, wiring cost is high.Current underground coal mine Network Video Surveillance wiring adopts optical fiber or fire-retardant netting twine, and cost is higher, is unfavorable for large-scale use.

4, network video monitor terminal circuit dynamic range is inadequate.Current underground coal mine network video monitor terminal circuit is dynamically generally all less than 90db, if monitor terminal installation site is not chosen, be easy to the phenomenon occurring that dynamic range is inadequate, there is the problem that partial exposure is not enough and local is over-exposed simultaneously, affect the quality of monitored picture.

Utility model content

Technical problem to be solved in the utility model is for above-mentioned deficiency of the prior art, a kind of underground coal mine network video monitor terminal circuit is provided, it can ensure the accurate synchronization of multiple video streaming, be convenient to carry out multiple terminals splicing, greatly reduce the field wiring cost of network video monitor terminal, dynamic range is large, ensure that the quality of Network Video Surveillance picture, practical, application value is high.

For solving the problems of the technologies described above, the technical solution adopted in the utility model is: a kind of underground coal mine network video monitor terminal circuit, it is characterized in that: the RTC real time clock circuit comprising FPGA module and connect with FPGA module, FLASH flash memory circuit, DRAM memory circuitry, configuring chip and AVB ethernet module, the input of described FPGA module is connected to ISP image-signal processor, and the input of described ISP image-signal processor is connected to imageing sensor; Described ISP image-signal processor is the ISP image-signal processor AP0101AT that Aptina company produces, and described imageing sensor is the imageing sensor AR0132AT that Aptina company produces.

Above-mentioned a kind of underground coal mine network video monitor terminal circuit, is characterized in that: described FPGA module is fpga chip EP3C5E144C8N.

Above-mentioned a kind of underground coal mine network video monitor terminal circuit, it is characterized in that: DO0 ~ DO6 pin of described ISP image-signal processor AP0101AT is corresponding in turn to and connects with 73rd ~ 80 pins of described fpga chip EP3C5E144C8N, the DO7 pin of described ISP image-signal processor AP0101AT connects with the 83rd pin of described fpga chip EP3C5E144C8N, the SCLK pin of described ISP image-signal processor AP0101AT connects with the 84th pin of described fpga chip EP3C5E144C8N, and is connected with the output of+3.3V power supply by resistance R3; The SDA pin of described ISP image-signal processor AP0101AT connects with the 85th pin of described fpga chip EP3C5E144C8N, and is connected with the output of+3.3V power supply by resistance R2; The PCLK pin of described ISP image-signal processor AP0101AT connects with the 86th pin of described fpga chip EP3C5E144C8N, the ECLK pin of described ISP image-signal processor AP0101AT connects with the 87th pin of described fpga chip EP3C5E144C8N, the VS pin of described ISP image-signal processor AP0101AT connects with the 69th pin of described fpga chip EP3C5E144C8N, and the HS pin of described ISP image-signal processor AP0101AT connects with the 70th pin of described fpga chip EP3C5E144C8N; The NRST pin of described ISP image-signal processor AP0101AT is connected with the output of+3.3V power supply by resistance R1, the MSCLK pin of described ISP image-signal processor AP0101AT is connected with the output of+1.8V power supply by resistance R6, the MSDA pin of described ISP image-signal processor AP0101AT is connected with the output of+1.8V power supply by resistance R5, the STANDBY pin of described ISP image-signal processor AP0101AT is by resistance R7 ground connection, and the FS pin of described ISP image-signal processor AP0101AT is by resistance R8 ground connection.

Above-mentioned a kind of underground coal mine network video monitor terminal circuit, it is characterized in that: DO0 ~ DO11 pin of described imageing sensor AR0132AT is corresponding in turn to and connects with DI0 ~ DI11 pin of described ISP image-signal processor AP0101AT, the EXTCLK pin of described imageing sensor AR0132AT connects with the ECO pin of described ISP image-signal processor AP0101AT, the RST pin of described imageing sensor AR0132AT connects with the RSTO pin of described ISP image-signal processor AP0101AT, and connected with the output of+1.8V power supply by resistance R31, the SCLK pin of described imageing sensor AR0132AT connects with the MSCLK pin of described ISP image-signal processor AP0101AT, the SDA pin of described imageing sensor AR0132AT connects with the MSDA pin of described ISP image-signal processor AP0101AT, the PCLK pin of described imageing sensor AR0132AT connects with the PCLKI pin of described ISP image-signal processor AP0101AT, the FV pin of described imageing sensor AR0132AT connects with the FVI pin of described ISP image-signal processor AP0101AT, the LV pin of described imageing sensor AR0132AT connects with the LVI pin of described ISP image-signal processor AP0101AT, the TRIGGER pin of described imageing sensor AR0132AT connects with the TO pin of described ISP image-signal processor AP0101AT, the SADDR pin of described imageing sensor AR0132AT is connected with the output of+1.8V power supply by resistance R32, the OE pin of described imageing sensor AR0132AT is by resistance R33 ground connection.

Above-mentioned a kind of underground coal mine network video monitor terminal circuit, it is characterized in that: described RTC real time clock circuit comprises real-time timepiece chip ISL1208 and crystal oscillator Y1, 1st pin of described real-time timepiece chip ISL1208 connects with one end of crystal oscillator Y1, 2nd pin of described real-time timepiece chip ISL1208 connects with the other end of crystal oscillator Y1, 3rd pin of described real-time timepiece chip ISL1208 connects with the output of+3.3V power supply, the 4th pin ground connection of described real-time timepiece chip ISL1208, 5th pin of described real-time timepiece chip ISL1208 connects with the 110th pin of described fpga chip EP3C5E144C8N, and connected with the output of+3.3V power supply by resistance R21, 6th pin of described real-time timepiece chip ISL1208 connects with the 111st pin of described fpga chip EP3C5E144C8N, and connected with the output of+3.3V power supply by resistance R20,7th pin of described real-time timepiece chip ISL1208 connects with the 24th pin of described fpga chip EP3C5E144C8N, and connected with the output of+3.3V power supply by resistance R19, the 8th pin of described real-time timepiece chip ISL1208 connects with the output of+3.3V power supply.

Above-mentioned a kind of underground coal mine network video monitor terminal circuit, it is characterized in that: described FLASH flash memory circuit comprises chip H27U1G8F2B, 7th pin of described chip H27U1G8F2B connects with the 127th pin of described fpga chip EP3C5E144C8N, and is connected with the output of+3.3V power supply by resistance R12, 8th pin of described chip H27U1G8F2B connects with the 128th pin of described fpga chip EP3C5E144C8N, 9th pin of described chip H27U1G8F2B connects with the 129th pin of described fpga chip EP3C5E144C8N, 12nd pin and the 37th pin of described chip H27U1G8F2B all connect with the output of+3.3V power supply, 13rd pin of described chip H27U1G8F2B and the equal ground connection of the 36th pin, 16th ~ 19 pins of described chip H27U1G8F2B are corresponding in turn to and connect with 132nd ~ 136 pins of described fpga chip EP3C5E144C8N, 29th ~ 32 pins of described chip H27U1G8F2B are corresponding in turn to and connect with 112nd ~ 115 pins of described fpga chip EP3C5E144C8N, 41st ~ 44 pins of described chip H27U1G8F2B are corresponding in turn to and connect with 119th ~ 124 pins of described fpga chip EP3C5E144C8N.

Above-mentioned a kind of underground coal mine network video monitor terminal circuit, it is characterized in that: described DRAM memory circuitry comprises chip K4S641632UC-70T, the 2nd of described chip K4S641632UC-70T, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51 and 53 pins are corresponding in turn to the with described fpga chip EP3C5E144C8N the 28th, 30, 31, 32, 33, 34, 38, 39, 54, 53, 52, 51, 50, 49, 46 and 44 pins connect, 19th pin of described chip K4S641632UC-70T connects with the 7th pin of described fpga chip EP3C5E144C8N, and connected with the output of+3.3V power supply by resistance R16, 16th pin of described chip K4S641632UC-70T connects with the 42nd pin of described fpga chip EP3C5E144C8N, and is connected with the output of+3.3V power supply by resistance R15, 17th pin of described chip K4S641632UC-70T connects with the 11st pin of described fpga chip EP3C5E144C8N, and is connected with the output of+3.3V power supply by resistance R14, 18th pin of described chip K4S641632UC-70T connects with the 10th pin of described fpga chip EP3C5E144C8N, and is connected with the output of+3.3V power supply by resistance R13, the 23rd of described chip K4S641632UC-70T, 24, 25, 26, 29, 30, 31, 32, 33, 34, 22 and 35 pins are corresponding in turn to the with described fpga chip EP3C5E144C8N the 1st, 144, 143, 68, 67, 66, 65, 64, 60, 59, 2 and 58 pins connect, 20th and 21 pins of described chip K4S641632UC-70T are corresponding in turn to and connect with the 4th and 3 pins of described fpga chip EP3C5E144C8N, 37th pin of described chip K4S641632UC-70T connects with the 55th pin of described fpga chip EP3C5E144C8N, the 43rd pin that 38th pin of described chip K4S641632UC-70T is corresponding in turn to described fpga chip EP3C5E144C8N connects, and by electric capacity C22 ground connection.

Above-mentioned a kind of underground coal mine network video monitor terminal circuit, it is characterized in that: described configuring chip is chip EPCS64,1st pin of described chip EPCS64 connects with the 8th pin of described fpga chip EP3C5E144C8N, 2nd pin of described chip EPCS64 is connected with the 13rd pin of described fpga chip EP3C5E144C8N by resistance R35,3rd, 7 and 8 pins of described chip EPCS64 all connect with the output of+3.3V power supply, and by electric capacity C27 ground connection, the 4th pin ground connection of described chip EPCS64; 5th pin of described chip EPCS64 connects with the 6th pin of described fpga chip EP3C5E144C8N, and the 6th pin of described chip EPCS64 is connected with the 12nd pin of described fpga chip EP3C5E144C8N by resistance R36.

Above-mentioned a kind of underground coal mine network video monitor terminal circuit, it is characterized in that: described AVB ethernet module comprises AVB Ethernet chip BCM89810, common mode inductance T1 and the four pin interface P2 for being connected unshielded twisted pair, 8th pin of described AVB Ethernet chip BCM89810 connects with the 98th pin of described fpga chip EP3C5E144C8N, 26th pin of described AVB Ethernet chip BCM89810 connects with the 72nd pin of described fpga chip EP3C5E144C8N, 32nd pin of described AVB Ethernet chip BCM89810 and the 31st pin are corresponding in turn to and connect with the 137th pin of described fpga chip EP3C5E144C8N and the 138th pin, 28th pin of described AVB Ethernet chip BCM89810 and the 27th pin are corresponding in turn to and connect with the 141st pin of described fpga chip EP3C5E144C8N and the 142nd pin, 33rd pin of described AVB Ethernet chip BCM89810 connects with the 104th pin of described fpga chip EP3C5E144C8N, 35th pin of described AVB Ethernet chip BCM89810 connects with the 101st pin of described fpga chip EP3C5E144C8N, 39th pin of described AVB Ethernet chip BCM89810 and the 38th pin are corresponding in turn to and connect with the 105th pin of described fpga chip EP3C5E144C8N and the 106th pin, 37th pin of described AVB Ethernet chip BCM89810 and the 36th pin are corresponding in turn to and connect with the 125th pin of described fpga chip EP3C5E144C8N and the 126th pin, 40th pin of described AVB Ethernet chip BCM89810 connects with the 71st pin of described fpga chip EP3C5E144C8N, 46th pin of described AVB Ethernet chip BCM89810 connects with the 103rd pin of described fpga chip EP3C5E144C8N, 47th pin of described AVB Ethernet chip BCM89810 connects with the 99th pin of described fpga chip EP3C5E144C8N, and connected with the output of+3.3V power supply by resistance R41,48th pin of described AVB Ethernet chip BCM89810 connects with the 100th pin of described fpga chip EP3C5E144C8N, 14th pin of described AVB Ethernet chip BCM89810 be connected to the resistance R45 and resistance R46 that connect between the 15th pin, the link ground connection of described resistance R45 and resistance R46, 14th pin of described AVB Ethernet chip BCM89810 is connected with first input pin of common mode inductance T1 by electric capacity C48, 15th pin of described AVB Ethernet chip BCM89810 is connected with second input pin of common mode inductance T1 by electric capacity C47, first output pin of described common mode inductance T1 connects with the 2nd pin of four pin interface P2, second output pin of described common mode inductance T1 connects with the 3rd pin of four pin interface P2, 1st pin of described four pin interface P2 connects with the output of+12V power supply, the 4th pin ground connection of described four pin interface P2.

The utility model compared with prior art has the following advantages:

1, can accurate synchronization between multiple terminal.The utility model have employed AVB Ethernet chip BCM89810 and peripheral circuit forms AVB ethernet module, can increase timestamp, ensure that the accurate synchronization of multiple video streaming, be convenient to carry out multiple terminals splicing for message transmission.

2, operating temperature range is wide.The imageing sensor AR0132AT that the utility model adopts and ISP image-signal processor AP0101AT, and FPGA module, RTC real time clock circuit, FLASH flash memory circuit, DRAM memory circuitry, configuring chip and AVB ethernet module are wide temperature level chip, make the operating temperature range of whole circuit be-40 DEG C ~+105 DEG C, can use under rescue acquisition environment.

3, wiring cost is low.The utility model is applied on underground coal mine network video monitor terminal, when multiple underground coal mine network video monitor terminal carries out networking, employing unshielded twisted pair connects up, greatly reduce the field wiring cost of network video monitor terminal, and make traditional unshielded twisted pair can transmit high-definition network video stream.

4, network video monitor terminal circuit dynamic range is large.The utility model have employed wide Dynamic IS P image-signal processor AP0101AT, and dynamic range is greater than 115db, meets the requirement of subsurface environment HD video, ensure that the quality of Network Video Surveillance picture.

5, of the present utility modelly to apply, significantly can improve the monitoring effect of underground coal mine network video monitor terminal, be convenient to ground monitoring personnel directly monitor in real time down-hole situation, can monitor and record the safety in production situation at underground work scene intuitively, and energy Timeliness coverage accident potential, prevent trouble before it happens, also relevant first-hand image document can be provided for ex-post analysis accident, practical, result of use is good, and application value is high.

In sum, the utility model can ensure the accurate synchronization of multiple video streaming, is convenient to carry out multiple terminals splicing, greatly reduce the field wiring cost of network video monitor terminal, dynamic range is large, ensure that the quality of Network Video Surveillance picture, practical, application value is high.

Below by drawings and Examples, the technical solution of the utility model is described in further detail.

Accompanying drawing explanation

Fig. 1 is schematic block circuit diagram of the present utility model.

Fig. 2 A is the circuit theory diagrams of the utility model FPGA module part A.

Fig. 2 B is the circuit theory diagrams of the utility model FPGA module part B.

Fig. 2 C is the circuit theory diagrams of the utility model FPGA module C part.

Fig. 2 D is the circuit theory diagrams of the utility model FPGA module D part.

Fig. 2 E is the circuit theory diagrams of the utility model FPGA module E part.

Fig. 2 F is the circuit theory diagrams of the utility model FPGA module F part.

Fig. 2 G is the circuit theory diagrams of the utility model FPGA module G part.

Fig. 2 H is the circuit theory diagrams of the utility model FPGA module H part.

Fig. 2 I is the circuit theory diagrams of the utility model FPGA module I part.

Fig. 2 J is the circuit theory diagrams of the utility model FPGA module J part.

Fig. 2 K is the circuit theory diagrams of the utility model FPGA module K part.

Fig. 2 L is the circuit theory diagrams of the utility model FPGA module L part.

Fig. 2 M is the circuit theory diagrams of the utility model FPGA module M part.

Fig. 3 is the circuit theory diagrams of the utility model ISP image-signal processor AP0101AT.

Fig. 4 is the circuit theory diagrams of the utility model imageing sensor AR0132AT.

Fig. 5 is the circuit theory diagrams of the utility model RTC real time clock circuit.

Fig. 6 is the circuit theory diagrams of the utility model FLASH flash memory circuit.

Fig. 7 is the circuit theory diagrams of the utility model DRAM memory circuitry.

Fig. 8 is the circuit theory diagrams of the utility model configuring chip.

Fig. 9 is the circuit theory diagrams of the utility model AVB ethernet module.

Description of reference numerals:

1-FPGA module; 2-RTC real time clock circuit; 3-FLASH flash memory circuit;

4-DRAM memory circuitry; 5-configuring chip; 6-AVB ethernet module;

7-ISP image-signal processor; 8-imageing sensor.

Embodiment

As shown in Figure 1, RTC real time clock circuit 2, FLASH flash memory circuit 3, DRAM memory circuitry 4, configuring chip 5 and AVB ethernet module 6 that the utility model comprises FPGA module 1 and connects with FPGA module 1, the input of described FPGA module 1 is connected to ISP image-signal processor 7, and the input of described ISP image-signal processor 7 is connected to imageing sensor 8; The ISP image-signal processor AP0101AT that described ISP image-signal processor 7 is produced for Aptina company, the imageing sensor AR0132AT that described imageing sensor 8 is produced for Aptina company.

As shown in Fig. 2 A ~ 2M, in the present embodiment, described FPGA module 1 is fpga chip EP3C5E144C8N.

As shown in Figure 3, in the present embodiment, DO0 ~ DO6 pin of described ISP image-signal processor AP0101AT is corresponding in turn to and connects with 73rd ~ 80 pins of described fpga chip EP3C5E144C8N, the DO7 pin of described ISP image-signal processor AP0101AT connects with the 83rd pin of described fpga chip EP3C5E144C8N, the SCLK pin of described ISP image-signal processor AP0101AT connects with the 84th pin of described fpga chip EP3C5E144C8N, and is connected with the output of+3.3V power supply by resistance R3; The SDA pin of described ISP image-signal processor AP0101AT connects with the 85th pin of described fpga chip EP3C5E144C8N, and is connected with the output of+3.3V power supply by resistance R2; The PCLK pin of described ISP image-signal processor AP0101AT connects with the 86th pin of described fpga chip EP3C5E144C8N, the ECLK pin of described ISP image-signal processor AP0101AT connects with the 87th pin of described fpga chip EP3C5E144C8N, the VS pin of described ISP image-signal processor AP0101AT connects with the 69th pin of described fpga chip EP3C5E144C8N, and the HS pin of described ISP image-signal processor AP0101AT connects with the 70th pin of described fpga chip EP3C5E144C8N; The NRST pin of described ISP image-signal processor AP0101AT is connected with the output of+3.3V power supply by resistance R1, the MSCLK pin of described ISP image-signal processor AP0101AT is connected with the output of+1.8V power supply by resistance R6, the MSDA pin of described ISP image-signal processor AP0101AT is connected with the output of+1.8V power supply by resistance R5, the STANDBY pin of described ISP image-signal processor AP0101AT is by resistance R7 ground connection, and the FS pin of described ISP image-signal processor AP0101AT is by resistance R8 ground connection.

As shown in Figure 4, in the present embodiment, DO0 ~ DO11 pin of described imageing sensor AR0132AT is corresponding in turn to and connects with DI0 ~ DI11 pin of described ISP image-signal processor AP0101AT, the EXTCLK pin of described imageing sensor AR0132AT connects with the ECO pin of described ISP image-signal processor AP0101AT, the RST pin of described imageing sensor AR0132AT connects with the RSTO pin of described ISP image-signal processor AP0101AT, and connected with the output of+1.8V power supply by resistance R31, the SCLK pin of described imageing sensor AR0132AT connects with the MSCLK pin of described ISP image-signal processor AP0101AT, the SDA pin of described imageing sensor AR0132AT connects with the MSDA pin of described ISP image-signal processor AP0101AT, the PCLK pin of described imageing sensor AR0132AT connects with the PCLKI pin of described ISP image-signal processor AP0101AT, the FV pin of described imageing sensor AR0132AT connects with the FVI pin of described ISP image-signal processor AP0101AT, the LV pin of described imageing sensor AR0132AT connects with the LVI pin of described ISP image-signal processor AP0101AT, the TRIGGER pin of described imageing sensor AR0132AT connects with the TO pin of described ISP image-signal processor AP0101AT, the SADDR pin of described imageing sensor AR0132AT is connected with the output of+1.8V power supply by resistance R32, the OE pin of described imageing sensor AR0132AT is by resistance R33 ground connection.

As shown in Figure 5, in the present embodiment, described RTC real time clock circuit 2 comprises real-time timepiece chip ISL1208 and crystal oscillator Y1, 1st pin of described real-time timepiece chip ISL1208 connects with one end of crystal oscillator Y1, 2nd pin of described real-time timepiece chip ISL1208 connects with the other end of crystal oscillator Y1, 3rd pin of described real-time timepiece chip ISL1208 connects with the output of+3.3V power supply, the 4th pin ground connection of described real-time timepiece chip ISL1208, 5th pin of described real-time timepiece chip ISL1208 connects with the 110th pin of described fpga chip EP3C5E144C8N, and connected with the output of+3.3V power supply by resistance R21, 6th pin of described real-time timepiece chip ISL1208 connects with the 111st pin of described fpga chip EP3C5E144C8N, and connected with the output of+3.3V power supply by resistance R20,7th pin of described real-time timepiece chip ISL1208 connects with the 24th pin of described fpga chip EP3C5E144C8N, and connected with the output of+3.3V power supply by resistance R19, the 8th pin of described real-time timepiece chip ISL1208 connects with the output of+3.3V power supply.

As shown in Figure 6, in the present embodiment, described FLASH flash memory circuit 3 comprises chip H27U1G8F2B, and the 7th pin of described chip H27U1G8F2B connects with the 127th pin of described fpga chip EP3C5E144C8N, and is connected with the output of+3.3V power supply by resistance R12, 8th pin of described chip H27U1G8F2B connects with the 128th pin of described fpga chip EP3C5E144C8N, 9th pin of described chip H27U1G8F2B connects with the 129th pin of described fpga chip EP3C5E144C8N, 12nd pin and the 37th pin of described chip H27U1G8F2B all connect with the output of+3.3V power supply, 13rd pin of described chip H27U1G8F2B and the equal ground connection of the 36th pin, 16th ~ 19 pins of described chip H27U1G8F2B are corresponding in turn to and connect with 132nd ~ 136 pins of described fpga chip EP3C5E144C8N, 29th ~ 32 pins of described chip H27U1G8F2B are corresponding in turn to and connect with 112nd ~ 115 pins of described fpga chip EP3C5E144C8N, 41st ~ 44 pins of described chip H27U1G8F2B are corresponding in turn to and connect with 119th ~ 124 pins of described fpga chip EP3C5E144C8N.

As shown in Figure 7, in the present embodiment, described DRAM memory circuitry 4 comprises chip K4S641632UC-70T, the 2nd of described chip K4S641632UC-70T, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51 and 53 pins are corresponding in turn to the with described fpga chip EP3C5E144C8N the 28th, 30, 31, 32, 33, 34, 38, 39, 54, 53, 52, 51, 50, 49, 46 and 44 pins connect, 19th pin of described chip K4S641632UC-70T connects with the 7th pin of described fpga chip EP3C5E144C8N, and connected with the output of+3.3V power supply by resistance R16, 16th pin of described chip K4S641632UC-70T connects with the 42nd pin of described fpga chip EP3C5E144C8N, and is connected with the output of+3.3V power supply by resistance R15, 17th pin of described chip K4S641632UC-70T connects with the 11st pin of described fpga chip EP3C5E144C8N, and is connected with the output of+3.3V power supply by resistance R14, 18th pin of described chip K4S641632UC-70T connects with the 10th pin of described fpga chip EP3C5E144C8N, and is connected with the output of+3.3V power supply by resistance R13, the 23rd of described chip K4S641632UC-70T, 24, 25, 26, 29, 30, 31, 32, 33, 34, 22 and 35 pins are corresponding in turn to the with described fpga chip EP3C5E144C8N the 1st, 144, 143, 68, 67, 66, 65, 64, 60, 59, 2 and 58 pins connect, 20th and 21 pins of described chip K4S641632UC-70T are corresponding in turn to and connect with the 4th and 3 pins of described fpga chip EP3C5E144C8N, 37th pin of described chip K4S641632UC-70T connects with the 55th pin of described fpga chip EP3C5E144C8N, the 43rd pin that 38th pin of described chip K4S641632UC-70T is corresponding in turn to described fpga chip EP3C5E144C8N connects, and by electric capacity C22 ground connection.

As shown in Figure 8, in the present embodiment, described configuring chip 5 is chip EPCS64,1st pin of described chip EPCS64 connects with the 8th pin of described fpga chip EP3C5E144C8N, 2nd pin of described chip EPCS64 is connected with the 13rd pin of described fpga chip EP3C5E144C8N by resistance R35,3rd, 7 and 8 pins of described chip EPCS64 all connect with the output of+3.3V power supply, and by electric capacity C27 ground connection, the 4th pin ground connection of described chip EPCS64; 5th pin of described chip EPCS64 connects with the 6th pin of described fpga chip EP3C5E144C8N, and the 6th pin of described chip EPCS64 is connected with the 12nd pin of described fpga chip EP3C5E144C8N by resistance R36.

As shown in Figure 9, in the present embodiment, described AVB ethernet module 6 comprises AVB Ethernet chip BCM89810, common mode inductance T1 and the four pin interface P2 for being connected unshielded twisted pair, 8th pin of described AVB Ethernet chip BCM89810 connects with the 98th pin of described fpga chip EP3C5E144C8N, 26th pin of described AVB Ethernet chip BCM89810 connects with the 72nd pin of described fpga chip EP3C5E144C8N, 32nd pin of described AVB Ethernet chip BCM89810 and the 31st pin are corresponding in turn to and connect with the 137th pin of described fpga chip EP3C5E144C8N and the 138th pin, 28th pin of described AVB Ethernet chip BCM89810 and the 27th pin are corresponding in turn to and connect with the 141st pin of described fpga chip EP3C5E144C8N and the 142nd pin, 33rd pin of described AVB Ethernet chip BCM89810 connects with the 104th pin of described fpga chip EP3C5E144C8N, 35th pin of described AVB Ethernet chip BCM89810 connects with the 101st pin of described fpga chip EP3C5E144C8N, 39th pin of described AVB Ethernet chip BCM89810 and the 38th pin are corresponding in turn to and connect with the 105th pin of described fpga chip EP3C5E144C8N and the 106th pin, 37th pin of described AVB Ethernet chip BCM89810 and the 36th pin are corresponding in turn to and connect with the 125th pin of described fpga chip EP3C5E144C8N and the 126th pin, 40th pin of described AVB Ethernet chip BCM89810 connects with the 71st pin of described fpga chip EP3C5E144C8N, 46th pin of described AVB Ethernet chip BCM89810 connects with the 103rd pin of described fpga chip EP3C5E144C8N, 47th pin of described AVB Ethernet chip BCM89810 connects with the 99th pin of described fpga chip EP3C5E144C8N, and connected with the output of+3.3V power supply by resistance R41,48th pin of described AVB Ethernet chip BCM89810 connects with the 100th pin of described fpga chip EP3C5E144C8N, 14th pin of described AVB Ethernet chip BCM89810 be connected to the resistance R45 and resistance R46 that connect between the 15th pin, the link ground connection of described resistance R45 and resistance R46, 14th pin of described AVB Ethernet chip BCM89810 is connected with first input pin of common mode inductance T1 by electric capacity C48, 15th pin of described AVB Ethernet chip BCM89810 is connected with second input pin of common mode inductance T1 by electric capacity C47, first output pin of described common mode inductance T1 connects with the 2nd pin of four pin interface P2, second output pin of described common mode inductance T1 connects with the 3rd pin of four pin interface P2, 1st pin of described four pin interface P2 connects with the output of+12V power supply, the 4th pin ground connection of described four pin interface P2.Wherein, AVB Ethernet chip BCM89810 be Broadcom company produce for the one in the physical layer transceiver of automotive networking, unshielded twisted pair can be adopted to connect up, reduce wiring cost.Common mode inductance T1 can attenuation common-mode electric current well, reaches the object of filtering, contributes to ensureing that unshielded twisted pair can transmit high-definition network video stream.

When the utility model uses, the light signal that imageing sensor AR0132AT is received converts the current signal of light sensitive diode to, export in electrical signal form through signal condition sampling, ISP image-signal processor AP0101AT receives the signal of telecommunication that imageing sensor AR0132AT exports, control the time for exposure, export 45fps, the video data of 1280*960, FPGA module 1 receives the video data that ISP image-signal processor AP0101AT exports, carry out distortion correction, video compression, outputting video streams after coding packing, AVB ethernet module 6 receives the video flowing that FPGA module 1 exports, coding exports serial data, be connected with AVB Ethernet by unshielded twisted pair, for the monitoring host computer called data be connected on AVB Ethernet.

The above; it is only preferred embodiment of the present utility model; not the utility model is imposed any restrictions; every above embodiment is done according to the utility model technical spirit any simple modification, change and equivalent structure change, all still belong in the protection range of technical solutions of the utility model.

Claims

1. a underground coal mine network video monitor terminal circuit, it is characterized in that: the RTC real time clock circuit (2), FLASH flash memory circuit (3), DRAM memory circuitry (4), configuring chip (5) and the AVB ethernet module (6) that comprise FPGA module (1) and connect with FPGA module (1), the input of described FPGA module (1) is connected to ISP image-signal processor (7), and the input of described ISP image-signal processor (7) is connected to imageing sensor (8); The ISP image-signal processor AP0101AT that described ISP image-signal processor (7) is produced for Aptina company, the imageing sensor AR0132AT that described imageing sensor (8) is produced for Apt ina company.

2. according to a kind of underground coal mine network video monitor terminal circuit according to claim 1, it is characterized in that: described FPGA module (1) is fpga chip EP3C5E144C8N.

3. according to a kind of underground coal mine network video monitor terminal circuit according to claim 2, it is characterized in that: DO0 ~ DO6 pin of described ISP image-signal processor AP0101AT is corresponding in turn to and connects with 73rd ~ 80 pins of described fpga chip EP3C5E144C8N, the DO7 pin of described ISP image-signal processor AP0101AT connects with the 83rd pin of described fpga chip EP3C5E144C8N, the SCLK pin of described ISP image-signal processor AP0101AT connects with the 84th pin of described fpga chip EP3C5E144C8N, and connected with the output of+3.3V power supply by resistance R3, the SDA pin of described ISP image-signal processor AP0101AT connects with the 85th pin of described fpga chip EP3C5E144C8N, and is connected with the output of+3.3V power supply by resistance R2, the PCLK pin of described ISP image-signal processor AP0101AT connects with the 86th pin of described fpga chip EP3C5E144C8N, the ECLK pin of described ISP image-signal processor AP0101AT connects with the 87th pin of described fpga chip EP3C5E144C8N, the VS pin of described ISP image-signal processor AP0101AT connects with the 69th pin of described fpga chip EP3C5E144C8N, and the HS pin of described ISP image-signal processor AP0101AT connects with the 70th pin of described fpga chip EP3C5E144C8N, the NRST pin of described ISP image-signal processor AP0101AT is connected with the output of+3.3V power supply by resistance R1, the MSCLK pin of described ISP image-signal processor AP0101AT is connected with the output of+1.8V power supply by resistance R6, the MSDA pin of described ISP image-signal processor AP0101AT is connected with the output of+1.8V power supply by resistance R5, the STANDBY pin of described ISP image-signal processor AP0101AT is by resistance R7 ground connection, and the FS pin of described ISP image-signal processor AP0101AT is by resistance R8 ground connection.

4. according to a kind of underground coal mine network video monitor terminal circuit according to claim 3, it is characterized in that: DO0 ~ DO11 pin of described imageing sensor AR0132AT is corresponding in turn to and connects with DI 0 ~ DI11 pin of described ISP image-signal processor AP0101AT, the EXTCLK pin of described imageing sensor AR0132AT connects with the ECO pin of described ISP image-signal processor AP0101AT, the RST pin of described imageing sensor AR0132AT connects with the RSTO pin of described ISP image-signal processor AP0101AT, and connected with the output of+1.8V power supply by resistance R31, the SCLK pin of described imageing sensor AR0132AT connects with the MSCLK pin of described ISP image-signal processor AP0101AT, the SDA pin of described imageing sensor AR0132AT connects with the MSDA pin of described ISP image-signal processor AP0101AT, the PCLK pin of described imageing sensor AR0132AT connects with the PCLKI pin of described ISP image-signal processor AP0101AT, the FV pin of described imageing sensor AR0132AT connects with the FVI pin of described ISP image-signal processor AP0101AT, the LV pin of described imageing sensor AR0132AT connects with the LVI pin of described ISP image-signal processor AP0101AT, the TRIGGER pin of described imageing sensor AR0132AT connects with the TO pin of described ISP image-signal processor AP0101AT, the SADDR pin of described imageing sensor AR0132AT is connected with the output of+1.8V power supply by resistance R32, the OE pin of described imageing sensor AR0132AT is by resistance R33 ground connection.

5. according to a kind of underground coal mine network video monitor terminal circuit according to claim 2, it is characterized in that: described RTC real time clock circuit (2) comprises real-time timepiece chip ISL1208 and crystal oscillator Y1, 1st pin of described real-time timepiece chip ISL1208 connects with one end of crystal oscillator Y1, 2nd pin of described real-time timepiece chip ISL1208 connects with the other end of crystal oscillator Y1, 3rd pin of described real-time timepiece chip ISL1208 connects with the output of+3.3V power supply, the 4th pin ground connection of described real-time timepiece chip ISL1208, 5th pin of described real-time timepiece chip ISL1208 connects with the 110th pin of described fpga chip EP3C5E144C8N, and connected with the output of+3.3V power supply by resistance R21, 6th pin of described real-time timepiece chip ISL1208 connects with the 111st pin of described fpga chip EP3C5E144C8N, and connected with the output of+3.3V power supply by resistance R20,7th pin of described real-time timepiece chip ISL1208 connects with the 24th pin of described fpga chip EP3C5E144C8N, and connected with the output of+3.3V power supply by resistance R19, the 8th pin of described real-time timepiece chip ISL1208 connects with the output of+3.3V power supply.

6. according to a kind of underground coal mine network video monitor terminal circuit according to claim 2, it is characterized in that: described FLASH flash memory circuit (3) comprises chip H27U1G8F2B, 7th pin of described chip H27U1G8F2B connects with the 127th pin of described fpga chip EP3C5E144C8N, and is connected with the output of+3.3V power supply by resistance R12, 8th pin of described chip H27U1G8F2B connects with the 128th pin of described fpga chip EP3C5E144C8N, 9th pin of described chip H27U1G8F2B connects with the 129th pin of described fpga chip EP3C5E144C8N, 12nd pin and the 37th pin of described chip H27U1G8F2B all connect with the output of+3.3V power supply, 13rd pin of described chip H27U1G8F2B and the equal ground connection of the 36th pin, 16th ~ 19 pins of described chip H27U1G8F2B are corresponding in turn to and connect with 132nd ~ 136 pins of described fpga chip EP3C5E144C8N, 29th ~ 32 pins of described chip H27U1G8F2B are corresponding in turn to and connect with 112nd ~ 115 pins of described fpga chip EP3C5E144C8N, 41st ~ 44 pins of described chip H27U1G8F2B are corresponding in turn to and connect with 119th ~ 124 pins of described fpga chip EP3C5E144C8N.

7. according to a kind of underground coal mine network video monitor terminal circuit according to claim 2, it is characterized in that: described DRAM memory circuitry (4) comprises chip K4S641632UC-70T, the 2nd of described chip K4S641632UC-70T, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51 and 53 pins are corresponding in turn to the with described fpga chip EP3C5E144C8N the 28th, 30, 31, 32, 33, 34, 38, 39, 54, 53, 52, 51, 50, 49, 46 and 44 pins connect, 19th pin of described chip K4S641632UC-70T connects with the 7th pin of described fpga chip EP3C5E144C8N, and connected with the output of+3.3V power supply by resistance R16, 16th pin of described chip K4S641632UC-70T connects with the 42nd pin of described fpga chip EP3C5E144C8N, and is connected with the output of+3.3V power supply by resistance R15, 17th pin of described chip K4S641632UC-70T connects with the 11st pin of described fpga chip EP3C5E144C8N, and is connected with the output of+3.3V power supply by resistance R14, 18th pin of described chip K4S641632UC-70T connects with the 10th pin of described fpga chip EP3C5E144C8N, and is connected with the output of+3.3V power supply by resistance R13, the 23rd of described chip K4S641632UC-70T, 24, 25, 26, 29, 30, 31, 32, 33, 34, 22 and 35 pins are corresponding in turn to the with described fpga chip EP3C5E144C8N the 1st, 144, 143, 68, 67, 66, 65, 64, 60, 59, 2 and 58 pins connect, 20th and 21 pins of described chip K4S641632UC-70T are corresponding in turn to and connect with the 4th and 3 pins of described fpga chip EP3C5E144C8N, 37th pin of described chip K4S641632UC-70T connects with the 55th pin of described fpga chip EP3C5E144C8N, the 43rd pin that 38th pin of described chip K4S641632UC-70T is corresponding in turn to described fpga chip EP3C5E144C8N connects, and by electric capacity C22 ground connection.

8. according to a kind of underground coal mine network video monitor terminal circuit according to claim 2, it is characterized in that: described configuring chip (5) is chip EPCS64,1st pin of described chip EPCS64 connects with the 8th pin of described fpga chip EP3C5E144C8N, 2nd pin of described chip EPCS64 is connected with the 13rd pin of described fpga chip EP3C5E144C8N by resistance R35,3rd, 7 and 8 pins of described chip EPCS64 all connect with the output of+3.3V power supply, and by electric capacity C27 ground connection, the 4th pin ground connection of described chip EPCS64; 5th pin of described chip EPCS64 connects with the 6th pin of described fpga chip EP3C5E144C8N, and the 6th pin of described chip EPCS64 is connected with the 12nd pin of described fpga chip EP3C5E144C8N by resistance R36.

9. according to a kind of underground coal mine network video monitor terminal circuit according to claim 2, it is characterized in that: described AVB ethernet module (6) comprises AVB Ethernet chip BCM89810, common mode inductance T1 and the four pin interface P2 for being connected unshielded twisted pair, 8th pin of described AVB Ethernet chip BCM89810 connects with the 98th pin of described fpga chip EP3C5E144C8N, 26th pin of described AVB Ethernet chip BCM89810 connects with the 72nd pin of described fpga chip EP3C5E144C8N, 32nd pin of described AVB Ethernet chip BCM89810 and the 31st pin are corresponding in turn to and connect with the 137th pin of described fpga chip EP3C5E144C8N and the 138th pin, 28th pin of described AVB Ethernet chip BCM89810 and the 27th pin are corresponding in turn to and connect with the 141st pin of described fpga chip EP3C5E144C8N and the 142nd pin, 33rd pin of described AVB Ethernet chip BCM89810 connects with the 104th pin of described fpga chip EP3C5E144C8N, 35th pin of described AVB Ethernet chip BCM89810 connects with the 101st pin of described fpga chip EP3C5E144C8N, 39th pin of described AVB Ethernet chip BCM89810 and the 38th pin are corresponding in turn to and connect with the 105th pin of described fpga chip EP3C5E144C8N and the 106th pin, 37th pin of described AVB Ethernet chip BCM89810 and the 36th pin are corresponding in turn to and connect with the 125th pin of described fpga chip EP3C5E144C8N and the 126th pin, 40th pin of described AVB Ethernet chip BCM89810 connects with the 71st pin of described fpga chip EP3C5E144C8N, 46th pin of described AVB Ethernet chip BCM89810 connects with the 103rd pin of described fpga chip EP3C5E144C8N, 47th pin of described AVB Ethernet chip BCM89810 connects with the 99th pin of described fpga chip EP3C5E144C8N, and connected with the output of+3.3V power supply by resistance R41,48th pin of described AVB Ethernet chip BCM89810 connects with the 100th pin of described fpga chip EP3C5E144C8N, 14th pin of described AVB Ethernet chip BCM89810 be connected to the resistance R45 and resistance R46 that connect between the 15th pin, the link ground connection of described resistance R45 and resistance R46, 14th pin of described AVB Ethernet chip BCM89810 is connected with first input pin of common mode inductance T1 by electric capacity C48, 15th pin of described AVB Ethernet chip BCM89810 is connected with second input pin of common mode inductance T1 by electric capacity C47, first output pin of described common mode inductance T1 connects with the 2nd pin of four pin interface P2, second output pin of described common mode inductance T1 connects with the 3rd pin of four pin interface P2, 1st pin of described four pin interface P2 connects with the output of+12V power supply, the 4th pin ground connection of described four pin interface P2.