CN204406964U - Gate driving circuit structure of display - Google Patents
Gate driving circuit structure of display Download PDFInfo
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- CN204406964U CN204406964U CN201420799379.2U CN201420799379U CN204406964U CN 204406964 U CN204406964 U CN 204406964U CN 201420799379 U CN201420799379 U CN 201420799379U CN 204406964 U CN204406964 U CN 204406964U
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- film transistor
- tft
- thin film
- conductive film
- connecting hole
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- 239000010409 thin film Substances 0.000 claims abstract description 102
- 239000010408 film Substances 0.000 claims description 69
- 239000002184 metal Substances 0.000 claims description 47
- 238000009413 insulation Methods 0.000 claims description 34
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 6
- 229910044991 metal oxide Inorganic materials 0.000 description 6
- 150000004706 metal oxides Chemical class 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The utility model discloses a gate drive circuit structure of display, the utility model discloses overlap the setting with thin film transistor and electric capacity among gate drive circuit's the signal generation circuit, and reduce the circuit area of signal generation circuit to reduce whole gate drive circuit's circuit area, and then reach the efficiency of the narrow frame of display.
Description
Technical field
The utility model relates to driving circuit structure field, more particularly, relates to a kind of gate drive circuit structure of display.
Background technology
In liquid crystal display (Liquid Crystal Display), each picture element has a thin film transistor (TFT) (TFT), its gate (Gate) is connected to horizontal direction sweep trace, drain (Drain) is connected to the data line of vertical direction, and source class (Source) is then connected to pixel electrode.If a certain bar scanning is in the horizontal direction online apply enough positive voltages, this online all TFT can be made to open, now this online pixel electrode can be connected with the data line of vertical direction, and by the display voltage of online data write picture element, control the penetrability of different liquid crystal and then reach the effect controlling color.
The driving circuit of current liquid crystal display has mainly been come by the external IC of panel, uses CMOS processing procedure.And GOA technology and Gate Driver on Array (multiple substrate row cutting technology), be directly gate drive circuit (Gate driver ICs) is produced on array (Array) substrate, replace a kind of technology of the driving chip made by external silicon.The application of this technology can directly be made in around panel, reduces production process, and reduces cost of products and volume.
But, along with panel resolution more and more higher when, cause the area of display device frame constantly to compress always.What now GOA driving circuit was relative must reduce its area, and general way reduces thin film transistor (TFT) and electric capacity, but the opering characteristic of electric apparatus so can be caused to change thereupon and then affect panel display characteristic, such as, the driving force of driving circuit likely can be caused not enough.
Therefore, the utility model, for the problems referred to above, provides a kind of gate drive circuit structure of display.
Utility model content
The utility model object, be to provide a kind of gate drive circuit structure of display, overlap by by the thin film transistor (TFT) in the signal generating circuit of gate drive circuit and electric capacity, and reduce the circuit area of signal generating circuit, to reduce the circuit area of overall gate drive circuit, and then reach effect of the narrow frame of display.
In order to reach above-mentioned censured each object and effect, the utility model discloses a kind of gate drive circuit structure of display, it comprises complex signal and produces circuit, described signal generating circuit is for generation of plural sweep signal, and export described sweep signal to display panel, described signal generating circuit comprises respectively: thin film transistor (TFT), in order to conducting or cut-off, to export described sweep signal; Insulation course, is positioned at the top of described thin film transistor (TFT), and described insulation course has the first connecting hole and the second connecting hole; First conductive film, is positioned at the top of described insulation course and described thin film transistor (TFT), and is electrically connected the first metal layer through described first connecting hole; And second conductive film, be positioned at the top of described first conductive film, described insulation course and described thin film transistor (TFT), and be electrically connected the second metal level through described second connecting hole; Wherein, described first conductive film and described second conductive film are overlapped in the top of described thin film transistor (TFT), and a distance and described first conductive film and described second conductive film are separated by, to form electric capacity.
This creation more discloses a kind of gate drive circuit structure of display, it comprises complex signal and produces circuit, described signal generating circuit is in order to produce plural sweep signal, and export those sweep signals to display panel, described signal generating circuit comprises respectively: the first film transistor, one end of described the first film transistor is electrically connected the first contact, and described first contact is positioned at the first metal layer; Second thin film transistor (TFT), one end of described second thin film transistor (TFT) is positioned at the second metal level, and described the first metal layer is positioned at the top of described second metal level; Insulation course, is positioned at the top of the second thin film transistor (TFT) and the 3rd thin film transistor (TFT) described in described the first film transistor AND gate, and described insulation course has the first connecting hole and the second connecting hole; First conductive film, is positioned at the top of described insulation course, described the first film transistor, described second thin film transistor (TFT) and described 3rd thin film transistor (TFT), and is electrically connected described first contact and described second metal level through described first connecting hole; And second conductive film, be positioned at the top of described first conductive film, described insulation course, described the first film transistor, described second thin film transistor (TFT) and described 3rd thin film transistor (TFT), and being electrically connected the second contact through described second connecting hole, described second contact is positioned at described the first metal layer; Wherein, described first conductive film and described second conductive film are overlapped in the top of described 3rd thin film transistor (TFT), and described first conductive film and described second conductive film separated by a distance, to form electric capacity.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the utility model is described in further detail, in accompanying drawing:
1st figure is the schematic diagram of the drive system of display of the present utility model;
2nd figure is the circuit diagram of the gate drive circuit of a preferred embodiment of the present utility model;
3rd figure is the circuit diagram of the signal generating circuit of a preferred embodiment of the present utility model;
4th figure is the schematic layout pattern of known signal generating circuit;
5th figure is the sectional view of known signal generating circuit;
6th figure is the schematic layout pattern of the signal generating circuit of a preferred embodiment of the present utility model;
7th figure is the sectional view of the signal generating circuit of a preferred embodiment of the present utility model;
8th figure is the sectional view of the signal generating circuit of another preferred embodiment of the present utility model.
Wherein, the label of each parts is as follows:
1 display
10 display panels
12 gate drive circuits
121-124,221-222 signal generating circuit
1210 pull-up circuits
1212 pull-down circuits
14 source electrode drive circuits
16 sequential control circuits
201,301,401 substrates
202,302 semiconductor layers
203,204,303,304 electrodes
205,305,405 insulation courses
206,207,306,307,406, conductive film
407
208,209,308,309,408, dielectric layer
409
410 first contacts
411 end points
412 second contacts
C1, C2 electric capacity
CLK frequency signal
H1, H3 first connecting hole
H2, H4 second connecting hole
M1, M2, M3, M4, M5 thin film transistor (TFT)
MT1, MT2 metal level
SC1-SC4 sweep signal
STV enabling signal
VSS reference voltage end
Embodiment
In order to there be understanding clearly to technical characteristic of the present utility model, object and effect, now contrast accompanying drawing and describe embodiment of the present utility model in detail.
Refer to the 1st figure, it is the schematic diagram of the drive system of display of the present utility model.As shown in the figure, display 1 comprises display panel 10, gate drive circuit 12, source electrode drive circuit 14 and sequential control circuit 16.Gate drive circuit 12 produces and transmits plural number (multiple, lower same) sweep signal to display panel 10, to drive display panel 10.Source electrode drive circuit 14 utilizes plural Ka agate voltage as multiple reference voltage, and selects those reference voltages to produce and to transmit complex data signals to display panel 10 according to plural number display data.Display panel 10 is show image according to those data-signals.Sequential control circuit 16 produces one scan control signal and a data controlling signal, and transmit scan control signal to gate drive circuit 12 and transmit data controlling signal to source electrode drive circuit 14, transmit those sweep signals and those data-signals sequential to display panel 10 with control grid driving circuit 12 and source electrode drive circuit 14.
Refer to the 2nd figure, it is the circuit diagram of the gate drive circuit of a preferred embodiment of the present utility model.As shown in the figure, gate drive circuit 12 comprises complex signal and produces circuit 121-124, those signal generating circuits 121-124 can be respectively shift register (Shift register), those signal generating circuits 121-124 receives frequency signal CLK and an enabling signal STV of the scan control signal of sequential control circuit 16 output, and according to frequency signal CLK and enabling signal STV, and sequentially produce and export plural sweep signal SC1-SC4.
But, due to gate drive circuit 12 those signal generating circuits 121-124 between connected mode have many kinds, and its connected mode is not also the technology emphasis of the utility model, therefore the utility model only introduces the connected mode of basic those signal generating circuits 121-124 in the 2nd figure, but and is not used to limit technology of the present utility model.
Refer to the 3rd figure, it is the circuit diagram of the signal generating circuit of a preferred embodiment of the present utility model.Because the circuit framework of those signal generating circuits 121-124 is all identical, therefore the utility model only explains with signal generating circuit 121.As shown in the figure, signal generating circuit 121 comprises plural thin film transistor (TFT) M1-M3, complex capacitance C1-C2, pull-up circuit 1210 and pull-down circuit 1212.The gate of thin film transistor (TFT) M1 couples pull-up circuit 1210, and the source electrode of thin film transistor (TFT) M1 couples pull-down circuit 1212, and the drain receiving frequency signals CLK of thin film transistor (TFT) M1, thin film transistor (TFT) M1 are in order to conducting or cut-off, to export sweep signal SC1.The gate of thin film transistor (TFT) M2 couples the gate of thin film transistor (TFT) M1, and the source electrode of thin film transistor (TFT) M2 couples reference voltage end Vss.The gate of thin film transistor (TFT) M3 couples the drain of thin film transistor (TFT) M2, and the drain of thin film transistor (TFT) M3 couples the gate of thin film transistor (TFT) M1, and the source electrode of thin film transistor (TFT) M3 couples reference voltage end Vss.Between the gate that electric capacity C1 is coupled to thin film transistor (TFT) M1 and source electrode.The end receiving frequency signals CLK of electric capacity C2, and its other end is coupled to the drain of thin film transistor (TFT) M2 and the gate of thin film transistor (TFT) M3.
Wherein, the thin film transistor (TFT) M1-M3 of the present embodiment is N-type metal-oxide half field effect transistor (N-MOSFET), but the utility model is not as limit, thin film transistor (TFT) M1-M3 is also replaceable is P type metal-oxide half field effect transistor (P-MOSFET).
See also the 4th, 5 figure, the 4th figure be the schematic layout pattern of known signal generating circuit, the 5th figure is the sectional view (sectional view of profile line A-A ') of known signal generating circuit.As shown in Figure 4, the layout type of known signal generating circuit 221-222 is arranged on by thin film transistor (TFT) M1 by electric capacity C1, and electric capacity C2 is arranged on by thin film transistor (TFT) M2-M5, wherein thin film transistor (TFT) M4 and M5 is the transistor of pull-up circuit 1210 and pull-down circuit 1212 inside.
5th figure shows the sectional view of the 4th figure section line A-A ', as shown in the figure, substrate 201, semiconductor layer 202, electrode 203 are positioned at metal level MT1 with electrode 204, and semiconductor layer 202, electrode 203, electrode 204 form thin film transistor (TFT) M1 with metal level MT2, electrode 204 extends a part of top electrode as electric capacity C1, and metal level MT2 is as the bottom electrode of electric capacity C1, electrode 204 extends partly separated by a distance with metal level MT2 and forms electric capacity C1.Insulation course 205 is positioned at the side of metal level MT1, is namely positioned at the side of thin film transistor (TFT) M1.One conductive film 206 and conductive film 207 are all positioned at the side of insulation course 205.In addition, between insulation course 205 and the second metal level MT2, more comprise dielectric layer 208, and more comprise dielectric layer 209 on insulation course 205.Wherein, electrode 203 and electrode 204 can according to the type of thin film transistor (TFT) M1 (NMOS or PMOS) as the drain of thin film transistor (TFT) M1 or source electrodes.
From the above, electric capacity C1 is arranged on by thin film transistor (TFT) M1 by known signal generating circuit 221-222, and is arranged on by thin film transistor (TFT) M2 and M3 by electric capacity C2, thus can occupy too much circuit area.
Refer to the 6th figure, it is the schematic layout pattern of the signal generating circuit of a preferred embodiment of the present utility model.As shown in the figure, the layout type of signal generating circuit of the present utility model is that electric capacity C1 is overlapping with thin film transistor (TFT) M1, and electric capacity C2 is overlapping with thin film transistor (TFT) M2 and M4.So, the circuit area of signal generating circuit can be reduced.
See also the 7th figure, it is the sectional view (i.e. the sectional view of the 6th figure profile line B-B ') of the signal generating circuit of preferred embodiment of the present utility model.As shown in the figure, substrate 301, semiconductor layer 302, electrode 303 are positioned at metal level MT1 with electrode 304, the gate of thin film transistor (TFT) M1 is then positioned at metal level MT2, semiconductor layer 302, electrode 303, electrode 304 form thin film transistor (TFT) M1 with metal level MT2, and metal level MT2 is positioned at the side of metal level MT1.Insulation course 305 is positioned at the top of metal level MT1, is namely positioned on thin film transistor (TFT) M1, and insulation course 305 has the first connecting hole H1 and the second connecting hole H2.Conductive film 306 is positioned at the side of insulation course 305 and thin film transistor (TFT) M1, and is electrically connected metal level MT1 through the first connecting hole H1, is namely electrically connected the electrode 304 of thin film transistor (TFT) M1.Conductive film 307, is positioned at the top of conductive film 306, insulation course 305 and thin film transistor (TFT) M1, and is electrically connected metal level MT2 through the second connecting hole H2, be namely electrically connected the gate of thin film transistor (TFT) M1.Conductive film 306 and 307 is overlapped in the side of thin film transistor (TFT) M1, and conductive film 306 and 307 is separated by a distance, to form electric capacity C1.In addition, more comprise dielectric layer 308, and on insulation course 305, more comprise dielectric layer 309 between insulation course 305 and metal level MT2, dielectric layer 309 is between conductive film 306 and 307.
Wherein, the thin film transistor (TFT) M1 of the present embodiment can be N-type metal-oxide half field effect transistor (N-MOSFET) or P type metal-oxide half field effect transistor (P-MOSFET).If thin film transistor (TFT) M1 is N-type metal-oxide half field effect transistor, then electrode 303 is the drain of thin film transistor (TFT) M1, and electrode 304 is the source electrode of thin film transistor (TFT) M1.Otherwise if thin film transistor (TFT) M1 is P type metal-oxide half field effect transistor, then electrode 303 is the source electrode of thin film transistor (TFT) M1, and electrode 304 is the drain of thin film transistor (TFT) M1.
See also the 8th figure, it is the sectional view (i.e. the sectional view of the 6th figure profile line C-C ') of the signal generating circuit of another preferred embodiment of the present utility model.As shown in the figure, one end that signal generating circuit 122 is formed on substrate 401, thin film transistor (TFT) M2 is electrically connected the first contact 410, first contact 410 and is positioned at metal level MT1.The end points 411 of thin film transistor (TFT) M3 is positioned at metal level MT2, and in the present embodiment, the end points 411 of thin film transistor (TFT) M3 is its gate.Insulation course 405 is positioned at the top of thin film transistor (TFT) M2-M4, and insulation course 405 has the first connecting hole H3 and the second connecting hole H4.Conductive film 406 is positioned at the top of insulation course 405, thin film transistor (TFT) M2-M4, and is electrically connected the end points 411 of thin film transistor (TFT) M3 in the first contact 410 and metal level MT2 through the first connecting hole H3.Conductive film 407 is positioned at the top of conductive film 406, insulation course 405, thin film transistor (TFT) M2-M4, and is electrically connected one second contact 412, the second contact 412 through the second connecting hole H4 and is positioned at metal level MT1.Conductive film 406 and conductive film 407 are overlapped in the top of thin film transistor (TFT) M2, M4, and the first conductive film 406 and the second conductive film 407 separated by a distance, to form electric capacity C2.In addition, more comprise dielectric layer 408, and more comprise dielectric layer 409 in the top of insulation course 405 between insulation course 405 and metal level MT2, dielectric layer 409 is between conductive film 406 and 407.
Wherein, the drain of the thin film transistor (TFT) M1 of the present embodiment or source electrode (being drain or source electrode depending on transistor types) are positioned at the second contact 412, namely conductive film 407 is electrically connected drain or the source electrode of thin film transistor (TFT) M1 through the second connecting hole H4, and conductive film 407 through this path receiving frequency signals CLK.
In sum, the gate drive circuit structure of display of the present utility model, overlap by by the thin film transistor (TFT) in the signal generating circuit of gate drive circuit and electric capacity, and reduce the circuit area of signal generating circuit, to reduce the circuit area of overall gate drive circuit, and then reach effect of the narrow frame of display.
By reference to the accompanying drawings embodiment of the present utility model is described above; but the utility model is not limited to above-mentioned embodiment; above-mentioned embodiment is only schematic; instead of it is restrictive; those of ordinary skill in the art is under enlightenment of the present utility model; do not departing under the ambit that the utility model aim and claim protect, also can make a lot of form, these all belong within protection of the present utility model.
Claims (10)
1. a gate drive circuit structure for display, is characterized in that, it comprises complex signal and produces circuit, and described signal generating circuit for generation of plural sweep signal, and exports described sweep signal to display panel, and described signal generating circuit comprises respectively:
Thin film transistor (TFT), in order to conducting or cut-off, to export described sweep signal;
Insulation course, is positioned at the top of described thin film transistor (TFT), and described insulation course has the first connecting hole and the second connecting hole;
First conductive film, is positioned at the top of described insulation course and described thin film transistor (TFT), and is electrically connected the first metal layer through described first connecting hole;
And second conductive film, be positioned at the top of described first conductive film, described insulation course and described thin film transistor (TFT), and be electrically connected the second metal level through described second connecting hole;
Wherein, described first conductive film and described second conductive film are overlapped in the top of described thin film transistor (TFT), and described first conductive film and described second conductive film separated by a distance, to form electric capacity.
2. gate drive circuit structure according to claim 1, is characterized in that, wherein said the first metal layer is between described second metal level and described insulation course.
3. gate drive circuit structure according to claim 1, it is characterized in that, the source electrode of wherein said thin film transistor (TFT) is positioned at described the first metal layer, and the gate of described thin film transistor (TFT) is positioned at described second metal level, described first conductive film is electrically connected the source electrode of described thin film transistor (TFT) via described first connecting hole, described second conductive film is electrically connected the described gate of described thin film transistor (TFT) via described second connecting hole.
4. gate drive circuit structure according to claim 1, it is characterized in that, the drain of wherein said thin film transistor (TFT) is positioned at described the first metal layer, and the gate of described thin film transistor (TFT) is positioned at described second metal level, described first conductive film is electrically connected the drain of described thin film transistor (TFT) via described first connecting hole, described second conductive film is electrically connected the described gate of described thin film transistor (TFT) via described second connecting hole.
5. gate drive circuit structure according to claim 1, it is characterized in that, it also comprises dielectric layer, and described dielectric layer is between described first conductive film and described second conductive film.
6. a gate drive circuit structure for display, is characterized in that, it comprises complex signal and produces circuit, and described signal generating circuit in order to produce plural sweep signal, and exports those sweep signals to display panel, and described signal generating circuit comprises respectively:
The first film transistor, one end of described the first film transistor is electrically connected the first contact, and described first contact is positioned at the first metal layer;
Second thin film transistor (TFT), one end of described second thin film transistor (TFT) is positioned at the second metal level, and described the first metal layer is positioned at the top of described second metal level;
Insulation course, is positioned at the top of the second thin film transistor (TFT) and the 3rd thin film transistor (TFT) described in described the first film transistor AND gate, and described insulation course has the first connecting hole and the second connecting hole;
First conductive film, is positioned at the top of described insulation course, described the first film transistor, described second thin film transistor (TFT) and described 3rd thin film transistor (TFT), and is electrically connected described first contact and described second metal level through described first connecting hole; And
Second conductive film, be positioned at the top of described first conductive film, described insulation course, described the first film transistor, described second thin film transistor (TFT) and described 3rd thin film transistor (TFT), and being electrically connected the second contact through described second connecting hole, described second contact is positioned at described the first metal layer;
Wherein, described first conductive film and described second conductive film are overlapped in the top of described 3rd thin film transistor (TFT), and described first conductive film and described second conductive film separated by a distance, to form electric capacity.
7. gate drive circuit structure according to claim 6, it is characterized in that, the gate of wherein said second thin film transistor (TFT) is positioned at described second metal level, and described first conductive film is electrically connected the described gate of described first contact and described second thin film transistor (TFT) via described first connecting hole.
8. gate drive circuit structure according to claim 6, it is characterized in that, wherein the drain of the 3rd thin film transistor (TFT) is positioned at described second contact of described the first metal layer, and described second conductive film is electrically connected the described drain of described 3rd thin film transistor (TFT) via described second connecting hole; Or wherein the source electrode of the 3rd thin film transistor (TFT) is positioned at described second contact of described the first metal layer, described second conductive film is electrically connected the described source electrode of described 3rd thin film transistor (TFT) via described second connecting hole.
9. gate drive circuit structure according to claim 6, is characterized in that, wherein said second conductive film is electrically connected described the first metal layer, with receiving frequency signals via described second connecting hole.
10. gate drive circuit structure according to claim 6, is characterized in that, it more comprises a dielectric layer, and described dielectric layer is between described first conductive film and described second conductive film.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103220509U TWM498327U (en) | 2014-11-19 | 2014-11-19 | Gate driving circuit structure of displays |
| TW103220509 | 2014-11-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204406964U true CN204406964U (en) | 2015-06-17 |
Family
ID=53430804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420799379.2U Active CN204406964U (en) | 2014-11-19 | 2014-12-16 | Gate driving circuit structure of display |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN204406964U (en) |
| TW (1) | TWM498327U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107527599A (en) * | 2017-08-16 | 2017-12-29 | 深圳市华星光电半导体显示技术有限公司 | Scan drive circuit, array base palte and display panel |
| TWI717983B (en) * | 2020-01-22 | 2021-02-01 | 友達光電股份有限公司 | Display panel and shift register thereof suitable for narrow border application |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI642998B (en) * | 2015-05-06 | 2018-12-01 | 凌巨科技股份有限公司 | A slim border display |
-
2014
- 2014-11-19 TW TW103220509U patent/TWM498327U/en unknown
- 2014-12-16 CN CN201420799379.2U patent/CN204406964U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107527599A (en) * | 2017-08-16 | 2017-12-29 | 深圳市华星光电半导体显示技术有限公司 | Scan drive circuit, array base palte and display panel |
| CN107527599B (en) * | 2017-08-16 | 2020-06-05 | 深圳市华星光电半导体显示技术有限公司 | Scanning driving circuit, array substrate and display panel |
| US10902809B2 (en) | 2017-08-16 | 2021-01-26 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Scan driver circuit, array substrate and display panel |
| TWI717983B (en) * | 2020-01-22 | 2021-02-01 | 友達光電股份有限公司 | Display panel and shift register thereof suitable for narrow border application |
Also Published As
| Publication number | Publication date |
|---|---|
| TWM498327U (en) | 2015-04-01 |
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