CN104460144A - Thin film transistor substrate, method for driving thin film transistor substrate and display device - Google Patents
Thin film transistor substrate, method for driving thin film transistor substrate and display device Download PDFInfo
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- CN104460144A CN104460144A CN201310436044.4A CN201310436044A CN104460144A CN 104460144 A CN104460144 A CN 104460144A CN 201310436044 A CN201310436044 A CN 201310436044A CN 104460144 A CN104460144 A CN 104460144A
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- film transistor
- thin film
- data line
- source electrode
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- 239000010409 thin film Substances 0.000 title claims abstract description 86
- 238000000034 method Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 title abstract description 11
- 238000009413 insulation Methods 0.000 claims description 37
- 239000010408 film Substances 0.000 claims description 24
- 238000010586 diagram Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Optics & Photonics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Provided is a thin film transistor substrate. The thin film transistor substrate comprises scanning lines, first data lines and second data lines. The first data lines are insulated from the second data lines, and positions of the first data lines and positions of the second data lines are at least partially overlapped in the direction perpendicular to the thin film transistor substrate. Any two adjacent scanning lines and any two adjacent first data lines intersect and define a pixel unit. One part of the pixel units located on the same vertical column comprise first thin film transistors electrically connected with the corresponding first data lines, and the other part of the pixel units located on the same vertical column comprise second thin film transistors electrically connected with the corresponding second data lines. The thin film transistor substrate can drive two rows of thin film transistors corresponding to two scanning lines within one time sequence and is high in scanning speed; compared with a traditional thin film transistor substrate, the thin film transistor substrate has obvious advantages in the scanning speed aspect when especially applied to a high-resolution display device.
Description
Technical field
The present invention relates to a kind of thin film transistor base plate, a kind ofly drive the driving method of this thin film transistor base plate and a kind of display device.
Background technology
Traditional thin film transistor base plate is provided with usually sweep trace and the data line of interlaced arrangement, and described sweep trace and data line intersection are provided with the on-off element of thin film transistor (TFT) as transmitting display signal therefor.When being applied to the display panel of high-res, the duration of charging of each thin film transistor (TFT) can be compressed, and the duration of charging can affect display effect not, and display effect may be caused not good.
Summary of the invention
Given this, be necessary to provide a kind of thin film transistor base plate.This thin film transistor base plate comprises sweep trace, the first data line and the second data line.Described first data line and the second data line mutually insulated, and on the direction perpendicular to described thin film transistor base plate, described first data line is overlapping at least partly with the position of described second data line.Any two adjacent sweep traces and any two adjacent the first data lines are staggered defines a pixel cell.The one part of pixel unit being positioned at same perpendicular row comprises the first film transistor be electrically connected with described first data line, and another part pixel cell being positioned at these perpendicular row comprises the second thin film transistor (TFT) be electrically connected with described second data line.
There is a need to provide a kind of display device.This display device comprises above-mentioned thin film transistor base plate.
There is a need to provide a kind of driving method driving above-mentioned thin film transistor (TFT).The method comprises: in a sequential, simultaneously to described first data line and the second data line transfer data, and the sweep trace that unlatching one is corresponding with described the first film transistor simultaneously and a sweep trace corresponding with described second thin film transistor (TFT).
Compared to prior art, the time that thin film transistor (TFT) charges can double by the present invention, and the duration of charging is longer, and especially when being applied to the display device of high-res, compared to traditional thin film transistor base plate, display effect is more stable.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the display device that the specific embodiment of the invention provides.
Fig. 2 is the electrical block diagram of the thin film transistor base plate in Fig. 1.
Fig. 3 is the enlarged drawing of a-quadrant in Fig. 2.
Fig. 4 is the enlarged drawing in B region in Fig. 2.
Fig. 5 is the diagrammatic cross-section of a-quadrant in Fig. 3.
Fig. 6 is the diagrammatic cross-section in B region in Fig. 4.
The schematic diagram of scan mode when Fig. 7 is the work of this thin film transistor base plate.
Main element symbol description
| Display device | 100 |
| Thin film transistor base plate | 1 |
| Subtend substrate | 2 |
| Liquid crystal layer | 3 |
| Sweep trace | GL、Gate1、Gate2、Gate3 |
| First data line | S1、S3、S5、S7、S9 |
| Second data line | S2、S4、S6、S8、S10 |
| Pixel cell | P |
| The first film transistor | 110 |
| First grid | 111 |
| First source electrode | 112 |
| First drain | 113 |
| First passage | 114 |
| First pixel electrode | 120 |
| Second thin film transistor (TFT) | 210 |
| Second grid | 211 |
| Second source electrode | 212 |
| Second drain | 213 |
| Second channel | 214 |
| Second pixel electrode | 220 |
| Transparency carrier | 300 |
| First insulation course | 400 |
| Second insulation course | 500 |
| Connecting portion | 600 |
| First through hole | 510 |
| Second through hole | 520 |
| Third through-hole | 530 |
| Sequential | t1、t2 |
Following embodiment will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Embodiment
As shown in Figure 1, the liquid crystal layer 3 that the display device 100 that the specific embodiment of the invention provides comprises thin film transistor base plate 1, subtend substrate 2 and is sandwiched between described thin film transistor base plate 1 and subtend substrate 2.
As shown in Figure 2, described thin film transistor base plate 1 comprises sweep trace GL(Gate1, Gate2, Gate3 ...), first data line S1(S3, S5, S7, S9 ...) and second data line S2(S4, S6, S8, S10 ...).Described sweep trace GL is used for providing sweep signal.Described first data line S1 and the second data line S2 is used for providing data-signal.Described first data line S1 and described sweep trace GL mutually insulated and be crisscross arranged.Described second data line S2 and described sweep trace GL mutually insulated and be crisscross arranged.Described first data line S1 and described second data line S2 mutually insulated.On the direction perpendicular to described thin film transistor base plate 1, described first data line S1 is overlapping at least partly with the position of described second data line S2.Be understandable that, although described in the drawings the first data line S1 and the second data line S2 on the direction perpendicular to described thin film transistor base plate 1 be adjacent and and non-overlapped, but this is only and makes reader understand the present invention more easily, described first data line S1 and the position of described second data line S2 should be overlapping at least partly.
Any two adjacent sweep trace GL and any two adjacent staggered institutes of the first data line S1 define a pixel cell P.Each pixel cell P comprises the first film transistor 110 or the second thin film transistor (TFT) 210.Wherein, described the first film transistor 110 is electrically connected with described first data line S1, and described second thin film transistor (TFT) 210 is electrically connected with described second data line S2.Particularly, the one part of pixel unit P being positioned at same perpendicular row comprises the first film transistor 110 be electrically connected with described first data line S1, and another part pixel cell P being positioned at these perpendicular row comprises the second thin film transistor (TFT) 210 be electrically connected with described second data line S2.In each pixel cell P, the quantity sum of described the first film transistor 110 and the second thin film transistor (TFT) 210 is one.That is, the second thin film transistor (TFT) 210 can not be had again by existing the first film transistor 110 in each pixel cell P.Described thin film transistor base plate 1 also comprises corresponding with described the first film transistor 110 and covers first pixel electrode 120 of corresponding pixel cell P and second pixel electrode 220 that also cover corresponding pixel cell P corresponding to described second thin film transistor (TFT) 210.In the present embodiment, on the direction along described first data line S1, described the first film transistor 110 is disposed alternately in each pixel cell P with described second thin film transistor (TFT) 210.Preferably, the quantity of described sweep trace GL is even number, is arranged in the set of whole pixel cell P of same perpendicular row, and the quantity summation of described the first film transistor 110 is equal with the quantity summation of the second thin film transistor (TFT) 210.The pixel cell P that described the first film transistor 110 is corresponding with the second thin film transistor (TFT) 210 is complete and independently pixel cell P, can be controlled respectively by described first data line S1 and the second data line S2.
As shown in Figure 3, described the first film transistor 110 comprises first grid 111, first source electrode 112, first drain 113 and first passage 114.Described first grid 111 is electrically connected with described sweep trace GL.Described first source electrode 112 is electrically connected with described first data line S1, and with described second data line S2 mutually insulated.Described first pixel electrode 120 is electrically connected with described the first film transistor 110 by described first drain 113.The two ends of described first passage 114 are electrically connected with described first source electrode 112 and the first drain 113 respectively.When described sweep trace GL applies voltage, described first passage 114 by described first source electrode 112 and the first drain 113 conducting, and then described first data line S1 by described first source electrode 112, first passage 114, first drain 113 with described first pixel electrode 120 conducting to realize being electrically connected.
As shown in Figure 4, described second thin film transistor (TFT) 210 comprises second grid 211, second source electrode 212, second drain 213 and second channel 214.Described second grid 211 is electrically connected with described sweep trace GL.Described second source electrode 212 is electrically connected with described second data line S2, and with described first data line S1 mutually insulated.Described second pixel electrode 220 is electrically connected with described second thin film transistor (TFT) 210 by described second drain 213.The two ends of described second channel 214 are electrically connected with described second source electrode 212 and the second drain 213 respectively.When described sweep trace GL applies voltage, described second channel 214 by described second source electrode 212 and the second drain 213 conducting, and then described second data line S2 by described second source electrode 212, second channel 214, second drain 213 with described second pixel electrode 220 conducting to realize being electrically connected.
As shown in figs. 5 and 6, described thin film transistor base plate 1 also comprises transparency carrier 300, first insulation course 400, second insulation course 500 and connecting portion 600.Described sweep trace GL(is not shown), first grid 111 and second grid 211 be formed on described transparency carrier 300.Described first insulation course 400 is formed on described transparency carrier 300, and covers described sweep trace GL, first grid 111 and second grid 211.Described first passage 114, second channel 214 and the second data line S2 are formed on described first insulation course 400, and described first passage 114 is just to described first grid 111, and described second channel 214 is just to described second grid 211.Described first source electrode 112 and the first drain 113 are formed in described first insulation course 400 with on described first passage 114, and are spaced to expose described first passage 114.Described first source electrode 112 is spaced to insulate with described second data line S2.Described second source electrode 212 and the second drain 213 are formed in described first insulation course 400 with on described second channel 214, and are spaced to expose described second channel 214.Described second source electrode 212 extends to the side away from described second channel 214 and is electrically connected with described second data line S2.Described second insulation course 500 is formed on described first insulation course 400, and covers described second data line S2, the first source electrode 112, second source electrode 212, first drain 113, second drain 213, first passage 114 and second channel 214.
Described second insulation course 500 offers the first through hole 510, second through hole 520 and third through-hole 530.Described first through hole 510 just runs through described second insulation course 500 until described first drain 113 to described first drain 113.Described second through hole 520 just runs through described second insulation course 500 until described second drain 213 to described second drain 213.Described third through-hole 530 just runs through described second insulation course 500 until described first source electrode 112 to described first source electrode 112.Described first pixel electrode 120 is formed on described second insulation course 500, and is electrically connected with described first drain 113 by described first through hole 510.Described second pixel electrode 220 is formed on described second insulation course 500, and is electrically connected with described second drain 213 by described second through hole 520.Described first data line S1 and connecting portion 600 to be jointly formed on described second insulation course 500 and to be mutually electrically connected, wherein, the corresponding described second data line S2 of described first data line S1 is arranged, and the corresponding described third through-hole 530 of described connecting portion 600 and the first source electrode 112 are arranged.Described connecting portion 600 is electrically connected with described first source electrode 112 by described third through-hole 530, and then described first data line S1 achieves electric connection by described connecting portion 600 with described first source electrode 112.Simultaneously.Described second source electrode 212 is by described second insulation course 500 and described first data line S1 mutually insulated.
In the present embodiment, described first insulation course 400 is gate insulators.Described second insulation course 500 is passivation layers.The material of described first pixel electrode 120 and the second pixel electrode 220 is tin indium oxide (Indium tin oxide, ITO).The material of described first data line S1, the second data line S2 and connecting portion 600 is metals, and described first data line S1 and described connecting portion 600 are by being formed with gold-tinted etch process.
As shown in Figure 7, when described thin film transistor base plate 1 works, can in a sequential, transmit data to described first data line S1 and the second data line S2 simultaneously, and open corresponding with a described the first film transistor sweep trace GL and sweep trace GL corresponding with described second thin film transistor (TFT) simultaneously, in same sequential, walk crosswise thin film transistor (TFT) to two with this simultaneously charge.Such as in the present embodiment, sweep trace Gate1 and Gate2 can be opened at the first sequential t1 simultaneously, and transmit data to described first data line S1 and the second data line S2 simultaneously, charge at the two row thin film transistor (TFT)s that this sequential t1 is simultaneously corresponding to sweep trace Gate1 and Gate2 with this.And at the second sequential t2, open sweep trace Gate3 and Gate4 to charge to ensuing two row thin film transistor (TFT)s simultaneously simultaneously, the like.The thin film transistor base plate 1 that the specific embodiment of the invention provides can charge to two thin film transistor (TFT)s in a sequential simultaneously, thus is doubled the time that single thin film transistor (TFT) charges, and the duration of charging is longer, and display effect is more stable.Especially, when being applied to the display device of high-res, compared to traditional thin film transistor base plate, there is in the duration of charging obvious advantage.And due to described first data line S1 be overlapping with the position of the second data line S2 on the direction perpendicular to described thin film transistor base plate 1, can't have an impact to the aperture opening ratio of this thin film transistor base plate 1.
Above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not depart from the spirit and scope of technical solution of the present invention.
Claims (13)
1. a thin film transistor base plate, comprise sweep trace, first data line and the second data line, described first data line and the second data line mutually insulated, and on the direction perpendicular to described thin film transistor base plate, described first data line is overlapping at least partly with the position of described second data line, any two adjacent sweep traces and any two adjacent the first data lines are staggered defines a pixel cell, the one part of pixel unit being positioned at same perpendicular row comprises the first film transistor be electrically connected with described first data line, another part pixel cell being positioned at these perpendicular row comprises the second thin film transistor (TFT) be electrically connected with described second data line.
2. thin film transistor base plate as claimed in claim 1, it is characterized in that, in each pixel cell, described in described the first film transistor AND gate, the quantity sum of the second thin film transistor (TFT) is one.
3. thin film transistor base plate as claimed in claim 1, it is characterized in that, be arranged in the set of whole pixel cells of same perpendicular row, the quantity summation of described the first film transistor is equal with the quantity summation of described second thin film transistor (TFT).
4. thin film transistor base plate as claimed in claim 1, it is characterized in that, on the direction along described first data line, described in described the first film transistor AND gate, the second thin film transistor (TFT) is disposed alternately in each pixel cell.
5. thin film transistor base plate as claimed in claim 1, it is characterized in that, described the first film transistor comprises first grid, first source electrode, first drain and first passage, described first grid is electrically connected with described sweep trace, described first source electrode is electrically connected with described first data line, the two ends of described first passage are electrically connected with described first source electrode and the first drain respectively, described second thin film transistor (TFT) comprises second grid, second source electrode, second drain and second channel, described second grid is electrically connected with described sweep trace, described second source electrode is electrically connected with described second data line, the two ends of described second channel are electrically connected with described second source electrode and the second drain respectively.
6. thin film transistor base plate as claimed in claim 1, it is characterized in that, the pixel cell that described the first film transistor AND gate second thin film transistor (TFT) is corresponding is complete and independently pixel cell, and the pixel cell that described the first film transistor AND gate second thin film transistor (TFT) is corresponding can be controlled respectively by described first data line and the second data line.
7. thin film transistor base plate as claimed in claim 5, is characterized in that, described second source electrode and described first data line mutually insulated, described first source electrode and described second data line mutually insulated.
8. thin film transistor base plate as claimed in claim 5, it is characterized in that, described thin film transistor base plate also comprises transparency carrier, first insulation course and the second insulation course, described sweep trace, first grid and second grid are formed on described transparency carrier, described first insulation course covers described transparency carrier, sweep trace, first grid and second grid, described first passage, second channel and the second data line are formed on described first insulation course, and described first passage is just to described first grid, described second channel is just to described second grid, described first source electrode and the first drain are formed on described insulation course and described first passage, and be spaced to expose described first passage, described second source electrode and the second drain are formed on described insulation course and described second channel, and be spaced to expose described second channel, described second source electrode extends to the side away from described second channel and is electrically connected with described second data line, described first source electrode and described second data line spaced to insulate, described second insulation course to be formed on described first insulation course and to cover described second data line, first source electrode, second source electrode, first passage, second channel, first drain and the second drain.
9. thin film transistor base plate as claimed in claim 8, it is characterized in that, described thin film transistor base plate also comprises corresponding with described the first film transistor and covers the first pixel electrode of corresponding pixel cell and second pixel electrode that also cover corresponding pixel cell corresponding to described second thin film transistor (TFT), described second insulation course is just offering the position of described first drain and is running through described second insulation course until the first through hole of described first drain, described second insulation course is just offering the position of described second drain and is running through affiliated second insulation course until the second through hole of described second drain, described first pixel electrode to be formed on described second insulation course and to be electrically connected with described first drain by described first through hole, described second pixel electrode to be formed on described second insulation course and to be electrically connected with described second drain by described second through hole.
10. thin film transistor base plate as claimed in claim 8, it is characterized in that, described second insulation course is just offering the position of described first source electrode and just described second insulation course is being run through until the third through-hole of described first source electrode to described first source electrode, described thin film transistor base plate also comprises connecting portion, described first data line and described connecting portion to be jointly formed on described second insulation course and to be mutually electrically connected, corresponding described second data line of described first data line is arranged, the corresponding described third through-hole of described connecting portion and the first source electrode are arranged, described connecting portion is electrically connected by described third through-hole and described first source electrode, described first data line is electrically connected by described connecting portion and described first source electrode.
11. thin film transistor base plates as claimed in claim 10, is characterized in that, described first data line and described connecting portion are by being formed with gold-tinted etch process.
12. 1 kinds of display device, this display device comprises the thin film transistor base plate as described in any one in claim 1 to 11.
13. 1 kinds of driving methods driving the thin film transistor base plate in described claim 1 to 11 described in any one, comprising:
In a sequential, simultaneously to described first data line and the second data line transfer data, and the sweep trace that unlatching one is corresponding with described the first film transistor simultaneously and a sweep trace corresponding with described second thin film transistor (TFT).
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| CN201310436044.4A CN104460144A (en) | 2013-09-24 | 2013-09-24 | Thin film transistor substrate, method for driving thin film transistor substrate and display device |
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| CN201310436044.4A CN104460144A (en) | 2013-09-24 | 2013-09-24 | Thin film transistor substrate, method for driving thin film transistor substrate and display device |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016187911A1 (en) * | 2015-05-26 | 2016-12-01 | 武汉华星光电技术有限公司 | Liquid crystal display panel, display device and drive method therefor |
| CN106773407A (en) * | 2016-12-29 | 2017-05-31 | 深圳市华星光电技术有限公司 | Display panel and preparation method thereof |
| WO2017166392A1 (en) * | 2016-03-29 | 2017-10-05 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, display panel and display device |
| WO2019127886A1 (en) * | 2017-12-29 | 2019-07-04 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| US10672803B2 (en) | 2017-12-29 | 2020-06-02 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel and display device |
| CN113138501A (en) * | 2020-01-19 | 2021-07-20 | 松下液晶显示器株式会社 | Liquid crystal display panel |
| CN113219734A (en) * | 2020-01-21 | 2021-08-06 | 松下液晶显示器株式会社 | Liquid crystal display panel |
| CN113488487A (en) * | 2021-06-30 | 2021-10-08 | 昆山龙腾光电股份有限公司 | Thin film transistor array substrate and display device |
| WO2022193440A1 (en) * | 2021-03-16 | 2022-09-22 | Tcl华星光电技术有限公司 | Display panel and display apparatus |
| US11947229B2 (en) | 2021-03-16 | 2024-04-02 | Tcl China Star Optoelectronics Technology Co., Ltd. | Display panel and display device |
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| CN101303840A (en) * | 2008-06-13 | 2008-11-12 | 上海广电光电子有限公司 | Liquid crystal display device and driving method thereof |
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| WO2017166392A1 (en) * | 2016-03-29 | 2017-10-05 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, display panel and display device |
| US10216057B2 (en) | 2016-03-29 | 2019-02-26 | Boe Technology Group Co., Ltd. | Array substrate and manufacturing method thereof, display panel and display device |
| CN106773407A (en) * | 2016-12-29 | 2017-05-31 | 深圳市华星光电技术有限公司 | Display panel and preparation method thereof |
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| US10672803B2 (en) | 2017-12-29 | 2020-06-02 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel and display device |
| CN113138501A (en) * | 2020-01-19 | 2021-07-20 | 松下液晶显示器株式会社 | Liquid crystal display panel |
| CN113219734A (en) * | 2020-01-21 | 2021-08-06 | 松下液晶显示器株式会社 | Liquid crystal display panel |
| CN113219734B (en) * | 2020-01-21 | 2023-09-05 | 松下电器（美国）知识产权公司 | Liquid crystal display panel having a light shielding layer |
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