TWI642998B - A slim border display - Google Patents

Abstract

The present invention is a narrow-frame display, which includes a gate drive circuit. The gate drive circuit includes a substrate, a first transparent layer, a first metal layer, a first insulating layer, a second metal layer, a first Two insulating layers and a second transparent layer. The first transparent layer is a transparent metal layer and formed on the substrate. The first metal layer is disposed on or under the first transparent layer. The first insulating layer is formed on the first transparent layer and the first metal layer. The two transparent layers are transparent metal layers and formed on the first transparent layer, the second metal layer is disposed on or under the second transparent layer, and the second insulating layer is formed on the second metal layer. The first transparent layer and the second transparent layer form a capacitor.

Description

Narrow bezel display

The invention relates to a gate driving circuit, in particular to a gate driving circuit of a narrow frame display.

With the increase in panel high-resolution and narrow bezel requirements, GOA (Gate on array) driving circuits have emerged. GOA circuits are arranged on the periphery of the panel display area to replace ordinary gate driving circuits. Please refer to the first figure, which is a top view of the conventional gate driving circuit 2. As shown in the figure, the display 10 has a display area 1, and a plurality of gate drive circuits 2 and a plurality of traces 90 are provided on the periphery of the display area 1. Generally, the gate drive circuit 2 uses metal materials as the structures of the transistors M3, M5, M6 and the capacitors Cb, C1, but the metal materials are opaque. Therefore, when the sealant 50 is coated, the The metal material makes the irradiation area of the sealant 50 insufficient, and reduces the yield of the sealant 50.

Furthermore, in order to solve the problem of insufficient irradiation area of the sealant 50, the layout of the dispersing elements is often used to increase the irradiation area of the sealant 50, for example, the plurality of transparent regions 34 shown in the first figure. Furthermore, referring to the second figure, which is a cross-sectional view of a conventional gate driving circuit and a sealant, as shown in the figure, the second figure is a cross-sectional view of the BB 'section line of the first figure. As shown from bottom to top, the display 10 has a substrate 20 on which a first metal layer 30, a first insulating layer 40, a second metal layer 32, a second insulating layer 42, and a liquid crystal layer are provided 80. A frame glue 50 and a color filter layer 60. Among them, the first The opacity of the metal layer 30 and the second metal layer 32 does affect the UV transmittance of the sealant 50. In general, the design method of the capacitor C1 (the first picture) is to increase the light-transmitting area 34 by means of dispersing elements, so as to improve the yield of the frame glue during manufacturing.

However, this method will occupy the frame area A of the display 10, and cannot achieve the design of the narrow frame display 10. In view of the above-mentioned problems, the present invention provides a gate driving circuit to meet the narrow-frame display and improve the yield of frame glue.

One of the objectives of the present invention is to provide a gate driving circuit which can meet the requirements of a narrow bezel display.

One of the objectives of the present invention is to provide a gate drive circuit, which can improve the yield of the frame glue during manufacturing.

To achieve the above object, the present invention is a narrow-frame display, which includes a gate driving circuit, the gate driving circuit includes a substrate, a first transparent layer, a first metal layer, a first insulating layer, a second A metal layer, a second insulating layer, and a second transparent layer. The first transparent layer is a transparent metal layer and formed on the substrate. The first metal layer is disposed on or under the first transparent layer. The first insulating layer is formed on the first transparent layer and the first metal layer. The two transparent layers are transparent metal layers and are formed on the first transparent layer, the second metal layer is disposed on or under the second transparent layer, the second insulating layer is formed on the second metal layer, and the second The transparent layer is a transparent metal layer and is formed on the first transparent layer. The first transparent layer and the second transparent layer form a capacitor.

Furthermore, the capacitor is formed on one side of the first metal layer and one side of the second metal layer, and a sealant is formed on the capacitor.

1‧‧‧Display area

2‧‧‧ Gate drive circuit

3‧‧‧Gate drive circuit

10‧‧‧Monitor

11‧‧‧Monitor

12‧‧‧Monitor

13‧‧‧Monitor

20‧‧‧ substrate

30‧‧‧First metal layer

32‧‧‧Second metal layer

34‧‧‧Transparent area

40‧‧‧First insulation layer

42‧‧‧Second insulation layer

50‧‧‧ frame glue

60‧‧‧Color filter layer

70‧‧‧The first transparent layer

72‧‧‧Second transparent layer

80‧‧‧Liquid crystal layer

90‧‧‧Trace

92‧‧‧Pull-up circuit

94‧‧‧pull-down circuit

300‧‧‧Side

320‧‧‧Side

500‧‧‧Side

720‧‧‧hole

A‧‧‧Border area

BB’‧‧‧hatching

C1‧‧‧Capacitor

C2‧‧‧Capacitor

Cb‧‧‧Capacitor

Cc‧‧‧Capacitor

CC’‧‧‧hatching

CLK1‧‧‧clock signal

D‧‧‧spacing

E‧‧‧non-display area

F‧‧‧ First distance

G‧‧‧Second distance

M3‧‧‧Transistor

M5‧‧‧transistor

M6‧‧‧transistor

OUT‧‧‧Output

UV‧‧‧Light

The first picture: it is the top view of the conventional gate drive circuit; the second picture: it is the sectional view of the conventional gate drive circuit and the sealant; the third picture: it is the gate drive circuit of the present invention Figure 4: It is a cross-sectional view of the gate drive circuit and sealant of the present invention; Figure 5: It is a cross-sectional view of one embodiment of the second transparent layer of the present invention; Figure 6: It is a cross-sectional view of an embodiment of the first transparent layer of the present invention; and FIG. 7 is a circuit diagram of an embodiment of the gate driving circuit of the present invention.

In order for your reviewing committee to have a better understanding and understanding of the features and effects of the present invention, we will use the embodiments and detailed descriptions as follows: please refer to the third figure, which is the gate of the present invention Top view of the pole drive circuit. As shown in the figure, the present invention is a narrow-frame display, which includes a display area 1 and a non-display area E. The non-display area E has a plurality of gate drive circuits 3 and a plurality of traces 90, Including complex transistors M3, M5, M6 and complex capacitors C2, Cc. Each gate driving circuit 3 of the present invention does not occupy the area of the frame area A, and the frame area A can be used to set the trace 90. Therefore, compared with the first figure, the conventional gate driving circuit 2 occupies the area of the frame area A, and is compressed to the area where the trace 90 can be set, so the conventional display 10 cannot achieve the design of narrow frame .

Referring back to the third figure, the capacitors C2 and Cc of the gate driving circuit 3 of the present invention are transparent semiconductors, so the light UV can penetrate the capacitors C2 and Cc to illuminate the sealant 50. Therefore, as compared with the first figure, the capacitors C1 and Cb of the conventional gate driving circuit 2 will block the light UV, so that the light UV cannot be irradiated to the sealant 50, and when the light UV of the sealant 50 When the irradiation amount is insufficient, the sealant 50 may not be cured.

Please refer to the fourth figure, which is a cross-sectional view of the gate driving circuit and the sealant of the present invention. As shown in the figure, the fourth figure is a cross-sectional view taken along the line CC 'of the third figure. The gate driving circuit 3 of the present invention includes a substrate 20, a first transparent layer 70, a first metal layer 30, a first insulating layer 40, a second metal layer 32, a second insulating layer 42, a second Transparent layer 72. The first transparent layer 70 is a transparent metal layer and formed on the substrate 20, the first metal layer 30 is disposed on or under the first transparent layer 70, and the first insulating layer 40 is formed on the first transparent layer 70 and the first On the metal layer 30, the second transparent layer 72 is a transparent metal layer and is formed on the first transparent layer 70, the second metal layer 32 is disposed on or under the second transparent layer 72, and the second insulating layer 42 is formed on the second metal layer 32, at least an insulating layer is formed between the second transparent layer 72 and the first transparent layer 70, wherein the first transparent layer 70 and the second transparent layer 72 form a capacitor C2, where the capacitor The capacitor C2 in the third diagram is used as an illustration.

Referring back to the fourth figure, the second transparent layer 72 is formed between the second insulating layer 42 and the first insulating layer 40, and the second transparent layer 72 is formed between the second metal layer 32 and the first insulating layer 40. The sealant 50 is formed on the first transparent layer 70 and the second transparent layer 72. The first transparent layer 70 and the second transparent layer 72 are formed on one side of the first metal layer 30 and one side of the second metal layer 32, respectively And, the first transparent layer 70 and the second transparent layer 72 are used to form the capacitor C2. In other words, the sealant 50 is formed on the capacitor C2, and the light UV penetrates the first transparent layer 70 and the second transparent layer 72 to illuminate the sealant 50, so that the irradiation area of the sealant 50 is increased and sufficient light UV is irradiated. To increase the yield of frame glue 50. Furthermore, the sealant 50 is formed under the color filter layer 60. A liquid crystal layer 80 is formed between the color filter layer 60 and the second insulating layer 42. The liquid crystal layer 80 is adjacent to the sealant 50. It is provided around the liquid crystal layer 80. In other words, the color filter layer 60 is disposed on the sealant 50 and the liquid crystal layer 80.

In addition, the increased light exposure range of the sealant 50 is the spacing D shown in the fourth figure The range of the distance D is calculated from the extension of one side 500 of the sealant 50 to the side 320 of the second metal layer 32. Therefore, in the fourth picture, compared with the second picture, the area from the side 500 of the frame 50 of the present invention to the side 320 of the second metal layer 32 can pass light UV to illuminate the frame 50, but the conventional gate In the structure of the pole driving circuit 2, a part of the light UV can only pass through the light-transmitting region 34, and the remaining part of the light UV is blocked by the capacitor C1 and cannot be irradiated to the sealant 50. Therefore, the gate driving circuit 3 of the present invention can improve the yield of the frame glue 50 and achieve the design of the narrow frame display 11.

Please refer to the fifth figure, which is a cross-sectional view of an embodiment of the second transparent layer of the present invention. As shown, the second transparent layer 72 of the display 12 may be disposed on the first transparent layer 70, the first metal layer 30, the first insulating layer 40, the second metal layer 32, and the second insulating layer 42, the second The transparent layer 72 is formed between the sealant 50 and the second insulating layer 42. The second transparent layer 72 forms a hole 720. The hole 720 penetrates the second insulating layer 42 and is formed between the second metal layer 32 and the second transparent layer 72. The second transparent layer 72 passes through the hole 720 and the second metal layer 32 connection. Therefore, the difference between the fifth diagram and the fourth diagram is that the second transparent layer 72 is disposed at different positions, so the second transparent layer 72 may be formed under the second metal layer 32 or above the second metal layer 32.

Following the above, the first transparent layer 70 also needs to be connected to the first metal layer 30. Furthermore, the first transparent layer 70 exceeds the side 300 of the first metal layer 30 by at least a first distance F, the second transparent layer 72 exceeds the side 320 of the second metal layer 32 by at least a second distance G, and the first The distance F, the second distance G, and the distance D also represent the irradiation area that the sealant 50 can increase, and the first distance F, the second distance G, and the distance D can be 100 μm to 200 μm.

Please refer to the sixth figure, which is a cross-sectional view of an embodiment of the first transparent layer of the present invention. As shown, the first transparent layer 70 is formed between the first metal layer 30 and the first insulating layer 40, and the first transparent layer 70 is formed between the substrate 20 and the first insulating layer 40. therefore The difference between the sixth and fourth and fifth figures is that the first transparent layer 70 of the display 13 can be disposed on the first metal layer 30, in other words, the first transparent layer 70 can be formed under the first metal layer 30 Above the first metal layer 30. Please refer to the seventh figure, which is a circuit diagram of an embodiment of the gate driving circuit of the present invention. As shown, the gate drive circuit 3 of the present invention includes a plurality of pull-up circuits 92 and a pull-down circuit 94 in addition to the complex transistors M3, M5, M6 and the complex capacitors C2, Cc. The gate driving circuit 3 receives the clock signal CLK1 to output the scan signal at the output terminal OUT. Furthermore, the coupling point between the capacitor Cc and the output terminal OUT is the first transparent layer 70, and the capacitor Cc and the pull-up circuit 92 The coupling point of is the second transparent layer 72, the rest of the techniques have been described above, and will not be repeated here.

In summary, the present invention is a narrow bezel display, which includes a gate drive circuit, the gate drive circuit includes a substrate, a first transparent layer, a first metal layer, a first insulating layer, a second A metal layer, a second insulating layer, and a second transparent layer. The first transparent layer is a transparent metal layer and formed on the substrate. The first metal layer is disposed on or under the first transparent layer. The first insulating layer is formed on the first transparent layer and the first metal layer. The two transparent layers are transparent metal layers, and are formed on the first transparent layer, the second metal layer is disposed on or under the second transparent layer, and the second insulating layer is formed on the second metal layer. The first transparent layer and the second transparent layer form a capacitor.

Furthermore, the capacitor is formed on one side of the first metal layer and one side of the second metal layer, and a sealant is formed on the capacitor.

Claims (15)

A narrow bezel display includes a gate drive circuit, the gate drive circuit includes: a substrate; a first transparent layer, which is a transparent metal layer, formed on the substrate; a first metal layer, It is disposed above or below the first transparent layer; a first insulating layer formed on the first transparent layer and the first metal layer; a second transparent layer, which is a transparent metal layer, And formed on the first transparent layer; a second metal layer, which is disposed above or below the second transparent layer; a second insulating layer, which is formed on the second metal layer; wherein, The first transparent layer and the second transparent layer form a capacitor; and a sealant is formed on the capacitor, and a side of the extension of the sealant and a side of the second metal layer have a spacing. The narrow bezel display as described in item 1 of the patent scope, wherein the second transparent layer is formed between the first insulating layer and the second metal layer, and the second transparent layer is formed on the first insulating layer and Between the second insulating layer. The narrow bezel display as described in item 1 of the patent application scope, wherein the second transparent layer is formed on the second insulating layer. The narrow bezel display according to item 3 of the patent application scope, wherein the second insulating layer comprises: a hole penetrating the second insulating layer, formed between the second metal layer and the second transparent layer; wherein, The second transparent layer is connected to the second metal layer through the hole. The narrow bezel display as described in item 1 of the patent application scope, wherein the first transparent layer is formed between the first metal layer and the first insulating layer, and the first transparent layer is formed on the substrate and the first Between insulating layers. The narrow bezel display as described in item 1 of the patent application scope includes: a liquid crystal layer, the frame ring is disposed around the liquid crystal layer; and a color filter layer, disposed on the frame rubber and the liquid crystal layer on. The narrow bezel display as described in item 1 of the patent application, wherein the first transparent layer extends beyond the side of the first metal layer by at least a first distance, and the second transparent layer extends beyond the side of the second metal layer At least a second distance. The narrow bezel display as described in item 1 of the patent scope, wherein the first transparent layer is formed above or below the first metal layer, and the second transparent layer is formed above or below the second metal layer, the The second transparent layer is connected to the second metal layer. A narrow bezel display includes: a gate drive circuit including a substrate; a first transparent layer, which is a transparent metal layer, formed on the substrate; and a first metal layer, which is disposed on the first Above or below a transparent layer; a first insulating layer formed on the first transparent layer and the first metal layer; a second transparent layer which is a transparent metal layer and formed on the first On the transparent layer; a second metal layer, which is disposed on or under the second transparent layer; a second insulating layer, which is formed on the second metal layer; a capacitor, formed on the first One side of the metal layer and one side of the second metal layer, the second transparent layer and the first transparent layer form the capacitor; and a sealant formed on the capacitor, one side of the sealant There is a distance between the extension and one side of the second metal layer. The narrow bezel display as described in item 9 of the patent scope, wherein the second transparent layer is formed between the second insulating layer and the first insulating layer, and the second transparent layer is formed on the second metal layer and Between the first insulating layer. The narrow bezel display according to item 9 of the patent application scope, wherein the second transparent layer is formed on the second insulating layer, and the second transparent layer is formed between the sealant and the second insulating layer. The narrow bezel display as described in item 9 of the patent scope, wherein the first transparent layer is formed between the first metal layer and the first insulating layer, and the first transparent layer is formed on the substrate and the first Between insulating layers. The narrow bezel display as described in item 9 of the patent application scope, wherein the gate driving circuit is disposed in a non-display area of the narrow bezel display and has the capacitor. The narrow bezel display as described in item 9 of the patent application range, wherein the first transparent layer extends beyond the side of the first metal layer by at least a first distance, and the second transparent layer extends beyond the side of the second metal layer At least a second distance. The narrow bezel display as described in item 9 of the patent application scope, wherein the first transparent layer is formed above or below the first metal layer, and the second transparent layer is formed above or below the second metal layer, the The second transparent layer is connected to the second metal layer.