TWI603132B - Display panel - Google Patents

Description

Display panel

The present invention relates to a display panel, and more particularly to a narrow bezel display panel.

With the advancement of technology, the technology of liquid crystal display panels has also been continuously developed. In order to further increase the area of the display area of the liquid crystal display panel, the demand for slim border design has also emerged.

Generally, a liquid crystal display panel is mainly composed of an upper substrate, a lower substrate, and a liquid crystal layer sandwiched between the upper substrate and the lower substrate. In order to bond the upper substrate and the lower substrate, a sealant is usually formed between the upper substrate and the lower substrate, and the sealant surrounds the pixel array, and the liquid crystal layer is disposed on the upper substrate and the lower substrate and the sealant. In a closed space. In addition, the common electrode of the substrate above the liquid crystal display panel is electrically connected to the transfer pad of the substrate below the liquid crystal display panel.

With the advancement of technology, the demand for increasing the display area of the liquid crystal display panel has gradually increased. However, when the frame of the liquid crystal display panel becomes smaller, the area of the transfer pad is covered by the alignment film, so that the common electrode of the upper substrate cannot be electrically connected to the transfer pad of the lower substrate, causing display abnormality.

Embodiments of the present invention provide a display panel that can meet the requirements of a narrow bezel design while ensuring that the transfer pad joint can be prevented from being blocked by the alignment film to smoothly conduct each other.

According to an embodiment of the invention, a display panel includes an array substrate and a pair of substrates. The array substrate includes a first substrate, a plurality of first signal lines, a plurality of second signal lines, and at least one first transfer pad. The first substrate has a display area and a peripheral area on at least one side of the display area. The first signal line is disposed on the first substrate. The second signal line is disposed on the first substrate and disposed opposite to the first signal line. The first transfer pad is disposed in a peripheral region of the first substrate. The opposite substrate comprises a second substrate, at least one second transfer pad, a light shielding layer, a common electrode and a first alignment film. The second substrate has a display area corresponding to the first substrate and a peripheral area on at least one side of the display area. The second transfer pad is disposed in a peripheral area of the second substrate, wherein the second transfer pad is electrically connected to the first transfer pad. The light shielding layer is disposed on the second substrate at least partially corresponding to the first signal line and the second signal line, wherein the light shielding layer comprises at least one unit light shielding portion, and the unit light shielding portion has a slit. The common electrode is disposed on the light shielding layer and electrically connected to the second transmission pad. The first alignment film is disposed over the common electrode, and the first alignment film is disposed within the slit. The unit light shielding portion is adjacent to a boundary of the display area of the second substrate, and corresponds to the second transmission pad of the peripheral area.

In an embodiment of the invention, the display area of the second substrate has a central portion, and the light shielding layer at the central portion is a continuous mesh structure.

In an embodiment of the invention, the light shielding layer located at the central portion does not have a slit.

In an embodiment of the invention, the unit light shielding portion at least partially overlaps a portion of the first signal line and the second signal line in a projection direction perpendicular to the first substrate.

In an embodiment of the invention, the slit is disposed corresponding to a portion of the first signal line.

In an embodiment of the invention, the second transport pad is disposed on at least one corner region of the peripheral region of the second substrate, and the unit light shielding portion is located at at least one corner region of the display region of the second substrate.

In an embodiment of the invention, the light shielding frame body is further disposed on the peripheral area of the second substrate and disposed corresponding to the peripheral area of the first substrate.

In an embodiment of the invention, the second transport pad is located on the light shielding frame.

In an embodiment of the invention, the light shielding frame is connected to the light shielding layer.

In an embodiment of the invention, at least one second transport pad is disposed in at least one corner region of the light shielding frame, and the unit light shielding portion is disposed on at least one corner region of the inner side of the light shielding frame.

In an embodiment of the invention, the first signal line and the second signal line are disposed to define a plurality of pixel regions, and the unit light blocking portion is disposed corresponding to a portion of the pixel region.

In an embodiment of the invention, the plurality of pixel units are further disposed in the pixel area of the array substrate. Each pixel unit includes an active component and a pixel electrode. The active component is electrically connected to the corresponding first signal line and the second signal line, and the pixel electrode is electrically connected to the active component.

In an embodiment of the invention, the second alignment film is further disposed on the pixel unit.

In an embodiment of the invention, a conductive element is further disposed between the array substrate and the opposite substrate to electrically connect the first transfer pad and the second transfer pad.

In an embodiment of the invention, the area of the first transport pad is X, the area of the light-shielding portion of the unit is Y, and the ratio of the ratio of Y/X is between 4 and 6.

In an embodiment of the invention, one of the slits has a width along the extending direction of the first signal line between 8 and 12 micrometers.

Based on the above, since the unit light shielding portion of the light shielding layer has a slit design, the alignment film can be prevented from covering the second transmission pad, so that the first transmission pad of the array substrate and the second transmission pad of the opposite substrate can maintain good electrical power. Sexual connection.

Furthermore, since the unit light shielding portion of the light shielding layer has a slit design, the display area of the second substrate adjacent to the peripheral area can ensure complete coverage of the alignment film, so that the display area of the second substrate adjacent to the peripheral area can provide an effective alignment and avoid display. The abnormal arrangement of the dielectric layer molecules (for example, liquid crystal molecules) leads to light leakage and can improve the display quality.

The above description of the present invention and the following description of the embodiments are intended to illustrate and explain the principles of the invention, and to provide a further explanation of the scope of the invention.

The various embodiments of the present invention are disclosed in the drawings, and in the claims However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified manner.

In the following detailed description, reference is made to the accompanying drawings. In the drawings, like reference characters generally refer to the The exemplary embodiments described in the Detailed Description, the drawings, and the claims are not limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein. It should be understood that the various aspects of the present disclosure, which are set forth in the <RTIgt;

The words used in the text are for the purpose of describing particular embodiments and are not intended to limit the invention. As used herein, the singular forms " " " The use of "first", "second", etc., is used to describe various elements, regions, layers, etc., but such terms are used to distinguish one element, region or layer from another element, region or layer. Thus, a first element, component, region, layer, and/or portion discussed below may be referred to as a second element, component, region, layer, and/or portion, without departing from the disclosure. In addition, spatially relative terms such as "under", "on", "lower", "upper" and the like may be used herein to describe one element or feature in the drawings. The relationship of a component or feature. It will be appreciated that the spatially relative terms may encompass different orientations of the elements in the application in addition to the orientation depicted in the drawings. For example, elements in the "following" or "beneath" or "an" or "an" Thus, the spatially relative terms "under" can include both orientations above and below.

As used herein, the terms "about", "about", "nearly" or "substantially" shall mean substantially within twenty percent of a given value or range, preferably in percent. Within ten, better than five percent. The quantities provided herein are approximate, meaning that unless otherwise stated, the terms "about", "about" or "nearly" may be used.

In the figures, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Throughout the specification, the same reference numerals denote the same elements. It will be understood that when an element such as a layer, a film, a region or a substrate is referred to as "on" or "connected to" another element, it can be Intermediate components can also be present. In contrast, when an element is referred to as “directly on” or “directly connected to” another element, As used herein, "connected" may refer to both physical and/or electrical connections.

Please refer to Figure 1 to Figure 6. 1 is a top plan view of a display panel according to a first embodiment of the present invention, FIG. 2 is a partial cross-sectional view of the display panel taken along line AA' of FIG. 1, and FIG. 3 is a view of the display panel of FIG. FIG. 4 is a top view of the opposite substrate in the display panel of FIG. 1 , and FIG. 5A is a partial cross-sectional view of the opposite substrate taken along line B-B′ of FIG. 4 , 5B is a partial cross-sectional view of the opposite substrate taken along the line C-C' of FIG. 4, and FIG. 6 is a top view of the relative position of the light shielding layer and the pixel unit of the display panel of the first embodiment of the present invention. schematic diagram. As shown in FIGS. 1 to 6 , the display panel 10 of the present embodiment includes an array substrate 100 and a counter substrate 200 . The display panel 10 includes a plurality of pixel opening areas OP. The array substrate 100 includes a first substrate 110, a plurality of first signal lines SL1, a plurality of second signal lines SL2, and at least one first transfer pad PAD1. The first substrate 110 has a display area 112 and a peripheral area 114 on at least one side of the display area 112. The first signal line SL1 and the second signal line SL2 are disposed on the first substrate 110, and the first signal line SL1 and the second signal line SL2 are disposed to cross each other. The first transfer pad PAD1 is disposed on the peripheral region 114 of the first substrate 110. The opposite substrate 200 includes a second substrate 210, at least one second transfer pad PAD2, a light shielding layer 220, a common electrode CE, and a first alignment film 240. The second substrate 210 has a display area 212 corresponding to the first substrate 110 and a peripheral area 214 located on at least one side of the display area 212. The second transfer pad PAD2 is disposed on the peripheral region 214 of the second substrate 210, wherein the second transfer pad PAD2 is electrically connected to the first transfer pad PAD1. The light shielding layer 220 is disposed on the second substrate 210 at least partially corresponding to the first signal line SL1 and the second signal line SL2, wherein the light shielding layer 220 includes at least one unit light shielding portion 222, the unit light shielding portion 222 has a slit 224; In this embodiment, the light shielding layer is, for example, an organic opaque material. The common electrode CE is disposed on the light shielding layer 220 and electrically connected to the second transmission pad PAD2. The first alignment film 240 is disposed over the common electrode CE, and the first alignment film 240 is disposed within the slit 224. The unit light shielding portion 222 is adjacent to one of the boundaries 212S1 of the display region 212 of the second substrate 210 and corresponds to the second transmission pad PAD2 of the peripheral region 214.

In this embodiment, as shown in FIG. 2 to FIG. 3 , the array substrate 100 includes a first substrate 110 , which may be a rigid substrate or a flexible substrate such as a glass substrate, a quartz substrate, a sapphire substrate, a plastic substrate, or Other suitable substrates. The first substrate 110 has a display area 112 and a peripheral area 114 located on at least one side of the display area 112. A plurality of first signal lines SL1 and a plurality of second signal lines SL2 are disposed on the first substrate 110. An insulating layer (not shown) is disposed between the first signal lines SL1 and the second signal lines SL2. In this embodiment, the first signal line SL1 and the second signal line SL2 are disposed to define a plurality of pixel regions 116, and the plurality of pixel units PU are disposed in the pixel region 116. Each of the pixel units PU includes an active component SW and a pixel electrode PE. The active component SW is electrically connected to the corresponding first signal line SL1 and the second signal line SL2, and the pixel electrode PE and the active component SW are electrically connected. Sexual connection. In this embodiment, the active device SW is, for example, a thin film transistor device, and includes a gate GE, a semiconductor layer CH, a gate insulating layer GI, a source SE, and a drain DE, but limit. In addition, the first transfer pad PAD1 is disposed in the peripheral region 114 of the periphery of the display region 112 of the first substrate 110. In this embodiment, the first transfer pad PAD1 is located at one side of the array substrate 110. In addition, in the embodiment, the array substrate 100 can also form a common line (not shown), and the common line can be coupled with corresponding other elements to generate a capacitor Cs.

Further, in the present embodiment, as shown in Figs. 2, 4, 5A and 5B. The opposite substrate 200 includes a second substrate 210, which may be a rigid substrate or a flexible substrate, such as a glass substrate, a quartz substrate, a sapphire substrate, a plastic substrate, or other suitable substrate. The second substrate 210 has a display area 212 and a peripheral area 214 located on at least one side of the display area 212. The display area 212 has a central portion 212c and a peripheral portion 212p surrounding the central portion. The light shielding layer 220 is disposed on the second substrate 210 , wherein the light shielding layer 220 is located in the display area 212 . In the embodiment, the light shielding layer 220 includes at least one unit light shielding portion 222, and the unit light shielding portion 222 has a plurality of slits 224. The opposite substrate 200 may further include a light shielding frame 230. The light shielding frame 230 is disposed on the peripheral region 214 of the second substrate 210, and is disposed corresponding to the peripheral region 114 of the first substrate 110. The light shielding frame 230 is disposed. It can be connected to the light shielding layer 220, but is not limited thereto. In addition, the common transfer electrode CE is disposed on the light shielding layer 220, and the second transfer pad PAD2 is disposed on the peripheral region 214 of the second substrate 210. In this embodiment, for example, the second transfer pad PAD2 is located on the light shielding frame 230, but not Limited. The common electrode CE is electrically connected to the second transfer pad PAD2. The first alignment film 240 is disposed over the common electrode CE, and the first alignment film 240 is disposed within the slit 224. As shown in FIG. 4, the unit light blocking portion 222 of the present embodiment is disposed adjacent to one of the boundaries 212S1 of the display area 212 of the second substrate 210, and is disposed corresponding to the second transfer pad PAD2. In addition, in an embodiment, the light shielding layer 220 located at the central portion 212c is a continuous mesh structure. For example, in the embodiment, the light shielding layer 220 located at the central portion 212c does not have a slit, which is periodically and continuously set. The mesh structure is located, and the unit light blocking portion 222 is located adjacent to the peripheral portion 212p of the second transfer pad PAD2.

Specifically, in one embodiment, the unit light shielding portion 222 at least partially overlaps a portion of the first signal line SL1 and the second signal line SL2 in a projection direction Z perpendicular to the first substrate 110. The slit 224 of the unit light blocking portion 222 is provided corresponding to the first signal line SL1. The slit 224 of the unit light shielding portion 222 has a width W in the direction along which the first signal line SL1 extends, for example, between 8 and 12 micrometers. It should be noted that the first signal line SL1 is, for example, a data line connected to the source SE, but is not limited thereto. The first signal line SL1 can also be, for example, a scan line connected to the gate stage GE. In detail, in an embodiment, the slit 224 of the unit light shielding portion 222 may be disposed corresponding to the data line; in another embodiment, the slit 224 of the unit light shielding portion 222 may be disposed corresponding to the scan line; In a variant embodiment, the slit 224 of the unit light-shielding portion 222 can be disposed corresponding to the data line and the scan line. Further, in an embodiment, the area of the first transfer pad PAD1 is X, and the area of the unit light blocking portion 222 is Y, wherein the ratio of Y/X is between 4 and 6.

Referring to FIG. 2 to FIG. 3 again, in the embodiment, the array substrate 100 and the opposite substrate 200 are disposed opposite to each other, and the display medium layer 300 is disposed between the array substrate 100 and the opposite substrate 200. In more detail, the first alignment film 240 is disposed on the common electrode CE, the second alignment film 140 is disposed on the pixel unit PU, and the display dielectric layer 300 is disposed on the first alignment film 240 and the second alignment film. Between 140. The first transfer pad PAD1 of the array substrate 100 and the second transfer pad PAD2 of the opposite substrate 200 are electrically connected to each other. In addition, in the embodiment, the peripheral region 112 of the first substrate 110 further includes a metal transfer pad 120, and the metal transfer pad 120 is electrically connected to the first transfer pad electrically conductive PAD1 through the contact window 132 in the insulating layer 130. In the present embodiment, the metal transfer pad 120 can be electrically connected to the common line in the pixel unit, for example, the common electrode CE and the second transfer pad PAD2 can be electrically connected to the first transfer pad electrical PAD1. The metal transfer pad 120 and the common line are provided to provide a certain potential.

In addition, in the embodiment, a conductive element 400 is disposed between the array substrate 100 and the opposite substrate 200 and surrounds the display medium layer 300. The first transfer pad electrically conductive PAD1 is electrically connected to the second transfer pad PAD2 through the conductive sealant 400. In this embodiment, the conductive element 400 is composed of, for example, an insulating rubber 410 and conductive particles 420 doped in the insulating rubber 410. The conductive particles 420 are randomly dispersed in the insulating rubber 410, wherein the insulating rubber material The material of 410 is, for example, a resin, and the conductive particles 420 are, for example, Au balls. Since the conductive particles 420 are previously doped in the insulating rubber 420, the first transfer pad electrical PAD1 is electrically connected to the second transfer pad PAD2 after the conductive sealant 420 is coated.

In this embodiment, the first alignment film 240 and the second alignment film 140 can be fabricated by an inkjet process technology. The second alignment film 140 is formed by spraying an alignment material solution on the first substrate 110 on which the pixel unit PU and the first transmission pad PAD1 are formed, and then performing a curing process to make the alignment material solution. Curing into the second alignment film 140. Similarly, the first alignment film 240 is formed by spraying an alignment material solution on the second substrate 210 on which the light shielding layer 220 and the second transmission pad PAD2 are formed, and then performing a curing process to make The alignment material solution is solidified into the first alignment film 240. The aforementioned curing process is, for example, a heat curing process, an ultraviolet curing process, or other suitable curing process. It should be noted that, in the opposite substrate of the display panel in the embodiment, the unit light shielding portion 222 of the light shielding layer 220 has a plurality of slits 224, so the inkjet printing process is used to spray the second substrate on the opposite substrate. When the material solution is aligned, the second transfer pad PAD2 of the adjacent unit light shielding portion 222 can be prevented from being covered by the alignment material solution, and the display area of the opposite substrate can be simultaneously covered with the full alignment material. The first alignment film 240 and the second alignment film 140 are not limited to an inkjet printing technique. The first alignment film 240 of the embodiment can also be formed on the common electrode CE by a coating technique. And the second alignment film 140 can also be formed on the pixel unit PU by a coating technique.

In the present embodiment, the type of the display panel 10 is not limited, and the display panel 10 has a different mechanism of action depending on the display medium layer 300. For example, the display medium layer 300 can be a liquid crystal material or other material that also has an alignment requirement. When the display medium layer 300 is a liquid crystal material, the display panel 100 is referred to as a liquid crystal display panel. For example, the liquid crystal display panel may be a vertical electric field type liquid crystal display panel, for example, a vertical alignment (VA) type liquid crystal display panel, and the liquid crystal display panel may also be a horizontal electric field type liquid crystal display panel, for example, a planar switching type (IPS) liquid crystal. Display panel or edge electric field switching type (FFS) liquid crystal display panel. Of course, those of ordinary skill in the art will appreciate that the design concepts of the present embodiments can still be reasonably applied to other types of display panels.

Further, in the present embodiment, the array substrate 100 is, for example, a thin film transistor array substrate. In other embodiments, the array substrate 100 may further include a color filter layer (not shown) between the flat layer PL and the pixel electrode PE, that is, the COA (Color) integrated with the color filter layer in the array substrate 100. Filter on Array).

As described above, in the display panel of the present embodiment, since the unit light shielding portion of the light shielding layer has a slit design, the inside of the unit light shielding portion can form an accommodation space that communicates with each other when the alignment material solution is sprayed adjacent to the second transmission. In the unit light-shielding portion of the pad, the alignment material solution can flow through the slit and flow into the space inside the unit light-shielding portion, and is evenly distributed in the space inside the unit light-shielding portion, so as to have a large precision control for the ink-jet printing process. Tolerance. Thereby, the first alignment film can be prevented from covering the second transfer pad, so that the first transfer pad of the array substrate and the second transfer pad of the opposite substrate can maintain a good electrical connection.

Furthermore, since the unit light shielding portion of the light shielding layer has a slit design, the display area of the second substrate adjacent to the peripheral area can ensure complete coverage of the alignment film, so that the display area of the second substrate adjacent to the peripheral area can provide an effective alignment and avoid display. The alignment of the dielectric layer molecules (for example, liquid crystal molecules) leads to light leakage and can improve display quality.

According to the display panel 10 of the first embodiment of the present invention, the second transfer pad PAD2 and the unit light blocking portion 222 are disposed at a boundary 212S1. However, the second transfer pad PAD2 may vary according to design requirements. For example, as shown in FIG. 7, in a variant embodiment, the second transfer pad PAD2 of the opposite substrate 200A may be disposed at the boundary 212S1. The boundary 212S2, the boundary 212S3, and the peripheral region 214 of the boundary 212S4, and the unit light shielding portion 222 are disposed corresponding to the display region 212 adjacent to the boundary 212S1, the boundary 212S2, the boundary 212S3, and the boundary 212S4 with respect to the second transfer pad PAD2. The four second transfer pads PAD2 of the opposite substrate 200A are electrically connected to the four first transfer pads PAD1 of the array substrate 100.

8 is a top plan view of a counter substrate of a display panel according to a second embodiment of the present invention. Figure 9A is a partial cross-sectional view of the opposite substrate taken along section line D-D' of Figure 8 . Figure 9B is a partial cross-sectional view of the opposite substrate taken along line E-E' of Figure 8. The counter substrate 200B of FIG. 8 is similar to the counter substrate 200 of FIG. 4, and thus the same or corresponding elements are denoted by the same or corresponding reference numerals. The difference between the two is that the positions of the second transfer pad PAD2 and the unit light blocking portion 222 of the opposite substrate 200B are different from those of the second transfer pad PAD2 and the unit light blocking portion 222 of the opposite substrate 200. In the following, the description of the difference between the two can be made. The same reference numerals are used to refer to the description of FIG. 4 in the same manner as in FIG. 8 , and the repeated portions will not be described again.

In the opposite substrate 200B, the second transfer pad PAD2 is disposed at a corner region 214C1 of the peripheral region 214 of the second substrate 210, and the cell light shielding portion 222 is located at at least one corner region 212C1 of the display region 212 of the second substrate 210. The second transfer pad PAD2 of the opposite substrate B is electrically connected to the first transfer pad PAD1 of the array substrate 100. In one embodiment, the second transport pad PAD2 may be disposed on at least one corner region 214C1 of the light-shielding frame 230, and the unit light-shielding portion 222 is disposed on at least one corner region 212C1 of the inner side of the light-shielding frame 230. In other words, the second transport pad PAD2 and the unit light blocking portion 222 are not disposed at the boundary 212S of the display area 212. Thus, the slit 224 of the unit light blocking portion 222 is located at the corner area 212C1, which can enhance the contrast of the display area for the user to watch. To a better display.

Further, in the present embodiment, the second transfer pad PAD2 is disposed in a corner region 214C1 and the cell light blocking portion 222 is disposed in a corner region 212C1. However, the second transfer pad PAD2 may vary according to design requirements. For example, as shown in FIG. 10, in a variant embodiment, the second transfer pad PAD2 of the opposite substrate 200C may be disposed in the corner region 214C1. The corner area 214C2, the corner area 214C3, and the corner area 214C4, and the unit light blocking portion 222 may be correspondingly disposed in the corner area 212C1, the corner area 212C2, the corner area 212C3, and the corner area 212C4 with respect to the second transport pad PAD2. The four second transfer pads PAD2 of the counter substrate 200C are electrically connected to the four first transfer pads PAD1 of the array substrate 100.

In addition, in other variant embodiments, the second transport pad PAD2 may be disposed in the four regions 212S1, the boundary 212S2, the boundary 212S3, and the peripheral region 214 of the boundary 212S4, and also disposed in the four corner regions 214C1 and the corner region 214C2. The area 214C3 and the corner area 214C4, and the unit light blocking unit 222 also corresponding to the display area 212 and the four corner areas 212C1, the corner area 212C2, the corner area 212C3, and the corner area disposed at the four boundaries 212S1, the boundary 212S2, the boundary 212S3, and the boundary 212S4. 212C4, by which, it is possible to provide a display panel, in particular a medium-sized display panel, with a more uniform potential.

In the above, in the opposite substrate of the display panel of the embodiment of the invention, the light shielding layer has a unit light shielding portion, and the unit light shielding portion has a plurality of slits. Therefore, it is possible to prevent the first alignment film from covering the second transfer pad, and the display area of the second substrate adjacent to the peripheral region can ensure that the alignment film is completely covered. In this way, the first transfer pad of the array substrate and the second transfer pad of the opposite substrate can maintain a good electrical connection, and the display area of the second substrate adjacent to the peripheral area can also provide an effective alignment to avoid molecular alignment of the display medium layer. Anomalies that cause light leakage can provide better display quality.

Although the embodiments of the present invention and its advantages are disclosed above, it should be understood that those skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of the invention. In addition, the scope of the present invention is not limited to the processes, machines, manufacture, compositions, devices, methods, and steps in the specific embodiments described in the specification. Any one of ordinary skill in the art can. The processes, machines, fabrications, compositions, devices, methods, and procedures that are presently or in the future are understood to be used in accordance with the present invention as long as they can perform substantially the same function or achieve substantially the same results in the embodiments described herein. Accordingly, the scope of the invention includes the above-described processes, machines, manufactures, compositions, devices, methods, and steps. In addition, the scope of each of the claims constitutes an individual embodiment, and the scope of the invention also includes the combination of the scope of the application and the embodiments.

10‧‧‧ display panel

100‧‧‧ Array substrate

110‧‧‧First substrate

112‧‧‧ display area

114‧‧‧The surrounding area

116‧‧‧ pixel area

120‧‧‧Metal transfer mat

130‧‧‧Insulation

140‧‧‧Second alignment film

200, 200A, 200B, 200C‧‧‧ opposite substrates

210‧‧‧First substrate

212‧‧‧ display area

212c‧‧‧Central Part

212p‧‧‧ peripheral parts

212S1, 212S2, 212S3, 212S4‧‧‧ border

212C1, 212C2, 212C3, 212C4‧‧‧ corner area

214‧‧‧The surrounding area

214C1, 214C2, 214C3, 214C4‧‧‧ corner area

220‧‧‧Lighting layer

222‧‧‧Unit shading department

224‧‧‧slit

230‧‧‧Lighting frame

240‧‧‧First alignment film

300‧‧‧Display media layer

400 ‧‧‧Conducting components

410‧‧‧Insulating rubber

420‧‧‧ conductive particles

CE‧‧‧Common electrode

CH‧‧‧Semiconductor layer

DE‧‧‧汲

GE‧‧‧ gate

GI‧‧‧ gate insulation

OP‧‧‧ pixel open area

PAD1‧‧‧First Transfer Pad

PAD2‧‧‧Second transport pad

PE‧‧‧ pixel electrode

PL‧‧‧flat layer

PU‧‧‧ pixel unit

SE‧‧‧ source

SL1‧‧‧first signal line

SL2‧‧‧second signal line

SW‧‧‧Active components

W‧‧‧Width

Z‧‧‧projection direction

1 is a top plan view of a display panel according to a first embodiment of the present invention; FIG. 2 is a partial cross-sectional view of the display panel taken along line AA' of FIG. 1; FIG. 3 is a view of the display panel of FIG. Figure 4 is a top plan view of the opposite substrate in the display panel of Figure 1; Figure 5A is a partial cross-sectional view of the opposite substrate taken along line BB' of Figure 4; 5B is a partial cross-sectional view of the opposite substrate taken along the line C-C' of FIG. 4; FIG. 6 is a top view of the relative position of the light shielding layer and the pixel unit of the display panel of the first embodiment of the present invention; FIG. 7 is a top view of a display panel according to a second embodiment of the present invention; FIG. 8 is a top view of the opposite substrate of the display panel according to the second embodiment of the present invention; Figure 8B is a partial cross-sectional view of the opposite substrate taken along section line E-E' of Figure 8; Figure 10 is a cross-sectional view of the opposite substrate taken along line EE' of Figure 8; A top view of a display panel of a variation embodiment of the second embodiment.

200‧‧‧ opposite substrate

210‧‧‧second substrate

212‧‧‧ display area

212S1, 212S2, 212S3, 212S4‧‧‧ border

212c‧‧‧Central Part

212p‧‧‧ peripheral parts

214‧‧‧The surrounding area

220‧‧‧Lighting layer

222‧‧‧Unit shading department

224‧‧‧slit

230‧‧‧Lighting frame

PAD2‧‧‧Second transport pad

W‧‧‧Width

Claims (15)

A display panel comprising: an array substrate, comprising: a first substrate having a display area and a peripheral area on at least one side of the display area; a plurality of first signal lines disposed on the first substrate; a plurality of second signal lines disposed on the first substrate, wherein the second signal lines are disposed to intersect with the first signal lines; and at least one first transmission pad disposed on the periphery of the first substrate And a pair of substrates, comprising: a second substrate having a display area corresponding to the first substrate and a peripheral area on at least one side of the display area; at least one second transfer pad disposed on the The peripheral region of the second substrate, wherein the at least one second transmission pad is electrically connected to the at least one first transmission pad; and a light shielding layer at least partially corresponding to the first signal lines and the second signal lines The light shielding layer is disposed on the second substrate, wherein the light shielding layer comprises at least one unit light shielding portion, wherein the light shielding portion has a plurality of slits, and the slits are disposed corresponding to the first plurality of signal lines; a common electrode, Set to Layer on the light, wherein the common electrode and the second pads are electrically connected to the transmission; and a first alignment film disposed on the common electrode and the first alignment film disposed within the plurality of slits; The light shielding portion of the unit is adjacent to a boundary of the display area of the second substrate, and corresponds to the at least one second transmission pad. The display panel of claim 1, wherein the display area of the second substrate has a central portion, and the light shielding layer located in the central portion is a continuous mesh structure. The display panel of claim 2, wherein the light shielding layer located in the central portion does not have a slit. The display panel of claim 1, wherein the unit light shielding portion at least partially overlaps a portion of the first signal lines and the second signal lines in a projection direction perpendicular to the first substrate. The display panel of claim 1, wherein the at least one second transport pad is disposed in at least one corner region of the peripheral region of the second substrate, and the unit light shielding portion is located in the display region of the second substrate A corner area. The display panel of claim 1, further comprising a light shielding frame disposed in a peripheral area of the second substrate, wherein the light shielding frame is disposed corresponding to the peripheral area of the first substrate. The display panel of claim 6, wherein the at least one second transport pad is located on the light shielding frame. The display panel of claim 6, wherein the light shielding frame is connected to the light shielding layer. The display panel of claim 6, wherein the at least one second transport pad is disposed in at least one corner region of the light-shielding frame, and the unit light-shielding portion is disposed on at least one corner region of the inner side of the light-shielding frame. The display panel of claim 1, wherein the first signal lines and the plurality of The second signal line cross setting defines a plurality of pixel regions, and the unit light blocking portion is disposed corresponding to a part of the pixel regions. The display panel of claim 10, further comprising: a plurality of pixel units disposed in the pixel regions of the array substrate, each pixel unit including an active component and a pixel electrode, wherein the active component An element is electrically connected to the corresponding first signal line and the second signal line, and the pixel electrode is electrically connected to the active element; and a display medium layer is disposed between the array substrate and the opposite substrate . The display panel of claim 11, further comprising a second alignment film disposed on the pixel units. The display panel of claim 1, further comprising a conductive component between the array substrate and the opposite substrate to electrically connect the at least one first transfer pad and the at least one second transfer pad. The display panel of claim 1, wherein the area of the first transport pad is X, the area of the light shielding portion of the unit is Y, and the ratio of Y/X is between 4 and 6. The display panel of claim 1, wherein a width of one of the slits along the extending direction of the first signal line is between 8 and 12 micrometers.