CN204389902U - A kind of digital display high-precision electronic clock based on CPLD digital circuit - Google Patents
A kind of digital display high-precision electronic clock based on CPLD digital circuit Download PDFInfo
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- CN204389902U CN204389902U CN201520023894.6U CN201520023894U CN204389902U CN 204389902 U CN204389902 U CN 204389902U CN 201520023894 U CN201520023894 U CN 201520023894U CN 204389902 U CN204389902 U CN 204389902U
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Abstract
The utility model discloses a kind of digital display high-precision electronic clock based on CPLD digital circuit, belong to electronic clock field, the built-in system of electronic clock comprises CPLD, crystal oscillator unit, frequency division/counting unit, second 60 system unit, point 60 system unit, time 24 system unit, decoding unit, display unit, operation control unit; The utility model designs based on CPLD, its resource can meet the design requirement of electronic clock, this electronic clock have display " second ", " dividing ", " time " effect, 24 hours display modes, and there is the function of setup times, and the utility model is based on external crystal-controlled oscillation clocking, VHDL language is utilized to adopt the modules of the patten's design CPLD of digital circuit, thus the precision greatly improved when walking and accuracy.
Description
Technical field
The utility model discloses a kind of digital display high-precision electronic clock, belong to electronic clock field, specifically a kind of digital display high-precision electronic clock based on CPLD digital circuit.
Background technology
The indicating clock of current market circulation, majority is all carry out signal control by single-chip microcomputer, and through walking about after a while, the error of time accuracy can be increasing, occurs accelerating, unstable situation such as slack-off grade.For the problems referred to above, the utility model provides a kind of design based on the digital display high-precision electronic clock based on CPLD digital circuit, design based on CPLD, this electronic clock has display " second ", " divide ", " time " effect, 24 hours display modes, and there is the function of setup times, by external crystal-controlled oscillation clocking, VHDL language is utilized to adopt the modules of the patten's design CPLD of digital circuit, avoid because Single-chip Controlling easily affects by external signal interference and the circumscribed of single-chip microcomputer, the error-reduction of enable clock is to minimum, accuracy when substantially increasing away.
Summary of the invention
The indicating clock that the utility model circulates for market, majority is all carry out signal control by single-chip microcomputer, through walking about after a while, the error of time accuracy can be increasing, appearance accelerates, the problem of unstable situation such as slack-off grade, a kind of digital display high-precision electronic clock based on CPLD digital circuit is provided, VHDL language is utilized to adopt the patten's design CPLD of digital circuit, external crystal-controlled oscillation is adopted to provide clock signal, avoid because Single-chip Controlling easily affects by external signal interference and the circumscribed of single-chip microcomputer, the error-reduction of enable clock is to minimum, accuracy when substantially increasing away.
The technical scheme that the utility model adopts is:
Based on a digital display high-precision electronic clock for CPLD digital circuit, the built-in system of electronic clock comprises CPLD unit, crystal oscillator unit, frequency division/counting unit, second 60 system unit, point 60 system unit, time 24 system unit, decoding unit, display unit, operation control unit;
CPLD unit is the core control part of whole electronic clock, is responsible for the control of the combination complicated at a high speed of each unit of built-in system, sequential logic;
Crystal oscillator unit is the external clock of built-in system, as clock source for CPLD unit provides a reference time;
Frequency division/counting unit carries out frequency division and counting to crystal oscillator unit as clock source, produces the least count unit of clock signal as electronic clock of " 1 second ", for each unit;
Second 60 system unit take second as chronomere, carry out the counting of 60 systems, counting region 0 ~ 59, and to point 60 system unit carries when counting down to 60, then this unit returns 0 and again counts, and constantly circulates;
Point 60 system unit, to be divided into chronomere, carry out the counting of 60 systems, counting region 0 ~ 59, when counting down to 60 to time 24 system unit carries, this unit returns 0 and again counts, and constantly circulates;
Time 24 system unit while taking as chronomere, carry out the counting of 24 systems, counting region 0 ~ 23, when counting down to 24, this unit returns 0 and again counts, and constantly circulates;
Decoding unit to second 60 system unit, point 60 system unit and time 24 system unit counting export and carry out decoding, control display unit and carry out numerical monitor;
Display unit is responsible for showing time figure corresponding to decoding unit;
Operation control unit and button with the use of, control system carries out the setting of time.
Described electronic clock comprises CPLD, 1MHz crystal oscillator, LED charactron, button;
Wherein CPLD model is the EPM7064STC100-10 of MAX7000S series 100 pins;
LED charactron divides three groups, respectively corresponding second 60 system unit, point 60 system unit, time 24 system unit, with the display word time;
By carrying out the setting of time by key control system.
A kind of built-in system of the digital display high-precision electronic clock based on CPLD digital circuit, be applied to described a kind of digital display high-precision electronic clock based on CPLD digital circuit, comprise CPLD unit, crystal oscillator unit, frequency division/counting unit, second 60 system unit, point 60 system unit, time 24 system unit, decoding unit, display unit, operation control unit;
CPLD unit is the core control part of whole electronic clock, is responsible for the control of the combination complicated at a high speed of each unit of built-in system, sequential logic;
Crystal oscillator unit is the external clock of built-in system, as clock source for CPLD unit provides a reference time;
Frequency division/counting unit carries out frequency division and counting to crystal oscillator unit as clock source, produces the least count unit of clock signal as electronic clock of " 1 second ", for each unit;
Second 60 system unit take second as chronomere, carry out the counting of 60 systems, counting region 0 ~ 59, and to point 60 system unit carries when counting down to 60, then this unit returns 0 and again counts, and constantly circulates;
Point 60 system unit, to be divided into chronomere, carry out the counting of 60 systems, counting region 0 ~ 59, when counting down to 60 to time 24 system unit carries, this unit returns 0 and again counts, and constantly circulates;
Time 24 system unit while taking as chronomere, carry out the counting of 24 systems, counting region 0 ~ 23, when counting down to 24, this unit returns 0 and again counts, and constantly circulates;
Decoding unit to second 60 system unit, point 60 system unit and time 24 system unit counting export and carry out decoding, control display unit and carry out numerical monitor;
Display unit is responsible for showing time figure corresponding to decoding unit;
Operation control unit and button with the use of, control system carries out the setting of time.
The beneficial effects of the utility model are: the utility model designs based on CPLD, its resource can meet the design requirement of electronic clock, this electronic clock have display " second ", " dividing ", " time " effect, 24 hours display modes, and there is the function of setup times, and the utility model is based on external crystal-controlled oscillation clocking, VHDL language is utilized to adopt the modules of the patten's design CPLD of digital circuit, thus the precision greatly improved when walking and accuracy.
Accompanying drawing explanation
Fig. 1 is control system block schematic illustration of the present utility model.
Embodiment
With reference to the accompanying drawings, by embodiment, the utility model is further illustrated:
Based on a digital display high-precision electronic clock for CPLD digital circuit, main hardware has:
CPLD: model is this chip of EPM7064STC100-10 of altera corp of U.S. MAX7000S series 100 pins is PLD based on product term structure, is applicable to realize combination complicated at a high speed, sequential logic.The device macroelement of EPM7064STC100-10 is 64, and I/O number of pins is 68, and its resource can meet the design requirement of electronic clock;
LED charactron divides three groups, often organizes 2, respectively corresponding second 60 system unit, point 60 system unit, time 24 system unit, with the display word time;
Button: by carrying out the setting of time by key control system.
Above-mentioned electronic clock, the built-in system of electronic clock comprises CPLD unit, crystal oscillator unit, frequency division/counting unit, second 60 system unit, point 60 system unit, time 24 system unit, decoding unit, display unit, operation control unit;
CPLD unit is the core control part of whole electronic clock, is responsible for the control of the combination complicated at a high speed of each unit of built-in system, sequential logic;
Crystal oscillator unit is the external clock of built-in system, as clock source for CPLD unit provides a reference time;
Frequency division/counting unit carries out frequency division and counting to crystal oscillator unit as clock source, produces the least count unit of clock signal as electronic clock of " 1 second ", for each unit;
Second 60 system unit take second as chronomere, carry out the counting of 60 systems, counting region 0 ~ 59, and to point 60 system unit carries when counting down to 60, then this unit returns 0 and again counts, and constantly circulates;
Point 60 system unit, to be divided into chronomere, carry out the counting of 60 systems, counting region 0 ~ 59, when counting down to 60 to time 24 system unit carries, this unit returns 0 and again counts, and constantly circulates;
Time 24 system unit while taking as chronomere, carry out the counting of 24 systems, counting region 0 ~ 23, when counting down to 24, this unit returns 0 and again counts, and constantly circulates;
Decoding unit to second 60 system unit, point 60 system unit and time 24 system unit counting export and carry out decoding, control display unit and carry out numerical monitor;
Display unit is responsible for showing time figure corresponding to decoding unit;
Operation control unit and button with the use of, control system carries out the setting of time.
Wherein arrange button: the setting carrying out time " second " by first time, " second " shows charactron flicker; The setting carrying out " minute " is selected, the flicker of " dividing " display charactron by second time; Select to carry out " hour " by third time to arrange, " time " show charactron flicker; Constantly switch between the setting of second time, minute, hour, until press " confirmation " key.
"+" button: setting time module being carried out to increment, when selecting to arrange " second " module, by once carrying out the operation adding 1, such as, when " second " showing charactron display numeral " 16 ", becomes " 17 " by a charactron, by that analogy; " divide " module with " time " module arrange with " second " module the same.
"-" button, and the effect of "+" button is similar, just carries out the operation subtracting 1.
" confirmation " button, determine the time of setting when pressing this button, electronic clock is started working.
Claims (2)
1., based on a digital display high-precision electronic clock for CPLD digital circuit, it is characterized in that the built-in system of electronic clock comprises CPLD unit, crystal oscillator unit, frequency division/counting unit, second 60 system unit, point 60 system unit, time 24 system unit, decoding unit, display unit, operation control unit;
CPLD unit is the core control part of whole electronic clock, is responsible for the control of the combination complicated at a high speed of each unit of built-in system, sequential logic;
Crystal oscillator unit is the external clock of built-in system, as clock source for CPLD unit provides a reference time;
Frequency division/counting unit carries out frequency division and counting to crystal oscillator unit as clock source, produces the least count unit of clock signal as electronic clock of " 1 second ", for each unit;
Second 60 system unit take second as chronomere, carry out the counting of 60 systems, counting region 0 ~ 59, and to point 60 system unit carries when counting down to 60, then this unit returns 0 and again counts, and constantly circulates;
Point 60 system unit, to be divided into chronomere, carry out the counting of 60 systems, counting region 0 ~ 59, when counting down to 60 to time 24 system unit carries, this unit returns 0 and again counts, and constantly circulates;
Time 24 system unit while taking as chronomere, carry out the counting of 24 systems, counting region 0 ~ 23, when counting down to 24, this unit returns 0 and again counts, and constantly circulates;
Decoding unit to second 60 system unit, point 60 system unit and time 24 system unit counting export and carry out decoding, control display unit and carry out numerical monitor;
Display unit is responsible for showing time figure corresponding to decoding unit;
Operation control unit and button with the use of, control system carries out the setting of time.
2. a kind of digital display high-precision electronic clock based on CPLD digital circuit according to claim 1, is characterized in that described electronic clock comprises CPLD, 1MHz crystal oscillator, LED charactron, button;
Wherein CPLD model is the EPM7064STC100-10 of MAX7000S series 100 pins;
LED charactron divides three groups, respectively corresponding second 60 system unit, point 60 system unit, time 24 system unit, with the display word time;
By carrying out the setting of time by key control system.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520023894.6U CN204389902U (en) | 2015-01-14 | 2015-01-14 | A kind of digital display high-precision electronic clock based on CPLD digital circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520023894.6U CN204389902U (en) | 2015-01-14 | 2015-01-14 | A kind of digital display high-precision electronic clock based on CPLD digital circuit |
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| CN204389902U true CN204389902U (en) | 2015-06-10 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104978243A (en) * | 2015-06-24 | 2015-10-14 | 浪潮电子信息产业股份有限公司 | Quick light path diagnosis method for server |
| CN107092182A (en) * | 2017-06-21 | 2017-08-25 | 福建中金在线信息科技有限公司 | Digital clock realizes equipment and digital clock implementation method |
-
2015
- 2015-01-14 CN CN201520023894.6U patent/CN204389902U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104978243A (en) * | 2015-06-24 | 2015-10-14 | 浪潮电子信息产业股份有限公司 | Quick light path diagnosis method for server |
| CN107092182A (en) * | 2017-06-21 | 2017-08-25 | 福建中金在线信息科技有限公司 | Digital clock realizes equipment and digital clock implementation method |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150610 Termination date: 20160114 |