CN204347454U

CN204347454U - A kind of device being measured the two paths of signals mistiming by FPGA internal delay time module

Info

Publication number: CN204347454U
Application number: CN201520004511.0U
Authority: CN
Inventors: 周柔刚; 周才健; 纪善昌
Original assignee: Hangzhou Collection Intelligence Science And Technology Ltd
Current assignee: Hangzhou Collection Intelligence Science And Technology Ltd
Priority date: 2015-01-06
Filing date: 2015-01-06
Publication date: 2015-05-20
Anticipated expiration: 2025-01-06

Abstract

The utility model comprises latch and some time delay modules, and described time delay module is connected successively, and the described input end of arbitrary time delay module is connected with the input end of latch.The utility model provides a kind of structure simple, and debugging is convenient, and error deviation is little, stable performance, a kind of device by the FPGA internal delay time module precision measurement two paths of signals mistiming that integrated level is high.

Description

A kind of device being measured the two paths of signals mistiming by FPGA internal delay time module

Technical field

The utility model relates to a kind of device being measured the two paths of signals mistiming by FPGA internal delay time module.

Background technology

Time measurement technology accurate between two signals has important effect in present field of engineering technology.Need within 100ps to the resolution of time measurement in ultraprecise displacement measurement, space flight, nuclear physics.High-resolution time measuring circuit is the core content of measuring system is also challenge maximum in design.The circuit realizing digital insertion is referred to as time-to-digit converter usually, and time figure conversion is the basic means of time measurement, and the signal carrying temporal information is converted to digital signal (digitizing) by it, thus realizes the measurement of temporal information.The direction realizing time-to-digit converter at present has following several: (1) precision capacitance electric discharge (time width transformation approach), and its realizing circuit is complicated, and price is high.(2) the TDC-GPX chip released of the ACAM company of Germany, this chip has the sampling precision of 8 passage 81ps, but price is high, needs complicated configuration before using, and the shortcoming such as when FPGA is combined integrated level is not high.(3) TDC module integration is inner at FPGA, time measurement is realized by Signal transmissions time delay between semiconductor, the method cost is minimum, integrated level is the highest, but design is difficulty quite, when needing when FPGA code compilation to generate chip internal logic gate, bottom carries out wires design, and signal drift is serious, has strict requirement to design process.

Utility model content

The utility model is for above-mentioned existing product Problems existing, and provide a kind of structure simple, debugging is convenient, and error deviation is little, stable performance, a kind of device being measured the two paths of signals mistiming by FPGA internal delay time module that integrated level is high.

The utility model comprises latch and some time delay modules, and described time delay module is connected successively, and the described input end of arbitrary time delay module is connected with the input end of latch.

After adopting above structure, the utility model compared with prior art, has the following advantages:

The utility model adopts multiple time delay module to connect successively, and when signal level in port one changes from low past height, this signal can toward next time delay module transmission after previous time delay module elapsed time time delay, and meanwhile, signal is also passed to a latch.When latch-control signal enters transition from low to high, in latch, data are latched, by calculating high level position number in latch, according to high level position number in m(storage) each delay unit delay time of * tap() value calculates mistiming between the step high level signal of signal input part input and latch-control signal.It is simple that the utility model has structure, and debugging is convenient, and error deviation is little, stable performance, and integrated level height waits many merits.

As preferably, what described time delay module adopted is Virtex and zynq Series FPGA internal delay time module.

The utility model can reach the resolution of maximum 52ps.Serial with internal delay time module according to the part FPGA that XILINX company releases, as Zynq series, Spartan series, Virtex series, called after IDELAY in function library, the internal delay time module performance of each family chip part model is as shown in table (1):

The time delay module performance of table (1) each family chip part model

Chip signal	Delay time	Delay value
			zynq	78 ps or 52 ps	0-31 tap
Virtex-4	75ps	0-64 tap
			Spartan-6	Uncertain	0-255 tap

Table (1)

In Spartan family chip, because its time delay module delay time is not what determine, adopt so family chip internal delay time module is not suitable for prolonging occasion in the time of precision.Virtex and zynq Series FPGA internal delay time module adopts feedback compensation technique, signal time delay is accurately exported according to the delay parameter of setting by the utility model, can adopt in chronometer time time delay occasion.

The utility model measuring accuracy is maximum can reach 52ps, compared to the method for m-digital conversion chip when carry chain insertion and employing, the utility model has error deviation between time slot little, stable performance, design is convenient, remarkable advantage such as grade with low cost, performance can meet nsec measuring accuracy demand in nuclear physics.

Accompanying drawing explanation

Fig. 1 is connection diagram of the present utility model.

Shown in figure 1, latch, 2, time delay module.

Embodiment

Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.

As shown in Figure 1, a kind of device by the FPGA internal delay time module measurement two paths of signals mistiming of the utility model comprises latch 1 and some time delay modules 2, described time delay module 2 is connected successively, and the input end of described arbitrary time delay module 2 is connected with the input end of latch 1.What described time delay module adopted is Virtex and zynq Series FPGA internal delay time module.

Set forth with regard to concrete implementation of the present utility model below, should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.Concrete implementation of the present utility model is: (a) generates several time delay module 2 in zynq or Virtex Series FPGA.B () be unified setting time delay module 2 delay value as requested.C time delay module 2 is connected by (), in module, DATAIN receives previous time delay module 2DATAOUT mouth, and wherein first time delay module 2DATAIN port receives signal input part 1.D () all time delay module 2DATAIN mouth receives the n position latch 1 of a FPGA inside by sequence.E, time () before m-digital conversion, signal input part 1 and latch 1 control end all set low level.F signal input part 1 is set high level by ().G latch 1 control signal is set high level by ().H () reads the data that latch 1 latches, according to high level position number in m(storage) each delay unit delay time of * tap() value calculate signal input part input high level signal and latch 1 control signal between mistiming, wherein m represents high level figure place in latch 1.Program minimum time resolution is Zynq series 52ps, Virtex series 75ps.

As Fig. 1, show time delay module 2 series connection figure of the present utility model and with latch 1 connection layout.As shown in fig. 1, when signal level in input port 1 changes from low past height, this signal can transmit toward next time delay module 2 after previous time delay module 2 elapsed time time delay, and meanwhile, signal is also passed to a latch 1.When latch 1 control signal enters transition from low to high, in latch 1, data are latched, by calculating high level position number in latch 1, according to high level position number in m(storage) each delay unit delay time of * tap() value calculate signal input part input high level signal and latch 1 control signal between mistiming, wherein m represents high level figure place in latch 1.

Below only just most preferred embodiment of the present utility model is described, but can not be interpreted as it is limitations on claims.The utility model is not limited only to above embodiment, and its concrete structure allows to change, and all various changes done in the protection domain of the utility model independent claims are all in protection domain of the present utility model.

Claims

1. measured the device of two paths of signals mistiming by FPGA internal delay time module for one kind, it is characterized in that: comprise latch (1) and some time delay modules (2), described time delay module (2) is connected successively, and the input end of described arbitrary time delay module (2) is connected with the input end of latch (1).

2. a kind of device being measured the two paths of signals mistiming by FPGA internal delay time module according to claim 1, be is characterized in that: what described time delay module (2) adopted is Virtex and zynq Series FPGA internal delay time module.