CN204271610U - Multistage gate circuit current foldback circuit - Google Patents
Multistage gate circuit current foldback circuit Download PDFInfo
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- CN204271610U CN204271610U CN201420587307.1U CN201420587307U CN204271610U CN 204271610 U CN204271610 U CN 204271610U CN 201420587307 U CN201420587307 U CN 201420587307U CN 204271610 U CN204271610 U CN 204271610U
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Abstract
The utility model discloses multistage gate circuit current foldback circuit, comprise charging indication, adjustable constant-flow circuit, adjustable voltage stabilizing circuit, charging indication comprises PNP type triode Q2, resistance R2, resistance R1, resistance R4, LED 1, adjustable voltage stabilizing circuit comprises NPN type triode Q1, resistance R3, variable resistor R5, voltage stabilizing didoe D1, adjustable constant-flow circuit comprises PNP type triode Q3, resistance R7, variable resistor R6, due to the dividing potential drop effect of resistance R2, make the E pole of PNP type triode Q2 different with the voltage of B pole, coating-forming voltage is poor, PNP type triode Q2 is in conducting state, along with the propelling in charging interval, rise gradually along with by charged lithium cells voltage, charging current will reduce gradually, pressure drop after battery is full of on resistance R2 constantly reduces, finally make PNP type triode Q2 by.A kind of simple and effective time-dependent current charging system is first quick and back slow provided.
Description
Technical field
The utility model relates to overcurrent protection, specifically multistage gate circuit current foldback circuit.
Background technology
IGBT drive circuit comprises IGBT (Insulated Gate Bipolar Transistor), IGBT and insulated gate bipolar transistor, the compound full-control type voltage driven type power semiconductor be made up of BJT (double pole triode) and MOS (insulating gate type field effect tube), has the advantage of the high input impedance of MOSFET and low conduction voltage drop two aspect of GTR concurrently.
IGBT drive circuit combines the advantage of above two kinds of devices, and driving power is little and saturation pressure reduces.Being applicable to very much being applied to direct voltage is that 600V and above converter system are as fields such as alternating current machine, frequency converter, Switching Power Supply, lighting circuit, Traction Drives.
And often need to process to protect IGBT drive circuit to the control signal of IGBT drive circuit in the application of IGBT drive circuit, place the overcurrent of input control signal and burn IGBT drive circuit.
Existing safeguard measure is: the size of the short circuit current of IGBT is relevant with grid voltage, in actual applications, can reduce the time that short circuit current is born in short circuit current or prolongation by reducing grid voltage.Prior art arranges triode in the G pole of IGBT; the conducting of triode and cut-off is utilized to form safeguard measure; but this safeguard measure can not reach accurate control that is very efficient and reaction at a high speed, and when often triode does not also reach cut-off state, IGBT has been burnt.
Utility model content
The purpose of this utility model is to provide a kind of multistage gate circuit current foldback circuit that is stable, that react at a high speed.
The purpose of this utility model is achieved through the following technical solutions: multistage gate circuit current foldback circuit, comprise integrated phase lock loop circuit J1, the IN1 pin of integrated phase lock loop circuit J1 connects power supply, the IN2 pin ground connection of integrated phase lock loop circuit J1, the TRES pin serial connection resistance R2 of integrated phase lock loop circuit J1, the V+ pin of integrated phase lock loop circuit J1 is linked into after potentiometer VR, the VCO pin of integrated phase lock loop circuit J1 is connected with ground capacity C2, electric capacity C2 is connected with between the V-pin of integrated phase lock loop circuit and TCAP pin, the VIN pin of integrated phase lock loop circuit J1 and the output signal of VOUT pin are input to inverter F1 simultaneously, the output of inverter F1 is connected to the CLK end of d type flip flop D1, also comprise secondary reverser F2 and secondary inverter F3, one-level and door M1, one-level and door M2, wherein, the D end of d type flip flop D1 is connected with the input of secondary inverter F3, the D end of d type flip flop D1 is also connected with the input of one-level with door M1 simultaneously, the output of secondary inverter F3 is connected with the input of one-level with door M2, the D end of d type flip flop D1 is also with d type flip flop D1's
end connects, with the input of secondary reverser F2 while that the Q of d type flip flop D1 holding, one-level is connected with the input of door M2, the output of secondary reverser F2 is connected with the input of one-level with door M1, the output of one-level and door M1 is connected with the input of secondary and door M3, the output of one-level and door M2 is connected with the input of secondary and door M4, the input of the input of secondary and door M3 and secondary and door M4 is also connected with command end EN simultaneously, the output of secondary and door M3 is connected with final stage inverter U1 and final stage inverter U2, the output of secondary and door M4 is connected with final stage inverter U3 and final stage inverter U4, final stage inverter U1 and final stage inverter U2, final stage inverter U3 and final stage inverter U4 exports a road signal all separately.
The operation principle of foregoing circuit is: it is OUT1, OUT2, OUT3, OUT4 respectively that final stage inverter U1 and final stage inverter U2, final stage inverter U3 and final stage inverter U4 export a road signal all separately, integrated phase lock loop circuit J1: its function is to provide the square-wave signal of frequency stabilization, can change the output frequency of integrated phase lock loop circuit J1 by regulator potentiometer VR.The output signal of integrated phase lock loop circuit J1 is input to the clock end (CLK end) of d type flip flop D1 after the anti-phase process of inverter F1, the output signal of d type flip flop D1 is added to the input of one-level and door M1 and one-level and door M2 after the Shape correction of secondary reverser F2 and secondary inverter F3, signal outputs to final stage inverter U1 and final stage inverter U2, final stage inverter U3 and final stage inverter U4 through secondary and door M3 and secondary and door M4 again, can obtain the complementary square-wave signals in 2 tunnels from output OUT1, OUT2, OUT3, OUT4.Wherein OUT1, OUT2 are one group, and OUT3, OUT4 are the input that another group is added to IGBT drive circuit respectively.From design, this circuit ensure that two paths of signals is all under any circumstance complementary, avoiding problems the generation that IGBT bridge leads directly to phenomenon, ensure that the fail safe of IGBT module work.Command end EN is that IGBT controls enable signal, when EN=1 then has control signal to export, when EN=0 does not then export, its objective is and has carried out overcurrent protection to IGBT drive circuit.
Preferably, integrated phase lock loop circuit J1 adopts model to be the integrated circuit of LM565.
Preferably, inverter F1, secondary reverser F2 and secondary inverter F3 all adopt model to be the schmitt inverter of 74HC14.
Preferably, one-level and door M1, one-level and door M2, secondary and door M3, secondary and door M4 all adopt model be 74HC08 with door device.
Preferably, final stage inverter U1 and final stage inverter U2, final stage inverter U3 and final stage inverter U4 all adopt model to be the inverter of 74LS06.
Preferably, also comprise resistance R3, resistance R3 is connected to the input end of inverter F1, be connected with the VIN pin of integrated phase lock loop circuit J1 and VOUT pin while of resistance R3, the input of secondary reverser F2 is held with the Q of d type flip flop D1 by resistance R4 and is connected, and the input of secondary inverter F3 is by resistance R5's and d type flip flop D1
end connects.
The utility model has the advantage of: structure is simple, and cost is low, simple and quick, the multistage gate circuit current foldback circuit stablized, react at a high speed can be realized fast, easily.
Accompanying drawing explanation
Fig. 1 is circuit diagram of the present utility model.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the utility model is described in further detail, but execution mode of the present utility model is not limited thereto.
Embodiment 1:
As shown in Figure 1.
Multistage gate circuit current foldback circuit, comprise integrated phase lock loop circuit J1, the IN1 pin of integrated phase lock loop circuit J1 connects the power supply of positive 5V, the power supply of positive 5V enters IN1 pin for integrated phase lock loop circuit J1 after the dividing potential drop of resistance R1 provides power supply, the IN2 pin ground connection of integrated phase lock loop circuit J1, the TRES pin serial connection resistance R2 of integrated phase lock loop circuit J1, the V+ pin of integrated phase lock loop circuit J1 is linked into after potentiometer VR, the VCO pin of integrated phase lock loop circuit J1 is connected with ground capacity C2, electric capacity C2 is connected with between the V-pin of integrated phase lock loop circuit and TCAP pin, the VIN pin of integrated phase lock loop circuit J1 and the output signal of VOUT pin are input to inverter F1 simultaneously, the output of inverter F1 is connected to the CLK end of d type flip flop D1, also comprise secondary reverser F2 and secondary inverter F3, one-level and door M1, one-level and door M2, wherein, the D end of d type flip flop D1 is connected with the input of secondary inverter F3, the D end of d type flip flop D1 is also connected with the input of one-level with door M1 simultaneously, the output of secondary inverter F3 is connected with the input of one-level with door M2, the D end of d type flip flop D1 is also with d type flip flop D1's
end connects, with the input of secondary reverser F2 while that the Q of d type flip flop D1 holding, one-level is connected with the input of door M2, the output of secondary reverser F2 is connected with the input of one-level with door M1, the output of one-level and door M1 is connected with the input of secondary and door M3, the output of one-level and door M2 is connected with the input of secondary and door M4, the input of the input of secondary and door M3 and secondary and door M4 is also connected with command end EN simultaneously, the output of secondary and door M3 is connected with final stage inverter U1 and final stage inverter U2, the output of secondary and door M4 is connected with final stage inverter U3 and final stage inverter U4, final stage inverter U1 and final stage inverter U2, final stage inverter U3 and final stage inverter U4 exports a road signal all separately.
The operation principle of foregoing circuit is: it is OUT1, OUT2, OUT3, OUT4 respectively that final stage inverter U1 and final stage inverter U2, final stage inverter U3 and final stage inverter U4 export a road signal all separately, integrated phase lock loop circuit J1: its function is to provide the square-wave signal of frequency stabilization, can change the output frequency of integrated phase lock loop circuit J1 by regulator potentiometer VR.The output signal of integrated phase lock loop circuit J1 is input to the clock end (CLK end) of d type flip flop D1 after the anti-phase process of inverter F1, the output signal of d type flip flop D1 is added to the input of one-level and door M1 and one-level and door M2 after the Shape correction of secondary reverser F2 and secondary inverter F3, signal outputs to final stage inverter U1 and final stage inverter U2, final stage inverter U3 and final stage inverter U4 through secondary and door M3 and secondary and door M4 again, can obtain the complementary square-wave signals in 2 tunnels from output OUT1, OUT2, OUT3, OUT4.Wherein OUT1, OUT2 are one group, and OUT3, OUT4 are the input that another group is added to IGBT drive circuit respectively.From design, this circuit ensure that two paths of signals is all under any circumstance complementary, avoiding problems the generation that IGBT bridge leads directly to phenomenon, ensure that the fail safe of IGBT module work.Command end EN is that IGBT controls enable signal, when EN=1 then has control signal to export, when EN=0 does not then export, its objective is and has carried out overcurrent protection to IGBT drive circuit.
Preferably, integrated phase lock loop circuit J1 adopts model to be the integrated circuit of LM565.
Preferably, inverter F1, secondary reverser F2 and secondary inverter F3 all adopt model to be the schmitt inverter of 74HC14.
Preferably, one-level and door M1, one-level and door M2, secondary and door M3, secondary and door M4 all adopt model be 74HC08 with door device.
Preferably, final stage inverter U1 and final stage inverter U2, final stage inverter U3 and final stage inverter U4 all adopt model to be the inverter of 74LS06.
Preferably, also comprise resistance R3, resistance R3 is connected to the input end of inverter F1, be connected with the VIN pin of integrated phase lock loop circuit J1 and VOUT pin while of resistance R3, the input of secondary reverser F2 is held with the Q of d type flip flop D1 by resistance R4 and is connected, and the input of secondary inverter F3 is by resistance R5's and d type flip flop D1
end connects.
The utility model has the advantage of: structure is simple, and cost is low, simple and quick, the multistage gate circuit current foldback circuit stablized, react at a high speed can be realized fast, easily.
Claims (6)
1. multistage gate circuit current foldback circuit, it is characterized in that: comprise integrated phase lock loop circuit J1, the IN1 pin of integrated phase lock loop circuit J1 connects power supply, the IN2 pin ground connection of integrated phase lock loop circuit J1, the TRES pin serial connection resistance R2 of integrated phase lock loop circuit J1, the V+ pin of integrated phase lock loop circuit J1 is linked into after potentiometer VR, the VCO pin of integrated phase lock loop circuit J1 is connected with ground capacity C2, electric capacity C2 is connected with between the V-pin of integrated phase lock loop circuit and TCAP pin, the VIN pin of integrated phase lock loop circuit J1 and the output signal of VOUT pin are input to inverter F1 simultaneously, the output of inverter F1 is connected to the CLK end of d type flip flop D1, also comprise secondary reverser F2 and secondary inverter F3, one-level and door M1, one-level and door M2, wherein, the D end of d type flip flop D1 is connected with the input of secondary inverter F3, the D end of d type flip flop D1 is also connected with the input of one-level with door M1 simultaneously, the output of secondary inverter F3 is connected with the input of one-level with door M2, the D end of d type flip flop D1 is also with d type flip flop D1's
end connects, with the input of secondary reverser F2 while that the Q of d type flip flop D1 holding, one-level is connected with the input of door M2, the output of secondary reverser F2 is connected with the input of one-level with door M1, the output of one-level and door M1 is connected with the input of secondary and door M3, the output of one-level and door M2 is connected with the input of secondary and door M4, the input of the input of secondary and door M3 and secondary and door M4 is also connected with command end EN simultaneously, the output of secondary and door M3 is connected with final stage inverter U1 and final stage inverter U2, the output of secondary and door M4 is connected with final stage inverter U3 and final stage inverter U4, final stage inverter U1 and final stage inverter U2, final stage inverter U3 and final stage inverter U4 exports a road signal all separately.
2. multistage gate circuit current foldback circuit according to claim 1, is characterized in that: integrated phase lock loop circuit J1 adopts model to be the integrated circuit of LM565.
3. multistage gate circuit current foldback circuit according to claim 1, is characterized in that: inverter F1, secondary reverser F2 and secondary inverter F3 all adopt model to be the schmitt inverter of 74HC14.
4. multistage gate circuit current foldback circuit according to claim 1, is characterized in that: one-level and door M1, one-level and door M2, secondary and door M3, secondary and door M4 all adopt model be 74HC08 with door device.
5. multistage gate circuit current foldback circuit according to claim 1, is characterized in that: final stage inverter U1 and final stage inverter U2, final stage inverter U3 and final stage inverter U4 all adopt model to be the inverter of 74LS06.
6. multistage gate circuit current foldback circuit according to claim 1; it is characterized in that: also comprise resistance R3; resistance R3 is connected to the input end of inverter F1; be connected with the VIN pin of integrated phase lock loop circuit J1 and VOUT pin while of resistance R3; the input of secondary reverser F2 is held with the Q of d type flip flop D1 by resistance R4 and is connected, and the input of secondary inverter F3 is by resistance R5's and d type flip flop D1
end connects.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420587307.1U CN204271610U (en) | 2014-10-13 | 2014-10-13 | Multistage gate circuit current foldback circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420587307.1U CN204271610U (en) | 2014-10-13 | 2014-10-13 | Multistage gate circuit current foldback circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204271610U true CN204271610U (en) | 2015-04-15 |
Family
ID=52806455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420587307.1U Expired - Fee Related CN204271610U (en) | 2014-10-13 | 2014-10-13 | Multistage gate circuit current foldback circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204271610U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104269817A (en) * | 2014-10-13 | 2015-01-07 | 成都锐奕信息技术有限公司 | Power protection circuit based on gate circuit |
| CN110445498A (en) * | 2019-07-31 | 2019-11-12 | 西安天和防务技术股份有限公司 | Current potential holding circuit and current foldback circuit |
-
2014
- 2014-10-13 CN CN201420587307.1U patent/CN204271610U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104269817A (en) * | 2014-10-13 | 2015-01-07 | 成都锐奕信息技术有限公司 | Power protection circuit based on gate circuit |
| CN104269817B (en) * | 2014-10-13 | 2017-09-08 | 成都锐奕信息技术有限公司 | Power protecting circuit based on gate circuit |
| CN110445498A (en) * | 2019-07-31 | 2019-11-12 | 西安天和防务技术股份有限公司 | Current potential holding circuit and current foldback circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150415 Termination date: 20151013 |
|
| EXPY | Termination of patent right or utility model |