CN204271065U - Wafer sort sample - Google Patents
Wafer sort sample Download PDFInfo
- Publication number
- CN204271065U CN204271065U CN201420827513.5U CN201420827513U CN204271065U CN 204271065 U CN204271065 U CN 204271065U CN 201420827513 U CN201420827513 U CN 201420827513U CN 204271065 U CN204271065 U CN 204271065U
- Authority
- CN
- China
- Prior art keywords
- wafer
- straight line
- measured
- adhesive
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Adhesives Or Adhesive Processes (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Sampling And Sample Adjustment (AREA)
Abstract
The utility model discloses a kind of wafer sort sample, comprise: substrate and the wafer to be measured be positioned on described substrate, the upper surface of described substrate is provided with water conservancy diversion region, diversion groove is provided with in described water conservancy diversion region, described wafer to be measured is fixed on the upper surface of described substrate by adhesive, described wafer to be measured covers the central area in described water conservancy diversion region.When described wafer to be measured being fixed on the upper surface of described substrate by described adhesive, unnecessary described adhesive flows out along described diversion groove, avoids unnecessary described adhesive to stain the upper surface of described wafer to be measured; And described adhesive is through the water conservancy diversion of described diversion groove, described adhesive is filled in the edge of the lower surface of described wafer to be measured better, makes described wafer to be measured not easily broken.
Description
Technical field
The utility model relates to reliability (Reliability) field in semiconductor manufacturing industry, particularly relates to a kind of wafer sort sample.
Background technology
The microminiaturization of information system, multifunction and intellectuality are the targets that people constantly pursue.The development of semiconductor integrated circuit technology is the main drive amount of these changes.The development of the technology such as system-level wafer, system in package makes the function of IC device be an unprecedented increase.Particularly because the use of the technology such as wafer stacking and 3D encapsulate makes some electronics field show the development trend surmounting Moore's Law.The huge advantage that industry more and more recognizes that wafer stacking and 3D encapsulation technology realize at the system level function of device, have in memory capacity increase etc.
Under the constant trend even decreased of encapsulating structure integral thickness, in wafer stacking, the thickness of each layer wafer used just inevitably needs thinning, but, after wafer is thinned, can become very fragile.Therefore, when the scanning electron microscopy (SEM) preparing ultra thin wafer tests sample, prevent wafer breakage from being very important.
In the prior art, the preparation method of ultra thin wafer test sample is: be pasted onto on slightly large thick substrate by ultra-thin sample by adhesive, process afterwards again.But the method has following shortcoming:
1. the edge being positioned at ultra thin wafer is easily stain by adhesive;
2. for the ultra thin wafer of photosensitive class, the edge cross-section due to wafer is inverted trapezoidal, therefore in the preparation process of test sample, the edge of wafer very easily ruptures;
3. wafer sort sample image quality is in the secure execution mode (sem poor.
Utility model content
The purpose of this utility model is, provides a kind of wafer sort sample, and the wafer of this wafer sort sample is not easily broken and not easily stain, and the image quality of this wafer sort sample is high.
For solving the problems of the technologies described above, the utility model provides a kind of wafer sort sample, comprise: substrate and the wafer to be measured be positioned on described substrate, the upper surface of described substrate is provided with water conservancy diversion region, diversion groove is provided with in described water conservancy diversion region, described wafer to be measured is fixed on the upper surface of described substrate by adhesive, described wafer to be measured covers the central area in described water conservancy diversion region.
Optionally, described water conservancy diversion region at least comprises multiple the first straight line diversion groove in first direction arrangement.
Optionally, the spacing between adjacent described first straight line diversion groove is 1 μm ~ 5 μm.
Optionally, the groove width of described first straight line diversion groove is 0.5 μm ~ 2 μm.
Optionally, described water conservancy diversion region also comprise multiple second direction arrangement the second straight line diversion groove, described first direction and second direction perpendicular.
Optionally, the spacing between multiple described second straight line diversion groove is 1 μm ~ 5 μm.
Optionally, the groove width of described second straight line diversion groove is 0.5 μm ~ 2 μm.
Optionally, described water conservancy diversion region comprises four crossing straight line diversion grooves, and described straight line diversion groove intersects for " rice " font, and described wafer to be measured covers the intersection point of four described straight line diversion grooves.
Optionally, the groove width of described straight line diversion groove is 0.5 μm ~ 2 μm.
Optionally, described adhesive is hot setting adhesive.
Optionally, described adhesive is conducting resinl.
Optionally, described substrate is silicon substrate, glass substrate or ceramic substrate.
Compared with prior art, the wafer sort sample that the utility model provides has the following advantages:
In the wafer sort sample that the utility model provides, the upper surface of described substrate is provided with water conservancy diversion region, diversion groove is provided with in described water conservancy diversion region, described wafer to be measured covers the central area in described water conservancy diversion region, when described wafer to be measured being fixed on the upper surface of described substrate by described adhesive, unnecessary described adhesive flows out along described diversion groove, avoids unnecessary described adhesive to stain the upper surface of described wafer to be measured; And described adhesive is through the water conservancy diversion of described diversion groove, described adhesive is filled in the edge of the lower surface of described wafer to be measured better, makes described wafer to be measured not easily broken.
Further, the adhesive of described wafer sort sample is conducting resinl, when described adhesive is derived by described diversion groove, described adhesive forms conductive path in described diversion groove, described wafer sort sample is conveniently connected with SEM sample stage, avoid electric charge to gather at described wafer to be measured, improve the image quality of described wafer sort sample.
Accompanying drawing explanation
Fig. 1 is the vertical view of wafer sort sample in the utility model first embodiment;
Fig. 2 is the profile of Fig. 1 along cutting line A-A ';
Fig. 3 is the vertical view of substrate in the utility model first embodiment;
Fig. 4 is schematic diagram when wafer sort sample is positioned over SEM sample stage in the utility model first embodiment;
Fig. 5 is the vertical view of wafer sort sample in the utility model second embodiment.
Embodiment
Below in conjunction with schematic diagram, wafer sort sample of the present utility model is described in more detail, which show preferred embodiment of the present utility model, should be appreciated that those skilled in the art can revise the utility model described here, and still realize advantageous effects of the present utility model.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as to restriction of the present utility model.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the utility model chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the utility model is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantage of the present utility model and feature will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, aid illustration the utility model embodiment lucidly.
Core concept of the present utility model is, a kind of wafer sort sample is provided, described wafer sort sample comprises: substrate and the wafer to be measured be positioned on described substrate, the upper surface of described substrate is provided with water conservancy diversion region, diversion groove is provided with in described water conservancy diversion region, described wafer to be measured is fixed on the upper surface of described substrate by adhesive, described wafer to be measured covers the central area in described water conservancy diversion region.When described wafer to be measured being fixed on the upper surface of described substrate by described adhesive, unnecessary described adhesive flows out along described diversion groove, avoids unnecessary described adhesive to stain the upper surface of described wafer to be measured; And described adhesive is through the water conservancy diversion of described diversion groove, described adhesive is filled in the edge of the lower surface of described wafer to be measured better, makes described wafer to be measured not easily broken.
Preferably, the adhesive of described wafer sort sample is conducting resinl, when described adhesive is derived by described diversion groove, described adhesive forms conductive path in described diversion groove, described wafer sort sample is conveniently connected with SEM sample stage, avoid electric charge to gather at described wafer to be measured, improve the image quality of described wafer sort sample.
Below enumerate several embodiments of wafer sort sample in described integrated circuit, to clearly demonstrate content of the present utility model, will be clear that, content of the present utility model is not restricted to following examples, and other improvement by the routine techniques means of those of ordinary skill in the art are also within thought range of the present utility model.
First embodiment
Below please refer to Fig. 1-Fig. 4 to illustrate the wafer sort sample in the utility model first embodiment, wherein, Fig. 1 is the vertical view of wafer sort sample in the utility model first embodiment; Fig. 2 is the profile of Fig. 1 along cutting line A-A '; Fig. 3 is the vertical view of substrate in the utility model first embodiment; Fig. 4 is schematic diagram when wafer sort sample is positioned over SEM sample stage in the utility model first embodiment.
As shown in Figure 1, described wafer sort sample 1 comprises substrate 100 and is positioned at the wafer to be measured 120 on described substrate 100, and described wafer 120 to be measured is fixed on the upper surface of described substrate 100 by adhesive 140.In the present embodiment, described wafer 120 to be measured is ultra thin wafer (typically referring to the wafer that thickness is less than or equal to 100 μm), and the thickness of described substrate 100 is greater than the thickness of described wafer to be measured 120.Preferably, described substrate 100 is silicon substrate, glass substrate or ceramic substrate etc., and silicon substrate, glass substrate or ceramic substrate have high temperature resistant and corrosion resistance preferably, can improve the reliability of described wafer sort sample 1.
As shown in Figure 3, the upper surface of described substrate 100 is provided with water conservancy diversion region 110, and described water conservancy diversion region 110 can cover the upper surface of whole described substrate 100, and described water conservancy diversion region 110 also only can be positioned at the upper surface of the described substrate 100 of part.Be provided with diversion groove 130 in described water conservancy diversion region 110, described diversion groove 130 is for carrying out water conservancy diversion to described adhesive 140.
In the present embodiment, described water conservancy diversion region 110 at least comprises multiple the first straight line diversion groove 131 arranged at first direction (X-direction).3 described first straight line diversion grooves 131 shown in Figure 3, but, described diversion groove 130 is not limited to comprise 3 described first straight line diversion grooves 131, and described diversion groove 130 can also comprise the described first straight line diversion groove 131 of 2,4,5,6 or more.Spacing W1 between adjacent described first straight line diversion groove 131 is preferably 1 μm ~ 5 μm, such as 2 μm, 3 μm, 4 μm etc., when the number of described first straight line diversion groove 131 is more, spacing W1 between adjacent described first straight line diversion groove 131 is less, and water conservancy diversion effect is better.The groove width D1 of described first straight line diversion groove 131 is preferably 0.5 μm ~ 2 μm, such as 1 μm, 1.5 μm etc., good water conservancy diversion effect can be reached.
Preferably, described water conservancy diversion region 110 also comprises multiple the second straight line diversion groove 132 arranged in second direction (Y-direction), described first direction (X-direction) is perpendicular with second direction (Y-direction), thus make described adhesive 140 all obtain water conservancy diversion at described first direction (X-direction) and second direction (Y-direction), improve the effect of water conservancy diversion.3 described second straight line diversion grooves 132 shown in Figure 3, but, described diversion groove 130 is not limited to comprise 3 described second straight line diversion grooves 132, and described diversion groove 130 can also comprise the described second straight line diversion groove 132 of 2,4,5,6 or more.Spacing W2 between adjacent described second straight line diversion groove 132 is preferably 1 μm ~ 5 μm, such as 2 μm, 3 μm, 4 μm etc., when the number of described second straight line diversion groove 132 is more, spacing W2 between adjacent described second straight line diversion groove 132 is less, and water conservancy diversion effect is better.The groove width D2 of described second straight line diversion groove 132 is preferably 0.5 μm ~ 2 μm, such as 1 μm, 1.5 μm etc., good water conservancy diversion effect can be reached.
As shown in Figure 1, described wafer to be measured 120 covers the central area in described water conservancy diversion region 110, thus make the fringe region of described wafer to be measured 120 all have described diversion groove to pass through, in the present embodiment, four limits of described wafer to be measured 120 all have described first straight line diversion groove 131 or described second straight line diversion groove 132.When described wafer 120 to be measured being fixed on the upper surface of described substrate 100 by described adhesive 140, unnecessary described adhesive 140 flows out along described diversion groove (described first straight line diversion groove 131 or described second straight line diversion groove 132), avoids unnecessary described adhesive 140 to stain the upper surface of described wafer to be measured 120; And, described adhesive 120 is through the water conservancy diversion of described diversion groove (described first straight line diversion groove 131 or described second straight line diversion groove 132), described adhesive 140 is filled in the edge of the lower surface of described wafer to be measured 120 better, makes described wafer to be measured 120 not easily broken.
In preferred version, described adhesive 140 is hot setting adhesive, and hot setting adhesive has high temperature resistant, corrosion resistant feature, can improve the reliability of described wafer sort sample 1.In the present embodiment, the adhesive 140 of described wafer sort sample 1 is conducting resinl, the paraffin of such as conductive doped particle or the resin of conductive doped particle, etc.When described adhesive 140 is derived by described diversion groove (described first straight line diversion groove 131 or described second straight line diversion groove 132), described adhesive 140 forms conductive path in described diversion groove (described first straight line diversion groove 131 or described second straight line diversion groove 132), as shown in Figure 4, when described wafer sort sample 1 being fixed to SEM sample stage 20 by copper adhesive tape 10, the described adhesive 140 be exported described in described copper adhesive tape 10 connects, described copper adhesive tape 10 also connects described SEM sample stage 20, never described wafer sort sample 1 is made conveniently to be connected with SEM sample stage point, electric charge is avoided to gather at described wafer 120 to be measured, improve the image quality of described wafer sort sample 1.
Second embodiment
Refer to Fig. 5, Fig. 5 is the vertical view of wafer sort sample in the utility model second embodiment.In Figure 5, reference number represents the parts that the statement identical with Fig. 1-Fig. 4 is identical with the first execution mode.The wafer sort sample 2 of described second embodiment is substantially identical with the wafer sort sample 1 of described first embodiment, its difference is: described water conservancy diversion region 110 comprises four crossing straight line diversion grooves 231,232,233,234, four described straight line diversion grooves 231,232,233,234 intersect for " rice " font, described wafer to be measured 120 covers the intersection point O of four described straight line diversion grooves 231,232,233,234, makes described adhesive 140 can obtain good water conservancy diversion.The groove width D3 of described straight line diversion groove 231,232,233,234 is preferably 0.5 μm ~ 2 μm, such as 1 μm, 1.5 μm etc., good water conservancy diversion effect can be reached.
In the present embodiment, when described wafer 120 to be measured being fixed on the upper surface of described substrate 100 by described adhesive 140, unnecessary described adhesive 140 flows out along described diversion groove (described straight line diversion groove 231,232,233,234), avoids unnecessary described adhesive 140 to stain the upper surface of described wafer to be measured 120; And, described adhesive 120 is through the water conservancy diversion of described diversion groove (described straight line diversion groove 231,232,233,234), described adhesive 140 is filled in the edge of the lower surface of described wafer to be measured 120 better, makes described wafer to be measured 120 not easily broken.
Preferred embodiment of the present utility model is described above, but, in other embodiment of the present utility model, described diversion groove can also be other shape, such as shaped form or fold-line-shaped etc., as long as described wafer to be measured is arranged on described diversion groove, the lower surface of unnecessary described adhesive from described wafer to be measured can be derived, all within thought range of the present utility model by described diversion groove.
In sum, the utility model provides a kind of wafer sort sample, described wafer sort sample comprises: substrate and the wafer to be measured be positioned on described substrate, the upper surface of described substrate is provided with water conservancy diversion region, diversion groove is provided with in described water conservancy diversion region, described wafer to be measured is fixed on the upper surface of described substrate by adhesive, described wafer to be measured covers the central area in described water conservancy diversion region.Compared with prior art, the wafer sort sample that the utility model provides has the following advantages: when described wafer to be measured being fixed on the upper surface of described substrate by described adhesive, unnecessary described adhesive flows out along described diversion groove, avoids unnecessary described adhesive to stain the upper surface of described wafer to be measured; And described adhesive is through the water conservancy diversion of described diversion groove, described adhesive is filled in the edge of the lower surface of described wafer to be measured better, makes described wafer to be measured not easily broken.
Further, the adhesive of described wafer sort sample is conducting resinl, when described adhesive is derived by described diversion groove, described adhesive forms conductive path in described diversion groove, described wafer sort sample is conveniently connected with SEM sample stage, avoid electric charge to gather at described wafer to be measured, improve the image quality of described wafer sort sample.
Obviously, those skilled in the art can carry out various change and modification to the utility model and not depart from spirit and scope of the present utility model.Like this, if these amendments of the present utility model and modification belong within the scope of the utility model claim and equivalent technologies thereof, then the utility model is also intended to comprise these change and modification.
Claims (12)
1. a wafer sort sample, it is characterized in that, comprise: substrate and the wafer to be measured be positioned on described substrate, the upper surface of described substrate is provided with water conservancy diversion region, diversion groove is provided with in described water conservancy diversion region, described wafer to be measured is fixed on the upper surface of described substrate by adhesive, described wafer to be measured covers the central area in described water conservancy diversion region.
2. wafer sort sample as claimed in claim 1, is characterized in that, described water conservancy diversion region at least comprises multiple the first straight line diversion groove in first direction arrangement.
3. wafer sort sample as claimed in claim 2, it is characterized in that, the spacing between adjacent described first straight line diversion groove is 1 μm ~ 5 μm.
4. wafer sort sample as claimed in claim 2, it is characterized in that, the groove width of described first straight line diversion groove is 0.5 μm ~ 2 μm.
5., as the wafer sort sample in claim 2 to 4 as described in any one, it is characterized in that, described water conservancy diversion region also comprise multiple second direction arrangement the second straight line diversion groove, described first direction and second direction perpendicular.
6. wafer sort sample as claimed in claim 5, it is characterized in that, the spacing between multiple described second straight line diversion groove is 1 μm ~ 5 μm.
7. wafer sort sample as claimed in claim 5, it is characterized in that, the groove width of described second straight line diversion groove is 0.5 μm ~ 2 μm.
8. wafer sort sample as claimed in claim 1, it is characterized in that, described water conservancy diversion region comprises four crossing straight line diversion grooves, and described straight line diversion groove intersects for " rice " font, and described wafer to be measured covers the intersection point of four described straight line diversion grooves.
9. wafer sort sample as claimed in claim 8, it is characterized in that, the groove width of described straight line diversion groove is 0.5 μm ~ 2 μm.
10. wafer sort sample as claimed in claim 1, it is characterized in that, described adhesive is hot setting adhesive.
11. wafer sort samples as described in claim 1 or 10, it is characterized in that, described adhesive is conducting resinl.
12. wafer sort samples as claimed in claim 1, it is characterized in that, described substrate is silicon substrate, glass substrate or ceramic substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420827513.5U CN204271065U (en) | 2014-12-23 | 2014-12-23 | Wafer sort sample |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420827513.5U CN204271065U (en) | 2014-12-23 | 2014-12-23 | Wafer sort sample |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204271065U true CN204271065U (en) | 2015-04-15 |
Family
ID=52805914
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420827513.5U Active CN204271065U (en) | 2014-12-23 | 2014-12-23 | Wafer sort sample |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204271065U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106971952A (en) * | 2016-01-13 | 2017-07-21 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor device failure analysis sample and preparation method thereof, failure analysis method |
| CN111277102A (en) * | 2018-12-04 | 2020-06-12 | 日本电产三协株式会社 | Actuator |
-
2014
- 2014-12-23 CN CN201420827513.5U patent/CN204271065U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106971952A (en) * | 2016-01-13 | 2017-07-21 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor device failure analysis sample and preparation method thereof, failure analysis method |
| CN106971952B (en) * | 2016-01-13 | 2019-08-27 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor device failure analyzes sample and preparation method thereof, failure analysis method |
| CN111277102A (en) * | 2018-12-04 | 2020-06-12 | 日本电产三协株式会社 | Actuator |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW452963B (en) | Semiconductor device having an alignment mark formed by the same material with a metal post | |
| CN101275895B (en) | Sample platform system for in-situ measuring Na electronic device property in transmission electron microscope | |
| CN102937695B (en) | Silicon through-hole ultrathin wafer testing structure and testing method | |
| US12057364B2 (en) | Package formation methods including coupling a molded routing layer to an integrated routing layer | |
| CN117794255A (en) | Multi-chip package | |
| CN204271065U (en) | Wafer sort sample | |
| CN104465315A (en) | Chip separation method for 3D stacked chip encapsulator | |
| CN104205316B (en) | The manufacture method of semiconductor device and manufacture device | |
| CN106356312A (en) | Testing and failure analysis method for packaged chip | |
| CN106449465A (en) | Method for testing single bit on memory chip | |
| CN105810593A (en) | Fan-out type packaging structure and packaging method therefor | |
| CN104465790B (en) | MEMS pressure sensor and its method for packing | |
| EP3506349A1 (en) | Molded substrate package in fan-out wafer level package | |
| Zhan et al. | Application of Aerosol Jet technology in through-via interconnection for MEMS wafer-level packaging | |
| CN110071087A (en) | Semiconductor chip and semiconductor packages including the semiconductor chip | |
| CN104155620A (en) | Magnetic sensing device and sensing method and preparation technology thereof | |
| CN105845744B (en) | Apparatus structure with negative resistance charactertistic | |
| CN112179915B (en) | Hierarchical removing method for positioning damage points inside bare chip | |
| CN103887150B (en) | A kind of preparation method testing sample | |
| US8666140B2 (en) | Defect inspection method for wafer and wafer defect inspection system using the same | |
| CN109148357A (en) | Test interface board assembly and manufacturing method thereof | |
| US8637988B2 (en) | Semiconductor device and method of testing the same | |
| US20240355697A1 (en) | Package formation methods including coupling a molded routing layer to an integrated routing layer | |
| CN107946202A (en) | The three-dimensional storage electric test method and test structure of short process stage | |
| CN102495091A (en) | High-flexibility nuclear magnetic resonance detection chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |