CN109148357A - Test interface board assembly and manufacturing method thereof - Google Patents
Test interface board assembly and manufacturing method thereof Download PDFInfo
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- CN109148357A CN109148357A CN201710546928.3A CN201710546928A CN109148357A CN 109148357 A CN109148357 A CN 109148357A CN 201710546928 A CN201710546928 A CN 201710546928A CN 109148357 A CN109148357 A CN 109148357A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a test interface board assembly and a manufacturing method thereof. The test interface board assembly includes a dielectric layer, a first circuit layer, an amplification layer, a conductive structure and a second circuit layer. The dielectric layer has a first surface and a second surface opposite to the first surface. The first circuit layer is embedded in the dielectric layer and has an exposed surface which is lower than or flush with the first surface of the dielectric layer. The amplification layer is arranged on the second surface of the dielectric layer. The conductive structure is arranged between the dielectric layer and the amplification layer and is electrically connected with the first circuit layer. The second circuit layer is electrically connected to the first circuit layer through the conductive structure. Therefore, the invention achieves the effects of improving the reliability and the electric connection quality.
Description
Technical field
The present invention relates to a kind of test interface board group part and its manufacturing methods, are applied to integrated circuit more particularly to one kind
The manufacturing method of test interface board group part and test interface board group part on integrated circuit.
Background technique
Firstly, the mode of the switching interface plate of prior art production chip testing is all using fan-in (Fan-in)/fan
(Fan-out) makes simultaneously out, or is made in a manner of fan-in (Fan-in).For example, Taiwan Patent bulletin the
No. M455979, be using fan-in/be fanned out to while making, either in the patent of entitled " small spacing test carrier plate structure "
It is made in a manner of fan-in, and forms the hardened structure of a test interface.
However, since the hardened structure of test interface is formed in a manner of multilayer build-up, the manufacturing process of each layer of structure
In more or less error therefore formed to the engagement pad (electric conductor for connecting with probe or chip pin) of top
When, error is maximum.Whereby, the hardened structure of test interface is formed by by such production method, is less prone to realize small
Structure away from (Fine Pitch) or ultra micro spacing (Ultra-Fine Pitch).
Furthermore the problem of fine rule road (Fine Line) is formed by by fan-in processing procedure, is also likely to encounter reliability,
That is may be relatively narrow because of the line width of fine rule road, and cause the combination effect of fine rule road and dielectric layer unevident.
Summary of the invention
Technical problem to be solved by the present invention lies in, provide in view of the deficiencies of the prior art it is a kind of can improve fine rule road can
Test interface board group part and its manufacturing method by spending and being promoted electrical connectivity quality.
In order to solve the above technical problems, a wherein technical solution of the present invention is to provide a kind of test and connects
The manufacturing method of plate assemblies comprising: a substrate is provided, the substrate has a surface；A first line layer is formed in institute
It states on the surface of substrate；A dielectric layer is formed to cover the surface of the first line layer Yu the substrate；It is formed
One first conductive structure is to be electrically connected at the first line layer；An amplification layer is formed to cover the dielectric layer and described the
One conductive structure, so that first conductive structure is located between the dielectric layer and the amplification layer；Form one second conduction
Structure is to be electrically connected at first conductive structure；A soldermask layer is formed on the amplification layer, and the soldermask layer covers
Second conductive structure；One second line layer is formed on the soldermask layer, and second line layer is electrically connected at institute
State the second conductive structure；And the substrate of a portion is removed, with an exposed surface of the exposed first line layer.
It further, include: to form one first conductive part in described in the step of forming first conductive structure
Among dielectric layer, and first conductive part of first conductive structure is electrically connected at the first line layer；And shape
At one second conductive part on the dielectric layer, and second conductive part of first conductive structure be electrically connected at it is described
First conductive part of first conductive structure.
It further, include: to form one first conductive part in described in the step of forming second conductive structure
It expands among layer, and first conductive part of second conductive structure is electrically connected at the described of first conductive structure
Second conductive part；And one second conductive part is formed on the amplification layer, and described the second of second conductive structure is led
Electric portion is electrically connected at first conductive part of second conductive structure.
Further, after the step of removing the substrate of a portion, it may further comprise: one chip of setting
Unit is to be electrically connected at the exposed surface of the first line layer, and the chip unit is located at the institute of another part
It states in the accommodating space that substrate is surrounded；And one encapsulation unit of setting is in the substrate of another part, with closing
The accommodating space.
An other technical solution of the present invention is to provide a kind of manufacturing method of test interface board group part, packet
It includes: a substrate is provided, the substrate has a surface；A first line layer is formed on the surface of the substrate；It is formed
One dielectric layer is to cover the surface of the first line layer Yu the substrate；It forms one and is electrically connected at the first line
The conductive structure and an amplification layer between the dielectric layer and the conductive structure of layer；Formed one second line layer in
On the amplification layer, and second line layer is electrically connected at the first line layer by the conductive structure；And
The substrate of a portion is removed, with an exposed surface of the exposed first line layer.
Further, it in the step of forming the conductive structure and the amplification layer, may further comprise: to be formed
One soldermask layer is on the amplification layer.
Yet another aspect of the present invention is to provide a kind of test interface board group part comprising a dielectric layer, one
First line layer, one first conductive structure, an amplification layer, one second conductive structure and one second line layer.The dielectric layer
With a first surface and a second surface relative to the first surface.The first line layer is embedded at the dielectric
Among layer, wherein the first line layer has an exposed surface, and the exposed surface of the first line layer is lower than or together
Put down the first surface in the dielectric layer.First conductive structure is electrically connected at the first line layer.The expansion
Increasing layer is set to the second surface of the dielectric layer.Second conductive structure is electrically connected at the described first conductive knot
Structure.Second line layer is electrically connected at described first by second conductive structure and first conductive structure
Line layer.
Further, first conductive structure is set among the dielectric layer and is electrically connected at described including one
It first conductive part of first line layer and one is set on the dielectric layer and is electrically connected at first conductive structure
Second conductive part of first conductive part.
Further, second conductive structure is set among the amplification layer and is electrically connected at described including one
It first conductive part of second conductive part of the first conductive structure and one is set on the amplification layer and is electrically connected at
Second conductive part of first conductive part of second conductive structure.
Further, the test interface board group part may further comprise: a substrate, and the substrate, which is set to, to be given an account of
On the first surface of electric layer, and the exposed surface of the exposed first line layer.
Further, the substrate can be around an accommodating space be gone out, and a chip unit is set in the accommodating space
And one encapsulation unit close the accommodating space, wherein the chip unit is electrically connected at the described of the first line layer
Exposed surface, to form a package assembling.
Further, the test interface board group part may further comprise: that a soldermask layer, the soldermask layer are set to institute
It states on amplification layer, and second line layer is set on the soldermask layer.
Another technical solution of the present invention is to provide a kind of test interface board group part comprising a dielectric layer, one
First line layer, an amplification layer, a conductive structure and one second line layer.The dielectric layer has a first surface and one
Second surface relative to the first surface.The first line layer is embedded among the dielectric layer, wherein described first
Line layer has an exposed surface, and the exposed surface of the first line layer is lower than or is flush to the described of the dielectric layer
First surface.The amplification layer is set to the second surface of the dielectric layer.The conductive structure is set to the dielectric
Between layer and the amplification layer, and the conductive structure is electrically connected at the first line layer.Second line layer passes through
The conductive structure and be electrically connected at the first line layer.
Further, the test interface board group part may further comprise: a substrate, and the substrate, which is set to, to be given an account of
On the first surface of electric layer, and the exposed surface of the exposed first line layer.
A wherein beneficial effect of the invention is, test interface board group part and its manufacture provided by the embodiment of the present invention
Method can utilize the technical solution of " the first line layer is embedded among the dielectric layer ", to improve first line layer
Reliability.Meanwhile the present invention also can using first " formed a first line layer on the surface of the substrate " and then
The technical solution of " substrate of a portion being removed, with an exposed surface of the exposed first line layer ", and can mention
It rises electrical connectivity quality and promotes the accuracy of small spacing.
Be further understood that feature and technology contents of the invention to be enabled, please refer to below in connection with it is of the invention specifically
Bright and attached drawing, however provided attached drawing is merely provided for reference and description, is not intended to limit the present invention.
Detailed description of the invention
Fig. 1 is the side elevational cross-section schematic diagram of the test interface board group part of first embodiment of the invention.
Fig. 2 is the use state diagram of the test interface board group part of first embodiment of the invention.
Fig. 3 is that the test interface board group part of second embodiment of the invention is formed by package assembling.
Fig. 4 A is a wherein flow diagram for the manufacturing method of the test interface board group part of third embodiment of the invention.
Fig. 4 B is the flow diagram in step S108.
Fig. 4 C is the flow diagram in step S112.
Fig. 5 is the schematic diagram of the step S102 of the manufacturing process of the test interface board group part of third embodiment of the invention.
Fig. 6 is the schematic diagram of the step S104 of the manufacturing process of the test interface board group part of third embodiment of the invention.
Fig. 7 is the schematic diagram of the step S106 of the manufacturing process of the test interface board group part of third embodiment of the invention.
Fig. 8 is the schematic diagram of the step S108 of the manufacturing process of the test interface board group part of third embodiment of the invention.
Fig. 9 is the schematic diagram of the step S110 of the manufacturing process of the test interface board group part of third embodiment of the invention.
Figure 10 is the schematic diagram of the step S112 of the manufacturing process of the test interface board group part of third embodiment of the invention.
Figure 11 is the schematic diagram of the step S114 of the manufacturing process of the test interface board group part of third embodiment of the invention.
Figure 12 is the schematic diagram of the step S116 of the manufacturing process of the test interface board group part of third embodiment of the invention.
Figure 13 is that the test interface board group part of third embodiment of the invention is formed by the another of the manufacturing method of package assembling
An outer flow diagram.
Figure 14 is the flow diagram of the manufacturing method of the test interface board group part of fourth embodiment of the invention.
Specific embodiment
It is to illustrate presently disclosed related " test interface board group part and its manufacture by specific specific example below
The embodiment of method ", those skilled in the art can understand advantages of the present invention and effect by content disclosed in this specification.
The present invention can be implemented or be applied by other different specific embodiments, and the various details in this specification may be based on not
With viewpoint and application, various modifications and change are carried out under without departing substantially from design of the invention.In addition, attached drawing of the invention is only letter
It is single schematically illustrate, not according to the description of actual size, stated.The present invention will be explained in further detail in the following embodiments and the accompanying drawings
The relevant technologies content, but the technical scope that disclosure of that is not intended to limit the invention.
It should be understood that although various elements or signal etc. may be described using term first, second, third, etc. herein,
But these elements or signal should not be limited by these terms.These terms are to distinguish an element and another element, Huo Zheyi
Signal and another signal.In addition, as used herein, term "or" may include depending on actual conditions and associated list project
Any of or multiple all combinations.
First embodiment
Firstly, refering to Figure 1, Fig. 1 is the side elevational cross-section schematic diagram of test interface board group part U.The present invention provides one
Kind test interface board group part U, using the switching interface plate or space convertor as chip testing.It should be noted that below
One embodiment will first introduce the overall structure of test interface board group part U, and the manufacturing method of test interface board group part U is implemented in second
Example again row explanation.It will illustrate the specific configuration of each element in test interface board group part of embodiment of the present invention U respectively below, then
Illustrate the connection relationship in test interface board group part U between each element in due course again.
Hold it is above-mentioned, referring back to shown in Fig. 1, test interface board group part U include a dielectric layer 2, a first line layer 3 (or
Can claim fine rule road), one first conductive structure 5a, an amplification layer 4, one second conductive structure 5b and one second line layer 7.Dielectric
Layer 2 can have a first surface 21 and a second surface 22 relative to first surface 21.First line layer 3 can be embedded (or
Can claim to be embedded into) among dielectric layer 2, that is to say, that the setting position of first line layer 3 is a flush type relative to dielectric layer 2
The route of (or built-in type can be claimed).Whereby, it can increase the associativity between first line layer 3 and dielectric layer 2, to promote route
Reliability.
Hold above-mentioned, referring back to shown in Fig. 1, first line layer 3 has an exposed surface 31, first line layer 3 it is exposed
Surface 31 can be lower than or be flush to the first surface 21 of dielectric layer 2, that is to say, that the exposed surface 31 of first line layer 3 can be low
It is flushed in the either exposed surface 31 of first line layer 3 of first surface 21 of dielectric layer 2 with the first surface 21 of dielectric layer 2,
Invention is not limited thereto.Preferably, for the embodiment of the present invention, the exposed surface 31 of first line layer 3 can be with dielectric layer 2
First surface 21 flush.
Hold above-mentioned, referring back to shown in Fig. 1, the first conductive structure 5a can be electrically connected at first line layer 3, with the present invention
For embodiment, the first conductive structure 5a may include one for being set among dielectric layer 2 and being electrically connected at first line layer 3
One conductive part 51a and be set on dielectric layer 2 and be electrically connected at the first conductive structure 5a the first conductive part 51a one
Two conductive part 52a.For example, the first conductive part 51a of the first conductive structure 5a can be a conductive hole, that is, filled with leading
The hole of electroplated layer or conductive materials, and the second conductive part 52a of the first conductive structure 5a can be a line conductor, this right hair
It is bright to be not limited.
Hold above-mentioned, referring back to shown in Fig. 1, amplification layer 4 be may be disposed on the second surface 22 of dielectric layer 2, and cover the
The second conductive part 52a of one conductive structure 5a.For example, amplification layer 4 or a dielectric layer with dielectric effect.It connects
, the second conductive structure 5b can be electrically connected at the first conductive structure 5a.For the embodiment of the present invention, the second conductive structure 5b
It may include one first conduction for being set among amplification layer 4 and being electrically connected at the second conductive part 52a of the first conductive structure 5a
Portion 51b and be set to amplification layer 4 on and be electrically connected at the second conductive structure 5b the first conductive part 51b the second conductive part
52b.For example, the first conductive part 51b of the second conductive structure 5b can be a conductive hole, and the of the second conductive structure 5b
Two conductive part 52b can be a line conductor, and so invention is not limited thereto.
Furthermore, it is understood that referring back to shown in Fig. 1, test interface board group part U still further comprises a soldermask layer 6 (or can
Claim every layer), soldermask layer 6 may be disposed on amplification layer 4, and the second line layer 7 may be disposed on soldermask layer 6.In addition, with this hair
For bright embodiment, soldermask layer 6 can be covered on and on the second conductive part 52b of the second conductive structure 5b.Furthermore, for example,
Second line layer 7 can be a welding material (such as, but not limited to tin ball) or metal coupling, so that the second line layer 7 sequentially leads to
It crosses the second conductive structure 5b and the first conductive structure 5a and is electrically connected at first line layer 3.However, it should be noted that,
In other embodiments, it can also be not provided with soldermask layer 6, and make the second conductive part 52b of the second conductive structure 5b direct
As the second line layer 7, using as the conductive pad being electrically connected with circuit board.
Then, referring back to shown in Fig. 1, test interface board group part U can also further comprise a substrate 1, and substrate 1 is settable
In on the first surface 21 of dielectric layer 2, and the exposed surface 31 of exposed first line layer 3.For example, substrate 1 can be one
Hard material (or rigid material can be claimed), such as glass, metal or ceramics or high molecular polymer etc., so the present invention not as
Limit.That is, substrate 1 can be a material with certain rigidity or stiffening property degree.
Furthermore, it is understood that Fig. 2 is the use state diagram of test interface board group part U shown in referring to Figure 2 together.
The first line layer 3 of test interface board group part U is that a spacing is smaller is led with what is connect for the probe T2 with a probe assembly T
Electric contact, and the second line layer 7 is the larger conductive junction point with for being electrically connected with a printed circuit board of a spacing.Whereby,
The metal gasket that spacing small on wafer configures can be converted on the printed circuit board configured to big spacing.Meanwhile passing through substrate 1
Setting, the load-bearing part T1 of probe assembly T so that probe assembly T is fixed, and can also facilitate probe T2 water against on the base 1
The control that prosposition is set.
In addition, should be specified referring back to shown in Fig. 1, in other embodiments, can be adjusted according to demand
Expand the quantity and allocation position of layer 4, the first conductive structure 5a and the second conductive structure.Furthermore, it is understood that user can be according to
The allocation position and the number of plies for being set to dielectric layer 2 and expanding the conductive structure 5 between layer 4 are adjusted according to demand, meanwhile, it is conductive
Structure 5 can be electrically connected at first line layer 3, so that the second line layer 7 is electrically connected at First Line by conductive structure 5
Road floor 3.In other words, the quantity of conductive structure 5 can be one layer, or as shown in Figure 1 by the first conductive structure 5a and the
Two the organized layers of conductive structure 5b, or be three layers or more of structure, the present invention is not with conductive structure 5 and the number of amplification layer 4
Amount is limited.
Second embodiment
Firstly, please referring to shown in Fig. 3, Fig. 3 is that test interface board group part U is formed by package assembling P.By Fig. 3's and Fig. 1
Comparison it is found that second embodiment and first embodiment it is maximum the difference is that, can further directly be surrounded out in substrate 1
In accommodating space S, a chip unit C is set in accommodating space S, and accommodating space S is closed by an encapsulation unit 9, with
Form a package assembling P.
Then, referring back to shown in Fig. 3, specifically, the pin (unlabeled in figure) of chip unit C can be electrically connected at
The exposed surface 31 of first line layer 3, and encapsulation unit 9 can be set in substrate 1 by an adhesion coating 8, whereby, by upper
Framework is stated, can be formed directly in a package assembling P.In other words, further in an encapsulation unit is arranged on test interface board group part U
9, one can be formed for encapsulating the encapsulating carrier plate of chip unit C.In addition, though Fig. 3 is with Flip Chip (Flip-Chip) setting
Still also chip list can be arranged in the way of routing technology (wire bonding) in other embodiments in chip unit C
First C.
3rd embodiment
Firstly, please referring to shown in Fig. 4 A to Figure 12, Fig. 4 A is a wherein process for the manufacturing method of test interface board group part U
Schematic diagram, Fig. 5 to Figure 12 are the schematic diagram of the manufacturing process of test interface board group part.Specifically, Fig. 4 A to Fig. 6 institute is please referred to
Show, and shown in matching step S102: a substrate 1 is provided, substrate 1 has a surface 11.For example, substrate 1 can be hard for one
Material, such as glass, metal or ceramics or high molecular polymer etc., so invention is not limited thereto.Then, such as step S104
It is shown: to form a first line layer 3 on the surface of substrate 1 11.For example, first line layer 3 can pass through printing
(printing), sputter (sputtered coating), vapor deposition (Deposition), plating (electro plating) or change
It learns the modes such as vapor deposition (chemical vapor deposition) to be formed, so invention is not limited thereto.Whereby, due to
First line layer 3 is first arranged on a hard material, therefore, can based on a flat surface 11 of hard material, and
So that the exposed surface 31 of generated first line layer 3 is that face is leveled up in a good engaged test in subsequent step.
Then, it please refers to shown in Fig. 7, and shown in matching step S106: forming a dielectric layer 2 to cover first line layer 3
With the surface 11 of substrate 1.Again come, please refer to shown in Fig. 8, and shown in matching step S108: formed one first conductive structure 5a with
It is electrically connected at first line layer 3.Specifically, dielectric layer 2 and the first conductive structure 5a are one by Layer increasing method (Build-
Up it) is formed by layer reinforced structure, dielectric layer 2 can be made of a dielectric material, and dielectric layer 2 can utilize hot pressing, be coated with, splash
The modes such as plating, vapor deposition or deposition are formed in substrate 1, and so invention is not limited thereto.
Then, it please refers to Fig. 4 B and cooperates together shown in Fig. 7 and Fig. 8, in the step of forming the first conductive structure 5a
In can first carry out as shown in step S1081: form one first conductive part 51a among dielectric layer 2, and the first conductive structure 5a
First conductive part 51a is electrically connected at first line layer 3.Come again, then carries out shown in step S1082: it is conductive to form one second
Portion 52a is on dielectric layer 2, and the second conductive part 52a of the first conductive structure 5a is electrically connected at the of the first conductive structure 5a
One conductive part 51a.For example, a hole can be formed on dielectric layer 2 first with modes such as photoetching (lithographic), drillings, then into
One step fills the first conductive part 51a in hole.Then, the modes shape such as recycling printing, sputter, vapor deposition, plating or deposition
At the second conductive part 52a for the first conductive part 51a for being electrically connected at the first conductive structure 5a.
Then, it please refers to shown in Fig. 9, and shown in matching step S110: forming an amplification layer 4 to cover dielectric layer 2 and the
One conductive structure 5a, so that the first conductive structure 5a is located between dielectric layer 2 and amplification layer 4.Then, it please refers to shown in Figure 10,
And shown in matching step S112: forming one second conductive structure 5b to be electrically connected at the first conductive structure 5a.Specifically, expand
Increasing layer 4 and the second conductive structure 5b are one to be formed by layer reinforced structure by Layer increasing method, and for example, amplification layer 4 can be by Jie
Electric material is formed, and amplification layer 4 can be formed in the way of hot pressing, coating, sputter, vapor deposition or deposition etc., and the right present invention is not
As limit.
Then, it please refers to Fig. 4 C and cooperates together shown in Fig. 9 and Figure 10, in the step of forming the second conductive structure 5b
In can first carry out as shown in step S1121: form one first conductive part 51b among amplification layer 4, and the second conductive structure 5b
First conductive part 51b is electrically connected at the second conductive part 52a of the first conductive structure 5a.Come again, then carries out step S1122 institute
Show: forming one second conductive part 52b on amplification layer 4, and the second conductive part 52b of the second conductive structure 5b is electrically connected at the
The first conductive part 51b of two conductive structure 5b.It for example, can be first with modes such as photoetching (lithographic), drillings on amplification layer 4
A hole is formed, the first conductive part 51b is further filled in hole.Then, recycling printing, sputter, vapor deposition, plating
Or the modes such as deposition are electrically connected in the second conductive part 52b of the first conductive part 51b of the second conductive structure 5b.It must explanation
, in other embodiments, when can adjust the first conductive structure 5a's and the second conductive structure 5b according to demand
Position and quantity, and also can adjust amplification layer 4 the number of plies, the present invention endlessly this for limitation.
Then, it please refers to shown in Figure 11, and shown in matching step S114: forming a soldermask layer 6 on amplification layer 4, and anti-
Layer 6 covers the second conductive structure 5b.For example, soldermask layer 6 can be a high polymer layer, and epoxy available resin gathers
Acid imide (PI) or similar substance are formed, and so invention is not limited thereto.Come again, please refers to shown in Figure 12, and cooperate step
Shown in rapid S116: forming one second line layer 7 on soldermask layer 6, and the second line layer 7 is electrically connected at the second conductive structure
5b.For example, the second line layer 7 can be made of multiple tin balls, and the second line layer 7 can by the second conductive structure 5b and
First conductive structure 5a and be electrically connected at first line layer 3.
Then, referring back to shown in Fig. 1, Fig. 1 is the signal of the step S118 of the manufacturing process of test interface board group part U
Figure.As shown in step S118: the substrate 1 of a portion is removed, with an exposed surface 31 of exposed first line layer 3.Citing
For, using the whole substrate 1 of the substrate 1 or removal of etching or grinding removal a portion, with exposed first line layer 3
An exposed surface 31.However, preferably can only remove the substrate 1 of a portion for the embodiment of the present invention.Whereby, lead to
A test interface board group part U can be formed after crossing above-mentioned steps.
Furthermore, it is understood that Figure 13 is the manufacturer of test interface board group part U referring back to shown in Fig. 4 A to Fig. 4 C and Figure 13
An other flow diagram for method.Such as step S202: forming a first line layer 3 on a surface 11 of a substrate 1；Such as step
Shown in S204: forming a dielectric layer 2 to cover the surface 11 of first line layer 3 Yu substrate 1.Then, as shown in step S206: shape
The conductive structure 5 for being electrically connected at first line layer 3 at one and an amplification layer between dielectric layer 2 and conductive structure 5
4.Again come, as shown in step S208: formed one second line layer 7 in amplification layer 4 on, and the second line layer 7 pass through conductive structure 5
And it is electrically connected at first line layer 3.Finally, as shown in step S210: the substrate 1 of a portion is removed, with exposed first
One exposed surface 31 of line layer 3.It should be noted that step S202, the embodiment of S204, S208 and S210 are for example the same
It states, holds repeat no more herein.In addition, user can adjust conductive structure 5 and amplification layer 4 according to demand such as step S206
The number of plies.That is, conductive structure 5 and amplification layer 4 can be formed by Layer increasing method according to demand.
Fourth embodiment
Firstly, please referring to shown in Figure 14, and cooperate shown in Fig. 3 and Fig. 4 A, after having carried out step S118 together, moreover it is possible to
Step S320 and S322 are carried out, again to form a package assembling P.Specifically, as shown in step S320: one chip unit of setting
C is to be electrically connected at the exposed surface 31 of first line layer 3, and chip unit C is located at what the substrate 1 of another part was surrounded
In one accommodating space S.It should be noted that the substrate 1 of another part is remaining to get off after the substrate 1 for removing a portion
Substrate 1.In addition, for example, chip unit C can be an Image Sensor (Complementary Metal-Oxide
Semiconductor, CMOS), and the pin of chip unit C can be electrically connected at the exposed surface 31 of first line layer 3, so originally
Invention is not limited.In other words, the chip unit C of other function can be set according to demand.Furthermore, it is understood that at other
In embodiment, micro electronmechanical encapsulation (MEMS Packaging) also can be applied to.
Then, referring back to shown in Fig. 3 and Figure 14, as shown in step S322: one encapsulation unit 9 of setting is in another part
Substrate 1 on, to close accommodating space S.For example, encapsulation unit 9 can be a lid, and encapsulation unit 9 can pass through one
Adhesion coating 8 and be set in the substrate 1 of another part.Whereby, to form a package assembling P.Furthermore, it is understood that due to substrate
1 is to be formed by step s 102, therefore, can avoid re-forming in the next steps caused by a substrate 1 and encapsulation unit 9
Excessive glue problem generate.Simultaneously, moreover it is possible to help to reduce the cost of encapsulation procedure.Whereby, being formed by package assembling P can be direct
It is set in a circuit board (not shown).It is worth noting that an encapsulation unit 9 is arranged in the substrate of another part
On 1, the step of to close accommodating space S before, can also further comprise: one packing colloid (not shown) of setting be empty in accommodating
Between in S, with coating chip unit C.For example, packing colloid can be an epoxy resin (Epoxy), and so the present invention is not with this
It is limited.
The beneficial effect of embodiment
A wherein beneficial effect of the invention can be, test interface board group part provided by the embodiment of the present invention and its
Manufacturing method, can utilize the technical solution of " first line layer 3 is embedded among dielectric layer 2 ", and can improve first line layer 3
Reliability.
In addition, the present invention using first " one first line layer 3 of formation is on 11 surfaces of substrate 1 " and then " can also remove
The substrate 1 of a portion with the technical solution of an exposed surface 31 " of exposed first line layer 3, and can promote electrical connectivity
Quality and the accuracy for promoting small spacing.Meanwhile the processing procedure of small spacing is made compared to the prior art, this processing procedure can be simpler
Change, and promotes the yield of integrated testability interface board component U.
In addition, also due to the present invention is to be initially formed the highest first line layer 3 of precision size degree demand in a manner of being fanned out to, because
This is formed by engaged test pad using fan-in mode compared to the prior art, and the present invention can obtain a complete plane, in turn
It generates good engaged test and levels up face.
Furthermore since first line layer 3 is the embedment for being embedded among dielectric layer 2 and being coated by dielectric layer 2, and formed
Therefore formula structure can promote the reliability of first line layer 3, and make first line layer 3 not easily damaged.Simultaneously as being to adopt
Test interface board group part U is formed with the mode of being fanned out to, therefore, caused by the reason that the prior art is arranged by core base can be removed from
The excessive problem of integral thickness.Whereby, since thickness reduces, and then it can be shortened transmission path, and then solve the problems, such as high inductance,
And it can help to characteristic impedance control and the control of Power Integrity.
Furthermore, it is understood that " substrate 1 of a portion is removed, after an exposed surface 31 " of exposed first line layer 3,
Recycling another part is set to the substrate 1 on dielectric layer 2, using as provide it is subsequent assembling probe assembly T basis and
Positioning, facilitates the control of the horizontal position probe T2.
Content disclosed above is only preferred possible embodiments of the invention, not thereby limits to right of the invention and wants
The protection scope of book is sought, so all equivalence techniques variations done with description of the invention and accompanying drawing content, are both contained in
In the protection scope of claims of the present invention.
Claims (14)
1. a kind of manufacturing method of test interface board group part, which is characterized in that the manufacturing method packet of the test interface board group part
It includes:
A substrate is provided, the substrate has a surface；
A first line layer is formed on the surface of the substrate；
A dielectric layer is formed to cover the surface of the first line layer Yu the substrate；
One first conductive structure is formed to be electrically connected at the first line layer；
An amplification layer is formed to cover the dielectric layer and first conductive structure, so that first conductive structure is located at institute
It gives an account of between electric layer and the amplification layer；
One second conductive structure is formed to be electrically connected at first conductive structure；
A soldermask layer is formed on the amplification layer, and the soldermask layer covers second conductive structure；
One second line layer is formed on the soldermask layer, and second line layer is electrically connected at the described second conductive knot
Structure；And
The substrate of a portion is removed, with an exposed surface of the exposed first line layer.
2. the manufacturing method of test interface board group part according to claim 1, which is characterized in that led forming described first
Include: in the step of electric structure
One first conductive part is formed among the dielectric layer, and first conductive part of first conductive structure electrically connects
It is connected to the first line layer；And
One second conductive part is formed on the dielectric layer, and second conductive part of first conductive structure is electrically connected
In first conductive part of first conductive structure.
3. the manufacturing method of test interface board group part according to claim 2, which is characterized in that led forming described second
Include: in the step of electric structure
One first conductive part is formed among the amplification layer, and first conductive part of second conductive structure electrically connects
It is connected to second conductive part of first conductive structure；And
One second conductive part is formed on the amplification layer, and second conductive part of second conductive structure is electrically connected
In first conductive part of second conductive structure.
4. the manufacturing method of test interface board group part according to claim 1, which is characterized in that removing a portion
The substrate the step of after, may further comprise:
One chip unit is set to be electrically connected at the exposed surface of the first line layer, and the chip unit is located at
In the accommodating space that the substrate of another part is surrounded；And
One encapsulation unit is set in the substrate of another part, to close the accommodating space.
5. a kind of manufacturing method of test interface board group part, which is characterized in that the manufacturing method packet of the test interface board group part
It includes:
A substrate is provided, the substrate has a surface；
A first line layer is formed on the surface of the substrate；
A dielectric layer is formed to cover the surface of the first line layer Yu the substrate；
Formation one is electrically connected at the conductive structure of the first line layer and one is located at the dielectric layer and the conductive knot
Amplification layer between structure；
One second line layer is formed on the amplification layer, and second line layer is electrically connected by the conductive structure
In the first line layer；And
The substrate of a portion is removed, with an exposed surface of the exposed first line layer.
6. the manufacturing method of test interface board group part according to claim 5, which is characterized in that forming the conductive knot
In the step of structure and the amplification layer, it may further comprise:
A soldermask layer is formed on the amplification layer.
7. a kind of test interface board group part, which is characterized in that the manufacturing method of the test interface board group part includes:
One dielectric layer, the dielectric layer have a first surface and a second surface relative to the first surface；
One first line layer, the first line layer are embedded among the dielectric layer, wherein the first line layer has one
The exposed surface of exposed surface, the first line layer is lower than or is flush to the first surface of the dielectric layer；
One first conductive structure, first conductive structure are electrically connected at the first line layer；
One amplification layer, the amplification layer are set to the second surface of the dielectric layer；
One second conductive structure, second conductive structure are electrically connected at first conductive structure；And
One second line layer, second line layer pass through second conductive structure and the first conductive structure electrical property
It is connected to the first line layer.
8. test interface board group part according to claim 7, which is characterized in that first conductive structure includes a setting
Among the dielectric layer and it is electrically connected at the first conductive part of the first line layer and one is set to the dielectric layer
Second conductive part of first conductive part that is upper and being electrically connected at first conductive structure.
9. test interface board group part according to claim 8, which is characterized in that second conductive structure includes a setting
Among the amplification layer and the first conductive part of second conductive part that is electrically connected at first conductive structure and
One is set to the second conductive part of first conductive part on the amplification layer and being electrically connected at second conductive structure.
10. test interface board group part according to claim 7, which is characterized in that the test interface board group part is also into one
Step includes: a substrate, and the substrate is set on the first surface of the dielectric layer, and the exposed first line layer
The exposed surface.
11. test interface board group part according to claim 10, which is characterized in that the substrate can be empty around an accommodating is gone out
Between, a chip unit is set in the accommodating space and an encapsulation unit closes the accommodating space, wherein the chip list
Member is electrically connected at the exposed surface of the first line layer, to form a package assembling.
12. test interface board group part according to claim 7, which is characterized in that the test interface board group part is also into one
Step includes: a soldermask layer, and the soldermask layer is set on the amplification layer, and second line layer is set to the soldermask layer
On.
13. a kind of test interface board group part, which is characterized in that the test interface board group part includes:
One dielectric layer, the dielectric layer have a first surface and a second surface relative to the first surface；
One first line layer, the first line layer are embedded among the dielectric layer, wherein the first line layer has one
The exposed surface of exposed surface, the first line layer is lower than or is flush to the first surface of the dielectric layer；
One amplification layer, the amplification layer are set to the second surface of the dielectric layer；
One conductive structure, the conductive structure are set between the dielectric layer and the amplification layer, and conductive structure electricity
Property is connected to the first line layer；And
One second line layer, second line layer are electrically connected at the first line layer by the conductive structure.
14. test interface board group part according to claim 13, which is characterized in that the test interface board group part is also into one
Step includes: a substrate, and the substrate is set on the first surface of the dielectric layer, and the exposed first line layer
The exposed surface.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106121585 | 2017-06-28 | ||
| TW106121585A TWI612599B (en) | 2017-06-28 | 2017-06-28 | Testing board component and manufacturing method thereof |
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| Publication Number | Publication Date |
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| CN109148357A true CN109148357A (en) | 2019-01-04 |
| CN109148357B CN109148357B (en) | 2021-12-17 |
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| CN201710546928.3A Active CN109148357B (en) | 2017-06-28 | 2017-07-06 | Test interface board assembly and manufacturing method thereof |
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| TWI721424B (en) * | 2018-05-23 | 2021-03-11 | 旺矽科技股份有限公司 | Space transformer, probe card, and manufacturing methods thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102324407A (en) * | 2011-09-22 | 2012-01-18 | 日月光半导体制造股份有限公司 | Semiconductor packaging piece and manufacturing method thereof |
| US20130256012A1 (en) * | 2009-06-03 | 2013-10-03 | Shinko Electric Industries Co., Ltd. | Wiring substrate and method of manufacturing the same |
| CN104851814A (en) * | 2014-02-13 | 2015-08-19 | 台湾积体电路制造股份有限公司 | Integrated circuit package and methods of forming same |
| CN106229309A (en) * | 2016-07-20 | 2016-12-14 | 日月光半导体(上海)有限公司 | Base plate for packaging and manufacture method thereof |
-
2017
- 2017-06-28 TW TW106121585A patent/TWI612599B/en active
- 2017-07-06 CN CN201710546928.3A patent/CN109148357B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130256012A1 (en) * | 2009-06-03 | 2013-10-03 | Shinko Electric Industries Co., Ltd. | Wiring substrate and method of manufacturing the same |
| CN102324407A (en) * | 2011-09-22 | 2012-01-18 | 日月光半导体制造股份有限公司 | Semiconductor packaging piece and manufacturing method thereof |
| CN104851814A (en) * | 2014-02-13 | 2015-08-19 | 台湾积体电路制造股份有限公司 | Integrated circuit package and methods of forming same |
| CN106229309A (en) * | 2016-07-20 | 2016-12-14 | 日月光半导体(上海)有限公司 | Base plate for packaging and manufacture method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201906037A (en) | 2019-02-01 |
| CN109148357B (en) | 2021-12-17 |
| TWI612599B (en) | 2018-01-21 |
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