CN109148357B - Test interface board assembly and manufacturing method thereof - Google Patents
Test interface board assembly and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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Abstract
The invention discloses a test interface board assembly and a manufacturing method thereof. The test interface board assembly includes a dielectric layer, a first circuit layer, an amplification layer, a conductive structure and a second circuit layer. The dielectric layer has a first surface and a second surface opposite to the first surface. The first circuit layer is embedded in the dielectric layer and has an exposed surface which is lower than or flush with the first surface of the dielectric layer. The amplification layer is arranged on the second surface of the dielectric layer. The conductive structure is arranged between the dielectric layer and the amplification layer and is electrically connected with the first circuit layer. The second circuit layer is electrically connected to the first circuit layer through the conductive structure. Therefore, the invention achieves the effects of improving the reliability and the electric connection quality.
Description
Technical Field
The present invention relates to a test interface board assembly and a method for manufacturing the same, and more particularly, to a test interface board assembly applied to an integrated circuit and a method for manufacturing the same.
Background
First, the conventional methods for manufacturing the landing interface board for testing the chip all use Fan-in (Fan-in)/Fan-out (Fan-out) manufacturing at the same time, or Fan-in (Fan-in) manufacturing. For example, in taiwan patent publication No. M455979 entitled "fine pitch test carrier board structure", a fan-in/fan-out process is performed simultaneously or in a fan-in manner to form a test interface board structure.
However, since the test interface board structure is formed by stacking a plurality of layers, there is a certain error in the manufacturing process of each layer, and thus the error is the largest when forming the contact pads (for the electrical conductors connected to the probes or chip pins) to the top layer. Therefore, the test interface board structure formed by the manufacturing method is not easy to realize the structure of micro Pitch (Fine Pitch) or Ultra-micro Pitch (Ultra-Fine Pitch).
Furthermore, the Fine Line (Fine Line) formed by the fan-in process is also prone to suffer from reliability problems, that is, the narrow Line width of the Fine Line may cause poor bonding effect between the Fine Line and the dielectric layer.
In addition, the structure of the test interface board disclosed in the above prior art is not designed for packaging chips.
Disclosure of Invention
The present invention is directed to a test interface board assembly and a method for manufacturing the same, which can improve the reliability of a fine line and the quality of electrical connectivity.
In order to solve the above technical problem, one technical solution adopted by the present invention is to provide a method for manufacturing a test interface board assembly, including: providing a substrate, wherein the substrate is provided with a surface; forming a first circuit layer on the surface of the substrate; forming a dielectric layer to cover the first circuit layer and the surface of the substrate; forming a first conductive structure to be electrically connected to the first circuit layer; forming an amplification layer to cover the dielectric layer and the first conductive structure such that the first conductive structure is located between the dielectric layer and the amplification layer; forming a second conductive structure to be electrically connected to the first conductive structure; forming a solder mask layer on the amplification layer, wherein the solder mask layer covers the second conductive structure; forming a second circuit layer on the solder mask layer, wherein the second circuit layer is electrically connected to the second conductive structure; and removing a part of the substrate to expose an exposed surface of the first circuit layer.
Still further, the step of forming the first conductive structure includes: forming a first conductive portion in the dielectric layer, wherein the first conductive portion of the first conductive structure is electrically connected to the first circuit layer; and forming a second conductive portion on the dielectric layer, wherein the second conductive portion of the first conductive structure is electrically connected to the first conductive portion of the first conductive structure.
Still further, the step of forming the second conductive structure includes: forming a first conductive portion in the amplification layer, wherein the first conductive portion of the second conductive structure is electrically connected to the second conductive portion of the first conductive structure; and forming a second conductive part on the amplification layer, wherein the second conductive part of the second conductive structure is electrically connected to the first conductive part of the second conductive structure.
Still further, after the step of removing a portion of the substrate, the method further includes: arranging a chip unit to be electrically connected to the exposed surface of the first circuit layer, wherein the chip unit is positioned in an accommodating space surrounded by the other part of the substrate; and arranging a packaging unit on the other part of the substrate to seal the accommodating space.
Another technical solution adopted by the present invention is to provide a method for manufacturing a test interface board assembly, including: providing a substrate, wherein the substrate is provided with a surface; forming a first circuit layer on the surface of the substrate; forming a dielectric layer to cover the first circuit layer and the surface of the substrate; forming a conductive structure electrically connected to the first circuit layer and an amplification layer between the dielectric layer and the conductive structure; forming a second circuit layer on the amplification layer, wherein the second circuit layer is electrically connected to the first circuit layer through the conductive structure; and removing a part of the substrate to expose an exposed surface of the first circuit layer.
Still further, in the step of forming the conductive structure and the amplification layer, the method further includes: forming a solder mask layer on the amplification layer.
In another embodiment of the present invention, a test interface board assembly is provided, which includes a dielectric layer, a first circuit layer, a first conductive structure, an amplification layer, a second conductive structure, and a second circuit layer. The dielectric layer has a first surface and a second surface opposite to the first surface. The first circuit layer is embedded in the dielectric layer, wherein the first circuit layer has an exposed surface, and the exposed surface of the first circuit layer is lower than or flush with the first surface of the dielectric layer. The first conductive structure is electrically connected to the first circuit layer. The amplification layer is disposed on the second surface of the dielectric layer. The second conductive structure is electrically connected to the first conductive structure. The second circuit layer is electrically connected to the first circuit layer through the second conductive structure and the first conductive structure.
Furthermore, the first conductive structure includes a first conductive portion disposed in the dielectric layer and electrically connected to the first circuit layer, and a second conductive portion disposed on the dielectric layer and electrically connected to the first conductive portion of the first conductive structure.
Furthermore, the second conductive structure includes a first conductive portion disposed in the amplification layer and electrically connected to the second conductive portion of the first conductive structure, and a second conductive portion disposed on the amplification layer and electrically connected to the first conductive portion of the second conductive structure.
Still further, the test interface board assembly further comprises: and the substrate is arranged on the first surface of the dielectric layer and exposes the exposed surface of the first circuit layer.
Furthermore, the substrate can surround an accommodating space, a chip unit is arranged in the accommodating space, and a packaging unit seals the accommodating space, wherein the chip unit is electrically connected to the exposed surface of the first circuit layer to form a packaging assembly.
Still further, the test interface board assembly further comprises: and the welding-proof layer is arranged on the amplification layer, and the second circuit layer is arranged on the welding-proof layer.
In another aspect, the present invention provides a test interface board assembly, which includes a dielectric layer, a first circuit layer, an amplification layer, a conductive structure, and a second circuit layer. The dielectric layer has a first surface and a second surface opposite to the first surface. The first circuit layer is embedded in the dielectric layer, wherein the first circuit layer has an exposed surface, and the exposed surface of the first circuit layer is lower than or flush with the first surface of the dielectric layer. The amplification layer is disposed on the second surface of the dielectric layer. The conductive structure is arranged between the dielectric layer and the amplification layer and is electrically connected with the first circuit layer. The second circuit layer is electrically connected to the first circuit layer through the conductive structure.
Still further, the test interface board assembly further comprises: and the substrate is arranged on the first surface of the dielectric layer and exposes the exposed surface of the first circuit layer.
The test interface board assembly and the manufacturing method thereof provided by the embodiment of the invention can utilize the technical scheme that the first circuit layer is embedded in the dielectric layer, so as to improve the reliability of the first circuit layer. Meanwhile, the invention can also utilize the technical scheme of firstly forming a first circuit layer on the surface of the substrate and then removing a part of the substrate to expose an exposed surface of the first circuit layer, thereby improving the quality of electric connection and the accuracy of micro-spacing.
In addition, the test interface board assembly and the manufacturing method thereof provided by the invention can also expose the exposed surface of the first circuit layer by removing a part of the substrate; arranging a chip unit to be electrically connected to the exposed surface of the first circuit layer, wherein the chip unit is positioned in an accommodating space surrounded by the other part of the substrate; and arranging a packaging unit on the other part of the substrate to seal the accommodating space, so that a packaging assembly for packaging the chip unit can be directly formed.
For a better understanding of the features and technical content of the present invention, reference should be made to the following detailed description of the invention and accompanying drawings, which are provided for purposes of illustration and description only and are not intended to limit the invention.
Drawings
Fig. 1 is a schematic side sectional view of a test interface board assembly according to a first embodiment of the present invention.
Fig. 2 is a schematic view illustrating a use state of a test interface board assembly according to a first embodiment of the present invention.
Fig. 3 shows a package assembly formed by a test interface board assembly according to a second embodiment of the present invention.
Fig. 4A is a flowchart illustrating a method for manufacturing a test interface board assembly according to a third embodiment of the present invention.
Fig. 4B is a flowchart of step S108.
Fig. 4C is a schematic flowchart of step S112.
Fig. 5 is a schematic diagram of step S102 of a manufacturing process of a test interface board assembly according to a third embodiment of the invention.
Fig. 6 is a schematic diagram of step S104 of a manufacturing process of a test interface board assembly according to a third embodiment of the invention.
Fig. 7 is a schematic diagram of step S106 of a manufacturing process of a test interface board assembly according to a third embodiment of the invention.
Fig. 8 is a schematic diagram of step S108 of the manufacturing process of the test interface board assembly according to the third embodiment of the present invention.
Fig. 9 is a schematic diagram of step S110 of a manufacturing process of a test interface board assembly according to a third embodiment of the invention.
Fig. 10 is a schematic diagram of step S112 of a manufacturing process of a test interface board assembly according to a third embodiment of the invention.
Fig. 11 is a schematic diagram of step S114 of a manufacturing process of a test interface board assembly according to a third embodiment of the invention.
Fig. 12 is a schematic diagram of step S116 of a manufacturing process of a test interface board assembly according to a third embodiment of the invention.
Fig. 13 is another flow chart illustrating a method of fabricating a package assembly formed by testing an interface board assembly according to a third embodiment of the present invention.
Fig. 14 is a flowchart illustrating a method for manufacturing a test interface board assembly according to a fourth embodiment of the present invention.
Detailed Description
The following is a description of the embodiments of the test interface board assembly and the method for manufacturing the same according to the present disclosure, and those skilled in the art will understand the advantages and effects of the present disclosure from the disclosure of the present disclosure. The invention is capable of other and different embodiments and its several details are capable of modification in various, obvious aspects, and various changes can be made without departing from the spirit and scope of the present invention. The drawings of the present invention are for illustrative purposes only and are not drawn to scale. The following embodiments will further explain the technical contents related to the present invention in detail, but the disclosure is not intended to limit the technical scope of the present invention.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements or signals, etc., these elements or signals should not be limited by these terms. These terms are used to distinguish one element from another element, or from one signal to another signal. In addition, as used herein, the term "or" may include all combinations of any one or more of the associated listed items as appropriate.
First embodiment
First, please refer to fig. 1, which is a schematic side sectional view of a test interface board assembly U in fig. 1. The invention provides a test interface board assembly U which is used as a switching interface board or a space converter for chip testing. It should be noted that, in the following first embodiment, the overall structure of the test interface board assembly U will be described, and the manufacturing method of the test interface board assembly U will be described in the second embodiment. The following will respectively describe specific configurations of the components in the test interface board assembly U according to the embodiment of the present invention, and then timely describe the connection relationship between the components in the test interface board assembly U.
In view of the above, referring to fig. 1, the test interface board assembly U includes a dielectric layer 2, a first circuit layer 3 (or called thin circuit), a first conductive structure 5a, an amplification layer 4, a second conductive structure 5b, and a second circuit layer 7. The dielectric layer 2 may have a first surface 21 and a second surface 22 opposite to the first surface 21. The first circuit layer 3 may be embedded (or may be referred to as embedded) in the dielectric layer 2, that is, the first circuit layer 3 is disposed at a position of an embedded (or may be referred to as buried) circuit with respect to the dielectric layer 2. Therefore, the bonding property between the first circuit layer 3 and the dielectric layer 2 can be increased, so as to improve the reliability of the circuit.
In view of the above, referring to fig. 1 again, the first circuit layer 3 has an exposed surface 31, and the exposed surface 31 of the first circuit layer 3 may be lower than or flush with the first surface 21 of the dielectric layer 2, that is, the exposed surface 31 of the first circuit layer 3 may be lower than the first surface 21 of the dielectric layer 2 or the exposed surface 31 of the first circuit layer 3 is flush with the first surface 21 of the dielectric layer 2, which is not limited thereto. Preferably, for the embodiment of the present invention, the exposed surface 31 of the first circuit layer 3 may be flush with the first surface 21 of the dielectric layer 2.
In view of the above, referring to fig. 1 again, the first conductive structure 5a may be electrically connected to the first circuit layer 3, and according to an embodiment of the present invention, the first conductive structure 5a may include a first conductive portion 51a disposed in the dielectric layer 2 and electrically connected to the first circuit layer 3, and a second conductive portion 52a disposed on the dielectric layer 2 and electrically connected to the first conductive portion 51a of the first conductive structure 5 a. For example, the first conductive portion 51a of the first conductive structure 5a may be a conductive hole, i.e., a hole filled with a conductive plating or a conductive material, and the second conductive portion 52a of the first conductive structure 5a may be a circuit conductor, but the invention is not limited thereto.
As described above, referring to fig. 1 again, the amplification layer 4 may be disposed on the second surface 22 of the dielectric layer 2 and cover the second conductive portion 52a of the first conductive structure 5 a. For example, the amplification layer 4 can also be a dielectric layer with dielectric effect. Then, the second conductive structure 5b can be electrically connected to the first conductive structure 5 a. For the embodiment of the present invention, the second conductive structure 5b may include a first conductive portion 51b disposed in the amplification layer 4 and electrically connected to the second conductive portion 52a of the first conductive structure 5a, and a second conductive portion 52b disposed on the amplification layer 4 and electrically connected to the first conductive portion 51b of the second conductive structure 5 b. For example, the first conductive portion 51b of the second conductive structure 5b may be a conductive hole, and the second conductive portion 52b of the second conductive structure 5b may be a line conductor, but the invention is not limited thereto.
Further, referring to fig. 1, the test interface board assembly U further includes a solder mask layer 6 (or solder mask layer), the solder mask layer 6 can be disposed on the amplification layer 4, and the second circuit layer 7 can be disposed on the solder mask layer 6. In addition, according to the embodiment of the present invention, the solder mask layer 6 can cover the second conductive portion 52b of the second conductive structure 5 b. Furthermore, for example, the second circuit layer 7 can be a solder material (such as but not limited to solder ball) or metal bump, so that the second circuit layer 7 is electrically connected to the first circuit layer 3 sequentially through the second conductive structure 5b and the first conductive structure 5 a. However, in other embodiments, the solder mask layer 6 may not be disposed, and the second conductive portion 52b of the second conductive structure 5b may be directly used as the second circuit layer 7 to be a conductive pad electrically connected to the circuit board.
Next, referring to fig. 1 again, the test interface board assembly U may further include a substrate 1, and the substrate 1 may be disposed on the first surface 21 of the dielectric layer 2 and expose the exposed surface 31 of the first circuit layer 3. For example, the substrate 1 may be a hard material (or referred to as a rigid material), such as glass, metal, ceramic, or polymer, but the invention is not limited thereto. That is, the substrate 1 may be a material having a certain degree of rigidity or stiffness.
Further, referring to fig. 2, fig. 2 is a schematic view illustrating a usage status of the test interface board assembly U. The first circuit layer 3 of the test interface board assembly U is a conductive contact with a smaller pitch for connecting with a probe T2 of a probe assembly T, and the second circuit layer 7 is a conductive contact with a larger pitch for electrically connecting with a printed circuit board. Therefore, the metal pads arranged at small intervals on the wafer can be converted to the printed circuit board arranged at large intervals. Meanwhile, through the arrangement of the substrate 1, the bearing member T1 of the probe assembly T can also abut against the substrate 1 for the probe assembly T to be fixed, thereby facilitating the control of the horizontal position of the probe T2.
In addition, referring to fig. 1 again, it should be specifically described that in other embodiments, the number and the arrangement positions of the amplification layer 4, the first conductive structures 5a and the second conductive structures may be adjusted according to requirements. Further, the user can adjust the arrangement position and the number of the conductive structures 5 disposed between the dielectric layer 2 and the amplification layer 4 according to the requirement, and meanwhile, the conductive structures 5 can be electrically connected to the first circuit layer 3, so that the second circuit layer 7 is electrically connected to the first circuit layer 3 through the conductive structures 5. In other words, the number of the conductive structures 5 may be one layer, or a layer composed of the first conductive structure 5a and the second conductive structure 5b as shown in fig. 1, or a structure with more than three layers, and the invention is not limited to the number of the conductive structures 5 and the amplification layers 4.
Second embodiment
First, referring to fig. 3, fig. 3 shows a package assembly P formed by testing an interface board assembly U. As can be seen from a comparison between fig. 3 and fig. 1, the greatest difference between the second embodiment and the first embodiment is that a chip unit C can be further directly disposed in the accommodating space S surrounded by the substrate 1, and the accommodating space S is sealed by a packaging unit 9 to form a packaging assembly P.
Referring to fig. 3 again, in detail, the pins (not numbered) of the chip unit C may be electrically connected to the exposed surface 31 of the first circuit layer 3, and the package unit 9 may be disposed on the substrate 1 through an adhesive layer 8, thereby directly forming a package assembly P through the above-mentioned structure. In other words, a package unit 9 is further disposed on the test interface board assembly U to form a package carrier for packaging the chip unit C. Although fig. 3 shows the Chip cell C formed by Flip-Chip technology (Flip-Chip), the Chip cell C may be formed by wire bonding in other embodiments.
Third embodiment
First, referring to fig. 4A to 12, fig. 4A is a schematic flow chart of a manufacturing method of a test interface board assembly U, and fig. 5 to 12 are schematic diagrams of a manufacturing process of the test interface board assembly U. In detail, please refer to fig. 4A to fig. 6, and step S102 is executed: a substrate 1 is provided, the substrate 1 having a surface 11. For example, the substrate 1 may be a hard material, such as glass, metal, ceramic, or polymer, but the invention is not limited thereto. Then, as shown in step S104: a first circuit layer 3 is formed on the surface 11 of the substrate 1. For example, the first circuit layer 3 can be formed by printing (printing), sputtering (sputtering), evaporation (Deposition), electroplating (electro-Deposition) or chemical vapor Deposition (chemical vapor Deposition), but the invention is not limited thereto. Therefore, since the first circuit layer 3 is disposed on a hard material, a flat surface 11 of the hard material can be used as a base, so that the exposed surface 31 of the first circuit layer 3 generated in the subsequent step is a good contact test pad plane.
Next, please refer to fig. 7, and step S106 is executed to: a dielectric layer 2 is formed to cover the first circuit layer 3 and the surface 11 of the substrate 1. Please refer to fig. 8, and step S108 is executed: a first conductive structure 5a is formed to electrically connect to the first circuit layer 3. In detail, the dielectric layer 2 and the first conductive structure 5a are Build-up structures formed by a Build-up process (Build-up), the dielectric layer 2 may be made of a dielectric material, and the dielectric layer 2 may be formed on the substrate 1 by thermal pressing, coating, sputtering, evaporation or deposition, but the invention is not limited thereto.
Next, referring to fig. 4B in combination with fig. 7 and 8, in the step of forming the first conductive structure 5a, step S1081 may be performed first: a first conductive portion 51a is formed in the dielectric layer 2, and the first conductive portion 51a of the first conductive structure 5a is electrically connected to the first circuit layer 3. Then, step S1082 is followed: a second conductive portion 52a is formed on the dielectric layer 2, and the second conductive portion 52a of the first conductive structure 5a is electrically connected to the first conductive portion 51a of the first conductive structure 5 a. For example, a hole may be formed on the dielectric layer 2 by photolithography (lithography), drilling, and the like, and then the hole is filled with the first conductive portion 51 a. Then, the second conductive portion 52a electrically connected to the first conductive portion 51a of the first conductive structure 5a can be formed by printing, sputtering, evaporation, electroplating or deposition.
Next, please refer to fig. 9, and step S110 is executed to: an amplification layer 4 is formed to cover the dielectric layer 2 and the first conductive structure 5a, such that the first conductive structure 5a is located between the dielectric layer 2 and the amplification layer 4. Next, please refer to fig. 10, and step S112 is executed to: a second conductive structure 5b is formed to electrically connect to the first conductive structure 5 a. In detail, the amplification layer 4 and the second conductive structure 5b are a layer-adding structure formed by a layer-adding method, for example, the amplification layer 4 may be composed of a dielectric material, and the amplification layer 4 may be formed by thermal pressing, coating, sputtering, evaporation or deposition, but the invention is not limited thereto.
Next, referring to fig. 4C in combination with fig. 9 and 10, in the step of forming the second conductive structure 5b, step S1121 may be performed first: a first conductive part 51b is formed in the amplification layer 4, and the first conductive part 51b of the second conductive structure 5b is electrically connected to the second conductive part 52a of the first conductive structure 5 a. Then, step S1122 is followed: a second conductive part 52b is formed on the amplification layer 4, and the second conductive part 52b of the second conductive structure 5b is electrically connected to the first conductive part 51b of the second conductive structure 5 b. For example, a hole may be formed on the amplification layer 4 by photolithography (lithography), drilling, and the like, and then the hole is filled with the first conductive portion 51 b. Then, the second conductive portion 52b electrically connected to the first conductive portion 51b of the second conductive structure 5b can be formed by printing, sputtering, evaporation, electroplating or deposition. It should be noted that, in other embodiments, the number of the amplification layers 4 can be adjusted by adjusting the positions and the numbers of the first conductive structures 5a and the second conductive structures 5b according to the requirement, and the invention is not limited thereto.
Next, please refer to fig. 11, and step S114 is executed to: a solder mask 6 is formed on the amplification layer 4, and the solder mask 6 covers the second conductive structure 5 b. For example, the solder mask 6 may be a polymer layer, which may be formed by epoxy, Polyimide (PI), or the like, but the invention is not limited thereto. Please refer to fig. 12, and step S116 shows: a second circuit layer 7 is formed on the solder mask layer 6, and the second circuit layer 7 is electrically connected to the second conductive structure 5 b. For example, the second circuit layer 7 may be composed of a plurality of solder balls, and the second circuit layer 7 may be electrically connected to the first circuit layer 3 through the second conductive structure 5b and the first conductive structure 5 a.
Next, referring back to fig. 1, fig. 1 is a schematic diagram illustrating a step S118 of a manufacturing process of the test interface board assembly U. As shown in step S118: a portion of the substrate 1 is removed to expose an exposed surface 31 of the first circuit layer 3. For example, a portion of the substrate 1 or the entire substrate 1 may be removed by etching or grinding to expose an exposed surface 31 of the first circuit layer 3. However, for the present embodiment, it is preferable that only a part of the substrate 1 may be removed. Therefore, the test interface board assembly U can be formed through the steps.
Further, referring to fig. 4A to 4C and fig. 13, fig. 13 is another flow chart of the manufacturing method of the test interface board assembly U. As step S202: forming a first circuit layer 3 on a surface 11 of a substrate 1; as shown in step S204: a dielectric layer 2 is formed to cover the first circuit layer 3 and the surface 11 of the substrate 1. Next, as shown in step S206: a conductive structure 5 electrically connected to the first circuit layer 3 and an amplification layer 4 between the dielectric layer 2 and the conductive structure 5 are formed. Then, as shown in step S208: a second circuit layer 7 is formed on the amplification layer 4, and the second circuit layer 7 is electrically connected to the first circuit layer 3 through the conductive structure 5. Finally, as shown in step S210: a portion of the substrate 1 is removed to expose an exposed surface 31 of the first circuit layer 3. It should be noted that the implementation of steps S202, S204, S208, and S210 is the same as the above, and will not be described herein again. In addition, in step S206, the user can adjust the number of the conductive structures 5 and the number of the amplification layers 4 according to the requirement. That is, the conductive structure 5 and the amplification layer 4 may be formed by a layer-adding method according to the requirement.
Fourth embodiment
First, referring to fig. 14 in combination with fig. 3 and 4A, after step S118, steps S120 and S122 can be performed to form a package assembly P. In detail, as shown in step S120: a chip unit C is disposed to be electrically connected to the exposed surface 31 of the first circuit layer 3, and the chip unit C is located in an accommodating space S surrounded by another portion of the substrate 1. It should be noted that the other portion of the substrate 1 is the substrate 1 remaining after removing one portion of the substrate 1. In addition, for example, the chip unit C may be an image sensor (CMOS), and the pins of the chip unit C may be electrically connected to the exposed surface 31 of the first circuit layer 3, but the invention is not limited thereto. In other words, other functional chip units C may be provided according to the requirements. Further, in other embodiments, the method can also be applied to micro-electromechanical Packaging (MEMS Packaging).
Next, referring back to fig. 3 and fig. 14, in step S122: a packaging unit 9 is disposed on another portion of the substrate 1 to enclose the accommodating space S. For example, the package unit 9 may be a cover, and the package unit 9 may be disposed on another portion of the substrate 1 through an adhesive layer 8. Thereby, a package assembly P is formed. Further, since the substrate 1 is formed in the step S102, the problem of glue overflow caused by forming a substrate 1 and the package unit 9 in the subsequent steps can be avoided. Meanwhile, the cost of the packaging process can be reduced. Thus, the formed package assembly P can be directly disposed on a circuit board (not shown). It should be noted that, before the step of disposing a packaging unit 9 on another part of the substrate 1 to close the accommodating space S, the method may further include: an encapsulant (not shown) is disposed in the accommodating space S to encapsulate the chip unit C. For example, the encapsulant may be an Epoxy (Epoxy), but the invention is not limited thereto.
Advantageous effects of the embodiments
One of the advantages of the present invention is that the test interface board assembly and the manufacturing method thereof according to the embodiment of the present invention can utilize the technical scheme that the first circuit layer 3 is embedded in the dielectric layer 2, so as to improve the reliability of the first circuit layer 3.
In addition, the present invention can also utilize the technical scheme of firstly forming a first circuit layer 3 on the surface 11 of the substrate 1 and then removing a part of the substrate 1 to expose an exposed surface 31 of the first circuit layer 3, thereby improving the quality of the electrical connection and the accuracy of the fine pitch. Meanwhile, compared with the manufacturing process for manufacturing the micro-spacing in the prior art, the manufacturing process can be simplified, and the yield of the whole test interface board assembly U is improved.
In addition, because the first circuit layer 3 with the highest requirement on the dimensional precision is formed in the fan-out mode, compared with the contact test pad formed in the fan-in mode in the prior art, the contact test pad can obtain a complete plane, and a good contact test pad plane is generated.
Furthermore, since the first circuit layer 3 is embedded in the dielectric layer 2 and is wrapped by the dielectric layer 2 to form an embedded structure, the reliability of the first circuit layer 3 can be improved, and the first circuit layer 3 is not easily damaged. Meanwhile, the fan-out mode is adopted to form the test interface board assembly U, so that the problem of overlarge overall thickness caused by the arrangement of the core substrate in the prior art can be solved. Therefore, the thickness is reduced, so that the transmission path can be shortened, the problem of high inductance can be solved, and the characteristic impedance control and the control of the integrity of the power supply can be facilitated.
Further, after removing a portion of the substrate 1 to expose an exposed surface 31 of the first circuit layer 3, another portion of the substrate 1 disposed on the dielectric layer 2 may be utilized as a basis and a location for subsequent assembly of the probe assembly T, which is helpful for controlling the horizontal position of the probe T2.
In addition, the test interface board assembly and the manufacturing method thereof provided by the present invention can also expose the exposed surface 31 of the first circuit layer 3 by "removing a portion of the substrate 1; arranging a chip unit C to be electrically connected to the exposed surface 31 of the first circuit layer 3, wherein the chip unit C is positioned in the accommodating space S surrounded by the other part of the substrate 1; and arranging the packaging unit 9 on the other part of the substrate 1 to seal the accommodating space S ″ and directly form a packaging component P for packaging the chip unit C.
The disclosure is only a preferred embodiment of the invention, and is not intended to limit the scope of the claims, so that all technical equivalents and modifications using the contents of the specification and drawings are included in the scope of the claims.
Claims (5)
1. A method of manufacturing a test interface board assembly, the method comprising:
providing a substrate, wherein the substrate is provided with a surface;
forming a first circuit layer on the surface of the substrate;
forming a dielectric layer to cover the first circuit layer and the surface of the substrate;
forming a first conductive structure to be electrically connected to the first circuit layer;
forming an amplification layer to cover the dielectric layer and the first conductive structure such that the first conductive structure is located between the dielectric layer and the amplification layer;
forming a second conductive structure to be electrically connected to the first conductive structure;
forming a solder mask layer on the amplification layer, wherein the solder mask layer covers the second conductive structure;
forming a second circuit layer on the solder mask layer, wherein the second circuit layer is electrically connected to the second conductive structure;
removing a part of the substrate to expose an exposed surface of the first circuit layer;
arranging a chip unit to be electrically connected to the exposed surface of the first circuit layer, wherein the chip unit is positioned in an accommodating space surrounded by the other part of the substrate; and
arranging a packaging unit on the other part of the substrate to seal the accommodating space;
wherein the packaging unit is arranged on the other part of the substrate through an adhesive layer.
2. The method of manufacturing a test interface board assembly of claim 1, wherein in the step of forming the first conductive structure comprises:
forming a first conductive portion in the dielectric layer, wherein the first conductive portion of the first conductive structure is electrically connected to the first circuit layer; and
forming a second conductive portion on the dielectric layer, wherein the second conductive portion of the first conductive structure is electrically connected to the first conductive portion of the first conductive structure.
3. The method of manufacturing a test interface board assembly of claim 2, wherein in the step of forming the second conductive structure comprises:
forming a first conductive portion in the amplification layer, wherein the first conductive portion of the second conductive structure is electrically connected to the second conductive portion of the first conductive structure; and
and forming a second conductive part on the amplification layer, wherein the second conductive part of the second conductive structure is electrically connected with the first conductive part of the second conductive structure.
4. A method of manufacturing a test interface board assembly, the method comprising:
providing a substrate, wherein the substrate is provided with a surface;
forming a first circuit layer on the surface of the substrate;
forming a dielectric layer to cover the first circuit layer and the surface of the substrate;
forming a conductive structure electrically connected to the first circuit layer and an amplification layer between the dielectric layer and the conductive structure;
forming a second circuit layer on the amplification layer, wherein the second circuit layer is electrically connected to the first circuit layer through the conductive structure;
removing a part of the substrate to expose an exposed surface of the first circuit layer;
arranging a chip unit to be electrically connected to the exposed surface of the first circuit layer, wherein the chip unit is positioned in an accommodating space surrounded by the other part of the substrate; and
arranging a packaging unit on the other part of the substrate to seal the accommodating space;
wherein the packaging unit is arranged on the other part of the substrate through an adhesive layer.
5. The method of manufacturing a test interface board assembly of claim 4, wherein in the step of forming the conductive structure and the amplification layer, further comprising:
forming a solder mask layer on the amplification layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106121585A TWI612599B (en) | 2017-06-28 | 2017-06-28 | Testing board component and manufacturing method thereof |
| TW106121585 | 2017-06-28 |
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| Publication Number | Publication Date |
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| CN109148357A CN109148357A (en) | 2019-01-04 |
| CN109148357B true CN109148357B (en) | 2021-12-17 |
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| CN201710546928.3A Active CN109148357B (en) | 2017-06-28 | 2017-07-06 | Test interface board assembly and manufacturing method thereof |
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| TWI721424B (en) * | 2018-05-23 | 2021-03-11 | 旺矽科技股份有限公司 | Space transformer, probe card, and manufacturing methods thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104851814A (en) * | 2014-02-13 | 2015-08-19 | 台湾积体电路制造股份有限公司 | Integrated circuit package and methods of forming same |
| CN106229309A (en) * | 2016-07-20 | 2016-12-14 | 日月光半导体(上海)有限公司 | Base plate for packaging and manufacture method thereof |
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| JP5561460B2 (en) * | 2009-06-03 | 2014-07-30 | 新光電気工業株式会社 | Wiring board and method for manufacturing wiring board |
| CN102324407A (en) * | 2011-09-22 | 2012-01-18 | 日月光半导体制造股份有限公司 | Semiconductor packaging piece and manufacturing method thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104851814A (en) * | 2014-02-13 | 2015-08-19 | 台湾积体电路制造股份有限公司 | Integrated circuit package and methods of forming same |
| CN106229309A (en) * | 2016-07-20 | 2016-12-14 | 日月光半导体(上海)有限公司 | Base plate for packaging and manufacture method thereof |
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| TWI612599B (en) | 2018-01-21 |
| TW201906037A (en) | 2019-02-01 |
| CN109148357A (en) | 2019-01-04 |
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