CN204214960U - A kind of device detected for merge cells - Google Patents
A kind of device detected for merge cells Download PDFInfo
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- CN204214960U CN204214960U CN201420519605.7U CN201420519605U CN204214960U CN 204214960 U CN204214960 U CN 204214960U CN 201420519605 U CN201420519605 U CN 201420519605U CN 204214960 U CN204214960 U CN 204214960U
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Abstract
The utility model discloses a kind of device detected for merge cells, belong to field of power detection.By embedded system module installation running parameter, optical Ethernet transceiver module receives the first message data and is sent to the first data processing module, first data processing module is by obtaining the first final data to the first message data calculation process, light serial ports transceiver module receives the second message Data Concurrent and delivers to the second data processing module, second data processing module is by obtaining the second final data to the second message data operation process, second final data is sent to the first data processing module, first final data and the second final data are sent to embedded system module by the first data processing module, be sent to touch-screen again, embedded system module obtains ROMPaq from memory module and carries out system upgrade.The utility model, by described a kind of device detected for merge cells, improves software updating efficiency.
Description
Technical field
The utility model relates to instrument check field, particularly a kind of device detected for merge cells.
Background technology
Merge cells is that the electric parameters transmitted mutual inductor in digital transformer substation carries out merging and synchronous process, and the digital signal after process is given to the device of bay device use according to specific format, achieve sharing and digitizing of process layer data to a certain extent, it, as following the digital substation interval layer of IEC61850 standard, the Data Source of station level equipment, acts on very important.And towards transformer substation case GOOSE (the Generic Object Oriented Substation Event of general object, transformer substation case towards general object) technology and sampled value IEC61850 (9-1,9-2) transmission technology be the most important two kinds of technology applied process layer of digitalization transformer substation.In addition also have IEC60044-7/8 (FT3) host-host protocol and GPS, B code, 1588 isochronon messages, in merge cells testing process, equally there is importance.
At present, the equipment for combining data detection unit is more and more extensive, but upgrade software carries out after all needing to connect computing machine by mode interface again, and upgrade software efficiency is in urgent need to be improved.
Utility model content
The purpose of this utility model there are provided a kind of device detected for merge cells, is intended to solve the existing device software detected for merge cells and upgrades inefficient problem.
The utility model is achieved in that a kind of device detected for merge cells, comprising:
For providing the power module of supply voltage;
For showing the touch-screen of test function, test parameter, the first final data and the second final data;
For selecting the keyboard of described test function and described test parameter;
For storing the memory module of ROMPaq;
For arranging the running parameter of the first data processing module and the second data processing module, described first final data received and described second final data are sent to described touch-screen, and obtains from described memory module the embedded system module that described ROMPaq carries out system upgrade;
For by input the first message data calculation process obtain described first final data, described second final data of described first final data and reception is sent to described embedded system module, and according to described test parameter matching the 3rd message data, by the first data processing module that described 3rd message data sends;
For by input the second message data operation process obtain described second final data, described second final data is sent to described first data processing module, and according to described test parameter matching the 4th message data, by the second data processing module that described 4th message data sends;
For communicating to receive described first message data with external lan by optical Ethernet interface and described first message data being sent to described first data processing module, communicate with described first data processing module to receive described 3rd message data, and the 3rd message data is sent to the optical Ethernet transceiver module of described external lan;
For communicating to receive described second message data with external lan by optical Ethernet interface and described second message data being sent to described second data processing module, communicate with described second data processing module to receive described 4th message data, and the 4th message data is sent to the light serial ports transceiver module of described external lan;
Described power module is connected with described embedded system module, described first data processing module and described second data processing module, described smooth serial ports transceiver module is connected with described second data processing module, described optical Ethernet transceiver module is connected with described first data processing module, described first data processing module and described embedded system model calling, described embedded system module is connected with described touch-screen, described memory module and described keyboard.
The beneficial effect that the technical scheme that the utility model provides is brought is:
From above-mentioned the utility model, due to the running parameter by embedded system module installation first data processing module and the second data processing module, optical Ethernet transceiver module is used for communicating to receive the first message data with external lan by optical Ethernet interface and the first message data being sent to the first data processing module, first data processing module is by obtaining the first final data to the first message data calculation process of input, light serial ports transceiver module communicates to receive the second message data with external lan by optical Ethernet interface and the second message data is sent to the second data processing module, second data processing module is by obtaining the second final data to the second message data operation process of input, second final data is sent to the first data processing module, second final data of the first final data and reception is sent to embedded system module by the first data processing module, embedded system module is sent to touch-screen again, 3rd message data according to test parameter matching the 3rd message data, then is sent to optical Ethernet transceiver module by the first data processing module, 4th message data, according to test parameter matching the 4th message data, is sent to light serial ports transceiver module by the second data processing module, embedded system module obtains ROMPaq from memory module and carries out system upgrade, this improves software updating efficiency.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the utility model embodiment, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the theory diagram of a kind of device first embodiment for merge cells detection of the utility model;
Fig. 2 is the circuit diagram of a kind of installation's power source module for merge cells detection of the utility model;
Fig. 3 is the circuit diagram of a kind of device optical Ethernet transceiver module for merge cells detection of the utility model.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearly, below in conjunction with accompanying drawing, the utility model embodiment is described in further detail.
The theory diagram of a kind of device first embodiment for merge cells detection of the utility model, see Fig. 1, comprising: for providing the power module 01 of supply voltage; For showing the touch-screen 05 of test function, test parameter, the first final data and the second final data; For selecting the keyboard 04 of test function and test parameter; For storing the memory module 03 of ROMPaq; For arranging the running parameter of the first data processing module 06 and the second data processing module 08, the first final data received and the second final data are sent to touch-screen 05, and obtains from memory module 03 the embedded system module 02 that ROMPaq carries out system upgrade; For by input the first message data calculation process obtain the first final data, second final data of the first final data and reception is sent to embedded system module 02, and according to test parameter matching the 3rd message data, by the first data processing module 06 that the 3rd message data sends; For by input the second message data operation process obtain the second final data, second final data is sent to the first data processing module 06, and according to test parameter matching the 4th message data, by the second data processing module 08 that the 4th message data sends; For communicating to receive the first message data with external lan by optical Ethernet interface and the first message data being sent to the first data processing module 06, communicate to receive the 3rd message data with the first data processing module 06, and the 3rd message data is sent to the optical Ethernet transceiver module 07 of external lan; For communicating to receive the second message data with external lan by optical Ethernet interface and the second message data being sent to the second data processing module 08, communicate to receive the 4th message data with the second data processing module 08, and the 4th message data is sent to the light serial ports transceiver module 09 of external lan.
Power module 01 is connected with embedded system module 02, first data processing module 06 and the second data processing module 08, light serial ports transceiver module 09 is connected with the second data processing module 08, optical Ethernet transceiver module 07 is connected with the first data processing module 06, first data processing module 06 is connected with embedded system module 02, and embedded system module 02 is connected with touch-screen 05, memory module 03 and keyboard 04.
The first above-mentioned message data and the 3rd message data are IEC61850 (9-1,9-2), GOOSE, GMRP data of standard, and the second above-mentioned message data and the 4th message data are IEC60044-7/8 (FT3) data of standard.
In concrete enforcement, the first above-mentioned data processing module can be DSP (Digital Signal Process, digital signal processing) data processing module, the second above-mentioned data processing module can be FPGA (Field-Programmable Gate Array, field programmable gate array) data processing module, memory module can be SD card.
In concrete enforcement, embedded system module is connected by rgb interface with touch-screen, light serial ports transceiver module is connected by Ethernet interface with the second data processing module, optical Ethernet transceiver module is connected by Ethernet interface with the first data processing module, embedded system module and the first data processing module are by Ethernet interface, serial line interface and SPORT (synchronous serial ports, synchronous serial interface) interface connection, the second data processing module is connected by SPORT interface with the first data processing module.
It is as follows that first message data receives operation: by the running parameter of embedded system module installation first data processing module, first data processing module buttress receives external data according to running parameter by optical Ethernet optical transceiver module and carries out analyzing and processing, by procotol, RS232 and SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) communications feedback result is to embedded system module, shown by touch screen interface again, thus complete the first message data dissection process.
3rd message data transmit operation is as follows: by the running parameter of embedded system module installation first data processing module, first data processing module buttress is according to running parameter matching message data, sent by optical Ethernet optical transceiver module, by procotol, RS232 and SPI communications feedback to embedded system module, again by touch screen interface display current message parameter, thus complete the 3rd message data matching transmission.
Second message data reception operation is as follows: by the running parameter of embedded system module installation first data processing module and the second data processing module, first data processing module carries out exchanges data according to running parameter by SPORT interface and the second data processing module, second data processing module receives external data by light serial ports transceiver module and carries out analyzing and processing, last first data processing module by RS232 and SPI communications feedback result to embedded system module, again by touch screen interface display current message parameter, thus complete the second message Data Analysis process.
4th message data transmit operation is as follows: by the running parameter of embedded system module installation first data processing module and the second data processing module, first data processing module buttress carries out exchanges data according to running parameter by SPORT interface and the second data processing module, data are sent external lan after data processing by light serial ports transceiver module by the second data processing module, thus complete the 4th message data analytic message matching transmission.
IRIG-B code or the operation of PPS synchronism output as follows: by the running parameter of embedded system module installation first data processing module and the second data processing module, first data processing module buttress carries out exchanges data according to running parameter by SPORT interface and the second data processing module, second data processing module receives external data by light serial ports transceiver module and carries out analyzing and processing, last first data processing module passes through according to the clock be resolved to, interval sends corresponding message, completes synchronism output.
IRIG-B code or PPS clock parse operation as follows: by the parameter of embedded system module installation first data processing module and the second data processing module, first data processing module buttress carries out exchanges data according to according to parameter by SPORT interface and the second data processing module, second data processing module receives external data by light serial ports transceiver module and carries out analyzing and processing, last first data processing module by RS232 and SPI communications feedback result to embedded system module, show current message parameter by touch screen interface again, thus complete clock dissection process.
Power module comprises power management chip PU1, first LED 34, diode D6, first inductance PL1, first electric capacity PC1, second electric capacity PC2, 3rd electric capacity PC3, 4th electric capacity PC4, 5th electric capacity PC5, 6th electric capacity PC6, first resistance PR1, second resistance PR4, 3rd resistance PR5, 4th resistance PR6, 5th resistance PR7, 6th resistance PR8, 7th resistance PR9, 8th resistance PR10, 9th resistance PR11, tenth resistance PR12, 11 resistance PR13, 12 resistance PR14 and the 13 resistance PR15, the charging Input voltage terminal of power management chip PU1 and the first power supply, the first end of the first electric capacity PC1, the first end of the second resistance PR4, the first end of the first resistance PR1, the analog device power input of power management chip PU1, the first end of the 3rd electric capacity PC3 connects, the charging first state end of power management chip PU1 is connected with the first negative electrode of the first LED 34, the charging second state end of power management chip PU1 is connected with the second negative electrode of the first LED 34, the timing of power management chip PU1 is connected with the first end of the second electric capacity PC2 with termination control end, the Enable Pin of power management chip PU1 and the analog device power ground end of power management chip PU1, second end of the second electric capacity PC2, second end of the 3rd electric capacity PC3, the first end of the 4th electric capacity PC4, the first end of the 3rd resistance PR5, the first end of the 4th resistance PR6, the first end of the 6th electric capacity PC6, the first end of the 6th resistance PR8, the first end of the 9th resistance PR11, the first end of the tenth resistance PR12, the first end of the 11 resistance PR13, the first end of the 12 resistance PR14, the first end of the 13 resistance PR15 connects altogether, the output voltage analog feedback adjustable side of power management chip PU1 and the first end of the 8th resistance PR10, second end of the 9th resistance PR11 connects, the charging current outputting inductance link of power management chip PU1 and the negative electrode of diode D6, the first end of the first inductance PL1 connects, the power supply ground input end of power management chip PU1 and the anode of diode D6, the first end of the 5th electric capacity PC5, second end of the first electric capacity PC1, second end of the second resistance PR4, second end of the tenth resistance PR12, second end of the 11 resistance PR13, second end of the 12 resistance PR14, second end of the 13 resistance PR15 connects and power supply ground altogether, the current sample input end of power management chip PU1 and second end of the first inductance PL1, second end of the 5th electric capacity PC5, the first end of the 7th resistance PR9, second end of the 6th electric capacity PC6 connects, the battery voltage sampling input end of power management chip PU1 and second end of the 7th resistance PR9, second end of the 8th resistance PR10 is the voltage output end connection of power module, the charging current first of power management chip PU1 arranges end and is connected with second end of the 3rd resistance PR5, the charging current second of power management chip PU1 arranges end and is connected with second end of the 4th resistance PR6, the temperature detection input end of power management chip PU1 and the first end of the 5th resistance PR7, the first end of the 6th resistance PR8 connects, the temperature detection internal adjustment voltage end of power management chip PU1 and second end of the 4th electric capacity PC4, second end of the 5th resistance PR7 connects, and second end of the first resistance PR1 is connected with the anode of light emitting diode LED34.In concrete enforcement, power management chip can be the power management chip that model is BQ24105IRHLRQ1.
Because the first power supply can be the battery of 12V, can on-the-spot little simulation electric energy meter and digitalized electrical energy meter be verified so achieve.
Optical Ethernet optical transceiver module comprises transceiver U402, exclusion RA403, the second light emitting diode LED7, the 3rd LED 8, second inductance L 404, the 3rd inductance L 405, the 7th electric capacity C412, the 8th electric capacity C416, the 9th electric capacity C417, the tenth electric capacity C418, the 11 electric capacity C421, the 14 resistance R411, the 15 resistance R414, the 16 resistance R415, the 17 resistance R416, the 18 resistance R413, the reception data first end of transceiver U402 is the first output terminal of optical Ethernet transceiver module, reception data second end of transceiver U402 is the second output terminal of optical Ethernet transceiver module, reception data the 3rd end of transceiver U402 is the 3rd output terminal of optical Ethernet transceiver module, reception data the 4th end of transceiver U402 is the 4th output terminal of optical Ethernet transceiver module, the receive clock end of transceiver U402 is the 5th output terminal of optical Ethernet transceiver module, the carrier sense end of transceiver U402 is the 6th output terminal of optical Ethernet transceiver module, the collision detection end of transceiver U402 is the 7th output terminal of optical Ethernet transceiver module, the reception data live end of transceiver U402 is the 8th output terminal of optical Ethernet transceiver module, the transfer clock end of transceiver U402 is the 9th output terminal of optical Ethernet transceiver module, the transmission Enable Pin of transceiver U402 is the first input end of optical Ethernet transceiver module, the transmission data first end of transceiver U402 is the second input end of optical Ethernet transceiver module, transmission data second end of transceiver U402 is the 3rd input end of optical Ethernet transceiver module, transmission data the 3rd end of transceiver U402 is the four-input terminal of optical Ethernet transceiver module, transmission data the 4th end of transceiver U402 is the 5th input end of optical Ethernet transceiver module, the data incoming/outgoing management end of transceiver U402 is the first input/output terminal of optical Ethernet transceiver module, the data management clock end of transceiver U402 is the 6th input end of optical Ethernet transceiver module, optical fiber/UTP the Enable Pin of transceiver U402 is connected with the 14 resistance R411 first end, 14 resistance R411 second end, the 3.3V digital power input end of transceiver U402, 8th pin of exclusion 403, the first end of the 17 resistance R416, the first end of the 3rd inductance L 405 is connected to second source altogether, the 25MHz crystal oscillator input end of transceiver U402 is the 7th input end of optical Ethernet transceiver module, the power supply feedback output terminal of transceiver U402 and the first end of the second inductance L 404, the first end of the 7th electric capacity C412, the first end of the 8th electric capacity C416 connects, the power supply feedback input end of transceiver U402 and the second end of the second inductance L 404, the first end of the 11 electric capacity C421 connects, second end of the 7th electric capacity C412, second end of the 8th electric capacity C416, second end of the 11 electric capacity C421, the first end of the 9th electric capacity C417, the first end of the tenth electric capacity C418, the negative electrode of the second LED 7, the first end of the 15 resistance R414, 2nd pin of exclusion RA403, 4th pin of exclusion RA403, 6th pin of exclusion RA403, the first end of the 18 resistance R413 is connected to power supply ground altogether, the 3.3V analog power input end of transceiver U402 and second end of the 9th electric capacity C417, second end of the tenth electric capacity C418, second end of the 3rd inductance L 405 connects, the transmission output cathode end of transceiver U402 is the tenth output terminal of optical Ethernet transceiver module, the transmission output negative pole end of transceiver U402 is the 11 output terminal of optical Ethernet transceiver module, the reception input positive terminal of transceiver U402 is the 8th input end of optical Ethernet transceiver module, the reception input negative pole end of transceiver U402 is the 9th input end of optical Ethernet transceiver module, the conflict LED end of transceiver U402 is connected with exclusion the 1st pin, the connection 100/ACT LED of transceiver U402 holds and the 15 resistance R414 second end, 16 resistance R415 first end connects, the connection 10/ACT LED end of transceiver U402 is connected with exclusion the 3rd pin, the full duplex LED end of transceiver U402 is connected with exclusion the 5th pin, the connection LED of transceiver U402 holds and exclusion the 7th pin, 3rd LED 8 negative electrode connects, first of transceiver U402 latches end, second of transceiver U402 latches end, the 3rd of transceiver U402 latches end, the battery saving mode end that goes offline of transceiver U402, the 4th of transceiver U402 latches end and is connected to second source altogether, the transmission bias resistor link of transceiver U402 is connected with second end of the 18 resistance R413, the reset terminal of transceiver U402 is the tenth input end of optical Ethernet transceiver module, 16 resistance R415 second end is connected with the anode of the second LED 7, second end of the 17 resistance R416 is connected with the anode of the 3rd LED 8.In concrete enforcement, transceiver can be the transceiver that model is RTL8201.
The utility model embodiment passes through the running parameter of embedded system module installation first data processing module and the second data processing module, optical Ethernet transceiver module is used for communicating to receive the first message data with external lan by optical Ethernet interface and the first message data being sent to the first data processing module, first data processing module is by obtaining the first final data to the first message data calculation process of input, light serial ports transceiver module communicates to receive the second message data with external lan by optical Ethernet interface and the second message data is sent to the second data processing module, second data processing module is by obtaining the second final data to the second message data operation process of input, second final data is sent to the first data processing module, second final data of the first final data and reception is sent to embedded system module by the first data processing module, embedded system module is sent to touch-screen again, 3rd message data according to test parameter matching the 3rd message data, then is sent to optical Ethernet transceiver module by the first data processing module, 4th message data, according to test parameter matching the 4th message data, is sent to light serial ports transceiver module by the second data processing module, embedded system module obtains ROMPaq from memory module and carries out system upgrade, this improves software updating efficiency.
Above-mentioned the utility model embodiment sequence number, just to describing, does not represent the quality of embodiment.
One of ordinary skill in the art will appreciate that all or part of step realizing above-described embodiment can have been come by hardware, the hardware that also can carry out instruction relevant by program completes, described program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium mentioned can be ROM (read-only memory), disk or CD etc.
The foregoing is only preferred embodiment of the present utility model, not in order to limit the utility model, all within spirit of the present utility model and principle, any amendment done, equivalent replacement, improvement etc., all should be included within protection domain of the present utility model.
Claims (8)
1., for the device that merge cells detects, it is characterized in that, comprising:
For providing the power module of supply voltage;
For showing the touch-screen of test function, test parameter, the first final data and the second final data;
For selecting the keyboard of described test function and described test parameter;
For storing the memory module of ROMPaq;
For arranging the running parameter of the first data processing module and the second data processing module, described first final data received and described second final data are sent to described touch-screen, and obtains from described memory module the embedded system module that described ROMPaq carries out system upgrade;
For by input the first message data calculation process obtain described first final data, described second final data of described first final data and reception is sent to described embedded system module, and according to described test parameter matching the 3rd message data, by the first data processing module that described 3rd message data sends;
For by input the second message data operation process obtain described second final data, described second final data is sent to described first data processing module, and according to described test parameter matching the 4th message data, by the second data processing module that described 4th message data sends;
For communicating to receive described first message data with external lan by optical Ethernet interface and described first message data being sent to described first data processing module, communicate with described first data processing module to receive described 3rd message data, and the 3rd message data is sent to the optical Ethernet transceiver module of described external lan;
For communicating to receive described second message data with external lan by optical Ethernet interface and described second message data being sent to described second data processing module, communicate with described second data processing module to receive described 4th message data, and the 4th message data is sent to the light serial ports transceiver module of described external lan;
Described power module is connected with described embedded system module, described first data processing module and described second data processing module, described smooth serial ports transceiver module is connected with described second data processing module, described optical Ethernet transceiver module is connected with described first data processing module, described first data processing module and described embedded system model calling, described embedded system module is connected with described touch-screen, described memory module and described keyboard.
2. the device detected for merge cells according to claim 1, it is characterized in that, described embedded system module is connected by rgb interface with described touch-screen.
3. the device detected for merge cells according to claim 1, it is characterized in that, described smooth serial ports transceiver module is connected by Ethernet interface with described second data processing module.
4. the device detected for merge cells according to claim 1, it is characterized in that, described optical Ethernet transceiver module is connected by Ethernet interface with described first data processing module.
5. the device detected for merge cells according to claim 1, it is characterized in that, described embedded system module is connected by Ethernet interface, serial line interface and SPORT interface with described first data processing module.
6. the device detected for merge cells according to claim 1, it is characterized in that, described second data processing module is connected by SPORT interface with described first data processing module.
7. the device detected for merge cells according to claim 1, it is characterized in that, described power module comprises power management chip, the first light emitting diode, diode, the first inductance, the first electric capacity, the second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the 6th electric capacity, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the 9th resistance, the tenth resistance, the 11 resistance, the 12 resistance and the 13 resistance;
The charging Input voltage terminal of described power management chip and the first power supply, the first end of described first electric capacity, the first end of described second resistance, the first end of described first resistance, the analog device power input of described power management chip, the first end of described 3rd electric capacity connects, the charging first state end of described power management chip is connected with the first negative electrode of described first light emitting diode, the charging second state end of described power management chip is connected with the second negative electrode of described first light emitting diode, the timing of described power management chip is connected with the first end of described second electric capacity with termination control end, the Enable Pin of described power management chip and the analog device power ground end of described power management chip, second end of described second electric capacity, second end of described 3rd electric capacity, the first end of described 4th electric capacity, the first end of described 3rd resistance, the first end of described 4th resistance, the first end of described 6th electric capacity, the first end of described 6th resistance, the first end of described 9th resistance, the first end of described tenth resistance, the first end of described 11 resistance, the first end of described 12 resistance, the first end of described 13 resistance connects altogether, the output voltage analog feedback adjustable side of described power management chip and the first end of described 8th resistance, second end of described 9th resistance connects, the charging current outputting inductance link of described power management chip and the negative electrode of described diode, the first end of described first inductance connects, the power supply ground input end of described power management chip and the anode of described diode, the first end of described 5th electric capacity, second end of described first electric capacity, second end of described second resistance, second end of described tenth resistance, second end of described 11 resistance, second end of described 12 resistance, second end of described 13 resistance connects and power supply ground altogether, the current sample input end of described power management chip and the second end of described first inductance, second end of described 5th electric capacity, the first end of described 7th resistance, second end of described 6th electric capacity connects, the battery voltage sampling input end of described power management chip and the second end of described 7th resistance, second end of described 8th resistance is the voltage output end connection of power module, the charging current first of described power management chip arranges end and is connected with the second end of described 3rd resistance, the charging current second of described power management chip arranges end and is connected with the second end of described 4th resistance, the temperature detection input end of described power management chip and the first end of described 5th resistance, the first end of described 6th resistance connects, the temperature detection internal adjustment voltage end of described power management chip and the second end of described 4th electric capacity, second end of described 5th resistance connects, and the second end of described first resistance is connected with the anode of described light emitting diode.
8. the device detected for merge cells according to claim 1, it is characterized in that, described optical Ethernet transceiver module comprises transceiver, exclusion, the second light emitting diode, the 3rd light emitting diode, the second inductance, the 3rd inductance, the 7th electric capacity, the 8th electric capacity, the 9th electric capacity, the tenth electric capacity, the 11 electric capacity, the 14 resistance, the 15 resistance, the 16 resistance, the 17 resistance, the 18 resistance;
The reception data first end of described transceiver is the first output terminal of described optical Ethernet transceiver module, reception data second end of described transceiver is the second output terminal of described optical Ethernet transceiver module, reception data the 3rd end of described transceiver is the 3rd output terminal of described optical Ethernet transceiver module, reception data the 4th end of described transceiver is the 4th output terminal of described optical Ethernet transceiver module, the receive clock end of described transceiver is the 5th output terminal of described optical Ethernet transceiver module, the carrier sense end of described transceiver is the 6th output terminal of described optical Ethernet transceiver module, the collision detection end of described transceiver is the 7th output terminal of described optical Ethernet transceiver module, the reception data live end of described transceiver is the 8th output terminal of described optical Ethernet transceiver module, the transfer clock end of described transceiver is the 9th output terminal of described optical Ethernet transceiver module, the transmission Enable Pin of described transceiver is the first input end of described optical Ethernet transceiver module, the transmission data first end of described transceiver is the second input end of described optical Ethernet transceiver module, transmission data second end of described transceiver is the 3rd input end of described optical Ethernet transceiver module, transmission data the 3rd end of described transceiver is the four-input terminal of described optical Ethernet transceiver module, transmission data the 4th end of described transceiver is the 5th input end of described optical Ethernet transceiver module, the data incoming/outgoing management end of described transceiver is the first input/output terminal of described optical Ethernet transceiver module, the data management clock end of described transceiver is the 6th input end of described optical Ethernet transceiver module, optical fiber/UTP the Enable Pin of described transceiver is connected with described 14 resistance first end, described 14 resistance second end, the 3.3V digital power input end of described transceiver, 8th pin of described exclusion, the first end of described 17 resistance, the first end of described 3rd inductance is connected to second source altogether, the 25MHz crystal oscillator input end of described transceiver is the 7th input end of described optical Ethernet transceiver module, the power supply feedback output terminal of described transceiver and the first end of described second inductance, the first end of described 7th electric capacity, the first end of described 8th electric capacity connects, the power supply feedback input end of described transceiver and the second end of described second inductance, the first end of described 11 electric capacity connects, second end of described 7th electric capacity, second end of described 8th electric capacity, second end of described 11 electric capacity, the first end of described 9th electric capacity, the first end of described tenth electric capacity, the negative electrode of described second light emitting diode, the first end of described 15 resistance, 2nd pin of described exclusion, 4th pin of described exclusion, 6th pin of described exclusion, the first end of described 18 resistance is connected to power supply ground altogether, the 3.3V analog power input end of described transceiver and the second end of described 9th electric capacity, second end of described tenth electric capacity, second end of described 3rd inductance connects, the transmission output cathode end of described transceiver is the tenth output terminal of described optical Ethernet transceiver module, the transmission output negative pole end of described transceiver is the 11 output terminal of described optical Ethernet transceiver module, the reception input positive terminal of described transceiver is the 8th input end of described optical Ethernet transceiver module, the reception input negative pole end of described transceiver is the 9th input end of described optical Ethernet transceiver module, the conflict LED end of described transceiver is connected with exclusion the 1st pin, the connection 100/ACT LED of described transceiver holds and described 15 resistance second end, described 16 resistance first end connects, the connection 10/ACT LED end of described transceiver is connected with exclusion the 3rd pin, the full duplex LED end of described transceiver is connected with exclusion the 5th pin, the connection LED of described transceiver holds and exclusion the 7th pin, described 3rd light-emitting diodes tube cathode connects, first of described transceiver latches end, second of described transceiver latches end, the 3rd of described transceiver latches end, the battery saving mode end that goes offline of described transceiver, the 4th of described transceiver latches end and is connected to described second source altogether, the transmission bias resistor link of described transceiver is connected with the second end of described 18 resistance, the reset terminal of described transceiver is the tenth input end of described optical Ethernet transceiver module, described 16 resistance second end is connected with the anode of described second light emitting diode, second end of described 17 resistance is connected with the anode of described 3rd light emitting diode.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420519605.7U CN204214960U (en) | 2014-09-10 | 2014-09-10 | A kind of device detected for merge cells |
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| CN201420519605.7U CN204214960U (en) | 2014-09-10 | 2014-09-10 | A kind of device detected for merge cells |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107525978A (en) * | 2016-06-22 | 2017-12-29 | 辽宁省送变电工程公司 | A kind of combining unit transient current method of testing and device based on transient state source |
| CN110413036A (en) * | 2018-04-27 | 2019-11-05 | 华为技术有限公司 | Adjust the device and electronic equipment of voltage |
-
2014
- 2014-09-10 CN CN201420519605.7U patent/CN204214960U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107525978A (en) * | 2016-06-22 | 2017-12-29 | 辽宁省送变电工程公司 | A kind of combining unit transient current method of testing and device based on transient state source |
| CN110413036A (en) * | 2018-04-27 | 2019-11-05 | 华为技术有限公司 | Adjust the device and electronic equipment of voltage |
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