CN204203830U - A kind of high power LD O circuit error amplifier - Google Patents
A kind of high power LD O circuit error amplifier Download PDFInfo
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- CN204203830U CN204203830U CN201420720395.8U CN201420720395U CN204203830U CN 204203830 U CN204203830 U CN 204203830U CN 201420720395 U CN201420720395 U CN 201420720395U CN 204203830 U CN204203830 U CN 204203830U
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Abstract
The utility model is to provide a kind of high power LD O circuit error amplifier, comprise 7 P type metal-oxide-semiconductors and 4 N-type metal-oxide-semiconductors, the utility model structure is simple, the function of error amplifier is achieved by 7 P type metal-oxide-semiconductors and being connected of 4 N-type metal-oxide-semiconductors, then decrease power consumption by the use of metal-oxide-semiconductor, effectively ensure that the output power of high-power LOD finally by metal-oxide-semiconductor power device.
Description
Technical field
The utility model relates to microelectronics technology, particularly relates to a kind of high power LD O circuit error amplifier.
Background technology
LDO is a kind of linear voltage regulator, and error amplifier is the necessary component of LDO.
If pressure drop is too large, consume energy on LDO too large, output power will reduce.Use MOS (metal-oxide-semiconductor), the ON resistance being power-supply device load current by the unique voltage pressure drop of voltage stabilizer causes.If load is less, the pressure drop that this mode produces only has tens millivolts.So use metal-oxide-semiconductor is a kind of method of effective guarantee output power.
In addition, MOS is voltage driven, does not need electric current, so greatly reduce the electric current of device consumption itself.
Such as Chinese patent discloses a kind of ultralow power consumption error amplifier, application number: 201210388331.8, the applying date: 2012-10-12, and " voltage negative feedback circuit, comprises PMOS pipe M8, divider resistance R3, R4 to this patent notes; Described PMOS pipe M8, its grid, as input end, is connected with current mirroring circuit; Its source electrode meets supply voltage VDD; Its drain electrode is connected with one end of divider resistance R3, and as the output terminal of error amplifier, output voltage signal VOUT ".
But prior art not yet has report: by MOS power device, ensure the error amplifier of the output power of LDO.
Summary of the invention
For the deficiencies in the prior art, the utility model is to provide a kind of and ensures output power and the little error amplifier of power consumption.
For achieving the above object, the utility model is achieved by following technical proposals:
A kind of high power LD O circuit error amplifier, comprise 7 P type metal-oxide-semiconductors and 4 N-type metal-oxide-semiconductors, its circuit connecting mode is:
The drain electrode of the one P type metal-oxide-semiconductor MP1, the source electrode of the 2nd P type metal-oxide-semiconductor MP2 are connected with the source electrode of the 3rd P type metal-oxide-semiconductor MP3; The grid of the 2nd P type metal-oxide-semiconductor MP2 is connected with the input end in the same way of this error amplifier; The grid of the 3rd P type metal-oxide-semiconductor MP3 is connected with the reverse input end of this error amplifier; The drain electrode of the 2nd P type metal-oxide-semiconductor MP2, the source electrode of the 3rd N-type metal-oxide-semiconductor MN3 are connected with the drain electrode of the first N-type metal-oxide-semiconductor MN1; The drain electrode of the 3rd P type metal-oxide-semiconductor MP3, the source electrode of the 4th N-type metal-oxide-semiconductor MN4 are connected with the drain electrode of the second N-type metal-oxide-semiconductor MN2; The drain electrode of the grid of the 4th P type metal-oxide-semiconductor MP4, the grid of the 5th P type metal-oxide-semiconductor MP5, the 6th P type metal-oxide-semiconductor MP6 is connected with the drain electrode of the 3rd N-type metal-oxide-semiconductor MN3; The drain electrode of the 4th P type metal-oxide-semiconductor MP4 is connected with the source electrode of the 6th P type metal-oxide-semiconductor MP6; The drain electrode of the 5th P type metal-oxide-semiconductor MP5 is connected with the source electrode of the 7th P type metal-oxide-semiconductor MP7; The drain electrode of the 7th P type metal-oxide-semiconductor MP7, the drain electrode of the 4th N-type metal-oxide-semiconductor MN4 are connected with the output port Vout of this error amplifier;
The grid of the one P type metal-oxide-semiconductor MP1 is connected with bias voltage Vpb1; The grid of the 6th P type metal-oxide-semiconductor MP6, the grid of the 7th P type metal-oxide-semiconductor MP7 are connected with bias voltage Vpb2; The grid of the first N-type metal-oxide-semiconductor MN1, the grid of the second N-type metal-oxide-semiconductor MN2 are connected with bias voltage Vnb1; The grid of the 3rd N-type metal-oxide-semiconductor MN3, the grid of the 4th N-type metal-oxide-semiconductor MN4 are connected with bias voltage Vnb2;
The source electrode of the source electrode of the one P type metal-oxide-semiconductor MP1, the source electrode of the 4th P type metal-oxide-semiconductor MP4, the 5th P type metal-oxide-semiconductor MP5 is connected with power vd D;
The source electrode of the first N-type metal-oxide-semiconductor MN1, the source electrode of the second N-type metal-oxide-semiconductor MN2 are connected with ground GND.
The beneficial effects of the utility model are: the utility model structure is simple, the function of error amplifier is achieved by 7 P type metal-oxide-semiconductors and being connected of 4 N-type metal-oxide-semiconductors, then decrease power consumption by the use of metal-oxide-semiconductor, effectively ensure that the output power of high-power LOD finally by metal-oxide-semiconductor power device.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is described in further detail.
As shown in Figure 1, a kind of high power LD O circuit error amplifier, comprise 7 P type metal-oxide-semiconductors and 4 N-type metal-oxide-semiconductors, its circuit connecting mode is:
The drain electrode of the one P type metal-oxide-semiconductor MP1, the source electrode of the 2nd P type metal-oxide-semiconductor MP2 are connected with the source electrode of the 3rd P type metal-oxide-semiconductor MP3; The grid of the 2nd P type metal-oxide-semiconductor MP2 is connected with the input end in the same way of this error amplifier; The grid of the 3rd P type metal-oxide-semiconductor MP3 is connected with the reverse input end of this error amplifier; The drain electrode of the 2nd P type metal-oxide-semiconductor MP2, the source electrode of the 3rd N-type metal-oxide-semiconductor MN3 are connected with the drain electrode of the first N-type metal-oxide-semiconductor MN1; The drain electrode of the 3rd P type metal-oxide-semiconductor MP3, the source electrode of the 4th N-type metal-oxide-semiconductor MN4 are connected with the drain electrode of the second N-type metal-oxide-semiconductor MN2; The drain electrode of the grid of the 4th P type metal-oxide-semiconductor MP4, the grid of the 5th P type metal-oxide-semiconductor MP5, the 6th P type metal-oxide-semiconductor MP6 is connected with the drain electrode of the 3rd N-type metal-oxide-semiconductor MN3; The drain electrode of the 4th P type metal-oxide-semiconductor MP4 is connected with the source electrode of the 6th P type metal-oxide-semiconductor MP6; The drain electrode of the 5th P type metal-oxide-semiconductor MP5 is connected with the source electrode of the 7th P type metal-oxide-semiconductor MP7; The drain electrode of the 7th P type metal-oxide-semiconductor MP7, the drain electrode of the 4th N-type metal-oxide-semiconductor MN4 are connected with the output port Vout of this error amplifier;
The grid of the one P type metal-oxide-semiconductor MP1 is connected with bias voltage Vpb1; The grid of the 6th P type metal-oxide-semiconductor MP6, the grid of the 7th P type metal-oxide-semiconductor MP7 are connected with bias voltage Vpb2; The grid of the first N-type metal-oxide-semiconductor MN1, the grid of the second N-type metal-oxide-semiconductor MN2 are connected with bias voltage Vnb1; The grid of the 3rd N-type metal-oxide-semiconductor MN3, the grid of the 4th N-type metal-oxide-semiconductor MN4 are connected with bias voltage Vnb2;
The source electrode of the source electrode of the one P type metal-oxide-semiconductor MP1, the source electrode of the 4th P type metal-oxide-semiconductor MP4, the 5th P type metal-oxide-semiconductor MP5 is connected with power vd D;
The source electrode of the first N-type metal-oxide-semiconductor MN1, the source electrode of the second N-type metal-oxide-semiconductor MN2 are connected with ground GND.
What describe in above-described embodiment and instructions just illustrates principle of the present utility model and most preferred embodiment; under the prerequisite not departing from the utility model spirit and scope; the utility model also has various changes and modifications, and these changes and improvements all fall within the scope of claimed the utility model.
Claims (1)
1. a high power LD O circuit error amplifier, comprise 7 P type metal-oxide-semiconductors and 4 N-type metal-oxide-semiconductors, it is characterized in that, its circuit connecting mode is:
The drain electrode of the one P type metal-oxide-semiconductor MP1, the source electrode of the 2nd P type metal-oxide-semiconductor MP2 are connected with the source electrode of the 3rd P type metal-oxide-semiconductor MP3; The grid of the 2nd P type metal-oxide-semiconductor MP2 is connected with the input end in the same way of this error amplifier; The grid of the 3rd P type metal-oxide-semiconductor MP3 is connected with the reverse input end of this error amplifier; The drain electrode of the 2nd P type metal-oxide-semiconductor MP2, the source electrode of the 3rd N-type metal-oxide-semiconductor MN3 are connected with the drain electrode of the first N-type metal-oxide-semiconductor MN1; The drain electrode of the 3rd P type metal-oxide-semiconductor MP3, the source electrode of the 4th N-type metal-oxide-semiconductor MN4 are connected with the drain electrode of the second N-type metal-oxide-semiconductor MN2; The drain electrode of the grid of the 4th P type metal-oxide-semiconductor MP4, the grid of the 5th P type metal-oxide-semiconductor MP5, the 6th P type metal-oxide-semiconductor MP6 is connected with the drain electrode of the 3rd N-type metal-oxide-semiconductor MN3; The drain electrode of the 4th P type metal-oxide-semiconductor MP4 is connected with the source electrode of the 6th P type metal-oxide-semiconductor MP6; The drain electrode of the 5th P type metal-oxide-semiconductor MP5 is connected with the source electrode of the 7th P type metal-oxide-semiconductor MP7; The drain electrode of the 7th P type metal-oxide-semiconductor MP7, the drain electrode of the 4th N-type metal-oxide-semiconductor MN4 are connected with the output port Vout of this error amplifier;
The grid of the one P type metal-oxide-semiconductor MP1 is connected with bias voltage Vpb1; The grid of the 6th P type metal-oxide-semiconductor MP6, the grid of the 7th P type metal-oxide-semiconductor MP7 are connected with bias voltage Vpb2; The grid of the first N-type metal-oxide-semiconductor MN1, the grid of the second N-type metal-oxide-semiconductor MN2 are connected with bias voltage Vnb1; The grid of the 3rd N-type metal-oxide-semiconductor MN3, the grid of the 4th N-type metal-oxide-semiconductor MN4 are connected with bias voltage Vnb2;
The source electrode of the source electrode of the one P type metal-oxide-semiconductor MP1, the source electrode of the 4th P type metal-oxide-semiconductor MP4, the 5th P type metal-oxide-semiconductor MP5 is connected with power vd D;
The source electrode of the first N-type metal-oxide-semiconductor MN1, the source electrode of the second N-type metal-oxide-semiconductor MN2 are connected with ground GND.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420720395.8U CN204203830U (en) | 2014-11-27 | 2014-11-27 | A kind of high power LD O circuit error amplifier |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420720395.8U CN204203830U (en) | 2014-11-27 | 2014-11-27 | A kind of high power LD O circuit error amplifier |
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| CN204203830U true CN204203830U (en) | 2015-03-11 |
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| CN201420720395.8U Active CN204203830U (en) | 2014-11-27 | 2014-11-27 | A kind of high power LD O circuit error amplifier |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109818488A (en) * | 2019-02-15 | 2019-05-28 | 上海艾为电子技术股份有限公司 | Output-stage circuit |
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2014
- 2014-11-27 CN CN201420720395.8U patent/CN204203830U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109818488A (en) * | 2019-02-15 | 2019-05-28 | 上海艾为电子技术股份有限公司 | Output-stage circuit |
| CN109818488B (en) * | 2019-02-15 | 2020-04-21 | 上海艾为电子技术股份有限公司 | Output stage circuit |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP02 | Change in the address of a patent holder |
Address after: 510663 C2, building 182, science Road, Science Town, Guangzhou hi tech Industrial Development Zone, Guangdong 1003, China Patentee after: GUANGZHOU REACH MICRO-ELECTRONICS TECHNOLOGY Co.,Ltd. Address before: No. 3 international business incubator G 510663 area in Guangdong city of Guangzhou province Luogang District Science City Moon road 209 Patentee before: GUANGZHOU REACH MICRO-ELECTRONICS TECHNOLOGY Co.,Ltd. |
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| CP02 | Change in the address of a patent holder |