CN204188983U

CN204188983U - A kind of high-speed sampling device based on FPGA and PHY chip

Info

Publication number: CN204188983U
Application number: CN201420681697.9U
Authority: CN
Inventors: 沈庆河; 刘辉; 杨波; 刘嵘; 张有平; 何一甲
Original assignee: State Grid Corp of China SGCC; Electric Power Research Institute of State Grid Shandong Electric Power Co Ltd
Current assignee: State Grid Corp of China SGCC; Electric Power Research Institute of State Grid Shandong Electric Power Co Ltd
Priority date: 2014-11-12
Filing date: 2014-11-12
Publication date: 2015-03-04
Anticipated expiration: 2024-11-12

Abstract

The utility model discloses a kind of high-speed sampling device based on FPGA and PHY chip, comprise FPGA unit, storage unit, ethernet PHY chip unit and variable bit rate sampling A/D converting unit; Described FPGA unit and variable bit rate A/D unit of sampling is connected by LVDS interface; Described FPGA unit intercoms mutually with storage unit; The MAC Address signal that FPGA unit exports directly exports in ethernet PHY chip unit.The utility model has highly versatile, picking rate is high, communication speed is high feature, is applicable to the various different engineering-environment of power industry, gathers the various signals be coupled to analyte sensors.

Description

A kind of high-speed sampling device based on FPGA and PHY chip

Technical field

The utility model relates to a kind of high-speed data acquiring device, particularly a kind of high-speed sampling device based on FPGA and PHY chip.

Background technology

Along with the technical development of power industry, the monitoring of intelligent grid and Partial discharge signal collection become key device wherein and important technology.It is quite huge that high sample frequency and longer sampling period determine image data amount, such as a power frequency period is 50Hz, if with sampling rate 100MHz, each sampled point is made up of 16bit, so within one second, have 50 power frequency periods, the signal collected is exactly the speed rates of 160MBPS.

Current harvester mostly is USB transmission, but the interface of USB type antistatic interference performance in the comparatively complicated power industry engineer applied of electromagnetic field environment is poor, often there will be situation about not connecting.And general Ethernet implementation many employings FPGA+DSP+PHY chip realizes, hardware size is comparatively large, and cost is higher.

Utility model content

For above-mentioned problems of the prior art, the utility model object is: propose that a kind of picking rate is high, memory capacity is large, highly versatile, cost performance are high, based on the high-speed sampling device of FPGA and PHY chip to solve the problem.

The utility model solves the technical scheme that its technical matters adopts:

Based on a high-speed sampling device for FPGA and PHY chip, comprising:

FPGA unit, storage unit, ethernet PHY chip unit and variable bit rate sampling A/D converting unit; Described FPGA unit and variable bit rate A/D unit of sampling is connected by LVDS interface; Described FPGA unit intercoms mutually with storage unit; The MAC Address signal that FPGA unit exports directly exports in ethernet PHY chip unit.

Described FPGA unit is also provided with expansion I/O mouth.

Described storage unit adopts DDR3 storer.

Described ethernet PHY chip is provided with network card interface.

The beneficial effects of the utility model are:

(1) the utility model adopts FPGA realization to the sampling of data and storage, saves hardware size and power consumption;

(2) adopt Ethernet interface, add antistatic interference performance;

(3) adopt DDR3 to store as on plate, add the reading speed of data stream;

(4) there is highly versatile, picking rate is high, communication speed is high feature, be applicable to the various different engineering-environment of power industry, gather the various signals be coupled to analyte sensors.

Accompanying drawing explanation

Fig. 1 is structural representation of the present utility model.

Embodiment

Below in conjunction with accompanying drawing, the utility model is described further.

As shown in Figure 1, a kind of high-speed sampling device based on FPGA and PHY chip, comprising: FPGA unit, storage unit, ethernet PHY chip unit and variable bit rate sampling A/D converting unit; Described FPGA unit and variable bit rate A/D unit of sampling is connected by LVDS interface; Described FPGA unit intercoms mutually with storage unit; The MAC Address signal that FPGA unit exports directly exports in ethernet PHY chip unit.

Wherein each Elementary Function is as follows:

The collection of the main settling signal of FPGA unit, transmission, storage and read functions.

Variable bit rate sampling A/D converting unit of the present utility model, high-speed a/d is adopted to carry out data acquisition, use FPGA to be directly responsible for the mutual and data transmission of control command between part of data acquisition and software systems as controller, and complete the function of memory controller.

In concrete enforcement, the utility model adopts Altera Cyclone V fpga chip to realize high-speed a/d logic controller, supports A/D chip LVDS output protocol, solves high-speed data IO interface problem.Described storage unit adopts DDR3 storer, guarantees real time data reading capability, solves the storage problem of high-speed data-flow; By the PHY chip that FPGA controls, support gigabit Ethernet transmission, solve the technological difficulties of high speed real-time Communication for Power.

The utility model sampling rate is high, can adapt to unlike signal frequency by the phaselocked loop on FPGA to sample frequency adjustment; On plate, Signal transmissions is fast, and the collection of the data adopting LVDS and DDR3 to make, the speed of storage comparatively like product significantly improve; Described FPGA unit is also provided with expansion I/O mouth, and expansion I/O mouth comprises 48 pin IDC sockets, and 48 pin high speed connectors are connected with 48 user I/O of FPGA, can be connected as general-purpose interfaces such as common I/O, RS232, RS485, LVDS with other devices; And configurability is good, flexible and convenient to use, adapt to various working environment.

Device of the present utility model is made up of analog to digital converter, FPGA, storer and ethernet communication part; Do string through FPGA after the simulating signal of input is converted into digital signal by analog to digital converter to turn also, the form of FIFO is adopted to be stored in DDR3 chip, simulate a MAC Address by FPGA simultaneously, ethernet PHY chip is provided with network card interface, form gigabit Ethernet communications portion with PHY chip, the signal collected the most at last is sent to host computer by netting twine.Compared with the FPGA+DSP+PHY chip that industry is general, decrease hardware size and part category, while reducing cost, substantially increase the mean time between failures of system.

The above-described preferred embodiment that utilizes describes the utility model in detail, and unrestricted scope of the present utility model.Those skilled in the art are by after reading the utility model, and make trickle change and adjustment, main idea place of the present utility model of will can yet be regarded as, does not also depart from spirit and scope of the present utility model.

Claims

1., based on a high-speed sampling device for FPGA and PHY chip, it is characterized in that, comprising:

2. a kind of high-speed sampling device based on FPGA and PHY chip as claimed in claim 1, is characterized in that, described FPGA unit is also provided with expansion I/O mouth.

3. a kind of high-speed sampling device based on FPGA and PHY chip as claimed in claim 1, it is characterized in that, described storage unit adopts DDR3 storer.

4. a kind of high-speed sampling device based on FPGA and PHY chip as claimed in claim 1, it is characterized in that, described ethernet PHY chip is provided with network card interface.