CN204180034U - Pulse edge rectifier circuit and reverse recovery time of diode testing apparatus - Google Patents
Pulse edge rectifier circuit and reverse recovery time of diode testing apparatus Download PDFInfo
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- CN204180034U CN204180034U CN201420189519.4U CN201420189519U CN204180034U CN 204180034 U CN204180034 U CN 204180034U CN 201420189519 U CN201420189519 U CN 201420189519U CN 204180034 U CN204180034 U CN 204180034U
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Abstract
The utility model discloses a kind of pulse edge rectifier circuit and reverse recovery time of diode testing apparatus, include pulse signal generator, pulse signal edge accelerating circuit and t
rrsignal processing circuit.Described pulse signal generator includes for generation of frequency and the adjustable inceptive impulse generator of duty ratio.Pulse signal edge accelerating circuit comprises secondary ECL circuit and high frequency power is guaranteed adequate food and switch, and the rise/fall time exporting porch is less than 0.4nS.Reverse recovery time t
rrsignal processing circuit comprises three grades of ECL circuit and the secondary voltage follower of high-frequency triode formation.The utility model advantage is by ECL circuit acceleration pulse edge, and processes t with it
rrsignal, is developed into t
rrtesting apparatus.By measuring the t of 1N4148 pipe
rr, the LCD reading of device itself and oscilloscope measurement result are coincide, and prove that design effectively, can be developed into measuring instrument.
Description
Technical field
The present invention relates to semiconductor and electronic measuring technology field, specifically refer to a kind of pulse edge rectifier circuit and reverse recovery time of diode testing apparatus.
Background technology
Power diode, snap-off diode, IGBT, thyristor and fast recovery diode constant power semiconductor device are widely used in field of power electronics, in the transfer process of forward and reverse voltage, there is reverse recovery characteristic in these devices, wherein reverse recovery time (t
rr) be the important parameter of these semiconductor device, this parameter to correct selector and design circuit most important.Research shows, for the semiconductor device such as Ultrafast recovery diode, switching diode, and t
rretc. the di of parameter and test pulse
f/ dt (or porch) is closely related, only has suitable di
f/ dt could form considerable reverse recovery current I
rrfor observation.
But in prior art, also there is no suitable pulse signal source to produce to be applicable to the nS level edge pulse signal of trr parameter measurement.Therefore, the present inventor specially have developed the pulse shaper at nS level edge, and forms a kind of nS level testing apparatus reverse recovery time on this basis.
Summary of the invention
The object of the present invention is the shortcoming and defect existed to overcome prior art, and provides a kind of pulse signal that can produce nS level edge, thus be applicable to the devices such as switching diode reverse recovery time high-acruracy survey pulse edge rectifier circuit.
Another object of the present invention is to provide a kind of high-precision reverse recovery time of diode testing apparatus based on pulse edge rectifier circuit.
For realizing first object of the present invention, technical scheme of the present invention includes before and after pulse signal generator and pulse signal along accelerating circuit, described pulse signal generator includes the inceptive impulse processor for generation of inceptive impulse signal, for receiving the main rest-set flip-flop (IC4A) of inceptive impulse signal, and be connected to after main rest-set flip-flop from rest-set flip-flop (IC4B), described main rest-set flip-flop (IC4A) is also connected with the adjustable rheostat (IC5) for the control lag time, be connected along the input of accelerating circuit with the pulse signal output end (out) from rest-set flip-flop (IC4B) before and after described pulse signal, include along accelerating circuit the first order ECL circuit that signal transmits successively before and after this pulse signal, second level ECL circuit and the high frequency power pipe (TR11) as saturated switch, described first order ECL circuit includes high-frequency small power pipe I (TR7) and high-frequency small power pipe II (TR8), this first order ECL circuit be used for by before and after inceptive impulse signal along accelerating not amplified pulse amplitudes.Second level ECL circuit to include in high frequency power tube II (TR10) in power tube I (TR9) and high frequency, this second level ECL circuit be used for by before and after inceptive impulse signal along accelerating further not amplified pulse amplitudes, described high frequency power pipe (TR11) for by before and after pulse along accelerating and being exaggerated amplitude.On the collector electrode of this high frequency power pipe (TR11), also input is connected with the reverse voltage source providing bias voltage, the collector electrode of this high frequency power pipe (TR11) is provided with test pulse output (V-trr).
Further setting is that the front and back of the input pulse of described first order ECL circuit are about 7nS along the rise/fall time, is about 2nS before and after during output along rise/fall, the front and back of the output of described second level ECL circuit along the rise/fall time lower than 0.8nS.
Another object of the present invention is to provide a kind of diode t based on pulse edge rectifier circuit as claimed in claim 1
rrtesting apparatus, its technical scheme comprises with lower unit:
Pulse edge rectifier circuit, this pulse edge rectifier circuit exports nS level edge pulse signal (V
r);
Reverse bias discharge circuit, comprises and connecting and nS level edge pulse signal (V successively
r) charging capacitor (Co), measured diode (Dx) and load resistance (RL), one end ground connection of this load resistance (RL), the other end is connected with signal processing circuit reverse recovery time, this, signal processing circuit was used for measured diode (Dx) reverse recovery time (trr) analog waveform to be transformed into voltage linearly reverse recovery time, and outputted in oscilloscope by A/D conversion;
Between described measured diode (Dx) and charging capacitor (Co), counter offer connects input and is connected with forward current source.
Further setting is signal transacting first order ECL circuit, secondary voltage follower, signal transacting second level ECL circuit and the signal transacting third level ECL circuit that described signal processing circuit reverse recovery time includes signal and transmits successively, described signal transacting first order ECL circuit includes high-frequency triode I (TR12) and high-frequency triode II (TR13), reverse recovery current (I
rr) voltage (V that presented by load resistance (RL)
-trr) signal inputs high-frequency triode I (TR12) base stage through resistance (R20), the preset level (V of this high-frequency triode II (TR13) base stage
-set) be the preset level (V of high-frequency triode II (TR13) base stage
-set) be I
rmaximum I
rm10% (i.e. 0.1I
rm) by voltage during RL, V
-set=0.1I
rmrL.Described secondary voltage follower includes high-frequency triode III (TR14) and high-frequency triode IV (TR15), high-frequency triode VII (TR18) and high-frequency triode VIII (TR19), and this secondary voltage follower is used for not amplifying voltage but keeps waveform and pulse duration to equal (t reverse recovery time
rr) and simultaneously amplified current, signal transacting second level ECL circuit includes high-frequency triode V (TR16) and high-frequency triode VI (TR17), signal transacting third level ECL circuit includes high-frequency triode IX (TR20) and high-frequency triode X (TR21), convert the signal into voltage mode signals (Uo) by high-frequency triode X (TR21) collector resistance (R29), and exported by A/D conversion.
Further setting is the little parasitic capacitance triode of spy that described high-frequency triode I (TR12), high-frequency triode II (TR13), high-frequency triode III (TR14), high-frequency triode IV (TR15), high-frequency triode VII (TR18), high-frequency triode VIII (TR19), high-frequency triode V (TR16) and high-frequency triode VI (TR17) are 1.5GHz, and described high-frequency triode IX (TR20) and high-frequency triode X (TR21) adopts the highly reliable Low dark curient triode of 1GHz.
Advantage of the present invention exports pulse, with ECL circuit acceleration pulse edge and the t using it as signal processing circuit reverse recovery time by CPU
rrtesting apparatus.By t reverse recovery time of Test Switchboard diode
rr, LCD reading and the oscilloscope measurement result of device itself are coincide, and have verified mutually the validity of design, can be developed further into measuring instrument.
Concrete data are see the embodiment of the application.
Below in conjunction with specification drawings and specific embodiments, the present invention is described further.
Accompanying drawing explanation
Fig. 1 the specific embodiment of the present invention diode t
rrtest philosophy figure;
Fig. 2 diode reverse recovery process schematic;
Fig. 3 specific embodiment of the invention forward current source circuit figure;
Fig. 4 specific embodiment of the invention reverse voltage source circuit figure;
The circuit diagram of Fig. 5 specific embodiment of the invention pulse signal generator;
The circuit diagram of Fig. 6 specific embodiment of the invention pulse signal edge accelerating circuit;
Fig. 7 specific embodiment of the invention t
rrthe circuit diagram of signal processing circuit;
Fig. 8 apparatus of the present invention measure the I of switching tube 1N4148 at 20 DEG C
rr-t reverse recovery current figure;
Fig. 9 apparatus of the present invention measure the I of 1N4148 pipe at 100 DEG C
rr-t reverse recovery current figure.
Embodiment
Below by embodiment, the present invention is specifically described; only be used to further illustrate the present invention; can not be interpreted as limiting the scope of the present invention, the technician in this field can make some nonessential improvement and adjustment according to the content of foregoing invention to the present invention.
Embodiment
As shown in figs. 1-7 be the specific embodiment of the invention.Diode t
rrtest philosophy figure as shown in Figure 1.This test circuit comprises and adds the process of forward current to measured diode Dx and it is added to the process of reverse voltage.Last process comprises Rc, Dx, RL, R1, Co element.The latter comprises Co, Dx, RL element.As test pulse V
rduring for high level, V
rcharge to electric capacity Co, IF adds forward current to measured tube Dx simultaneously.I
fthe time flowing through Dx is sufficiently long, at least makes V
rpulse has time enough to complete charging voltage to V by R1 to Co
rpeak value.After charging terminates, V
rloop disconnects, only by forward constant-current source I
fpass through R
c-Dx-RL loop works to Dx, and this process is and adds forward current process to diode Dx.As pulse V
rground connection, forms discharge loop by ground connection-RL-Dx-Co, and because capacitance voltage can not suddenly change, diode reverses current through, and is referred to as the process applying reverse voltage to diode.The reverse recovery current of measured diode is represented by the terminal voltage measuring RL.
Forward current source as shown in Figure 3.Here IC1 is a D/A converter, by arranging DIN, SCLK, CS port of IC1, and outside reference input voltage V
rEFbe all 2048mV, maximum 2 times of reaching reference input voltage of its analog output voltage.Be I to make the electric current of the collector electrode of TR1
f(being assumed to be 50mA here), so the emitter of TR1 is also 50mA, namely the current potential of the positive input of IC12A is 12V-0.05*80V=8V, to break principle according to the short void of the void of amplifier, the current potential of the inverting input of IC12A is also 8V, the collector current so flowing through TR2 is (12-8) V/5000 Ω=0.8mA, and so the emitter current potential of TR2 is 0.8mA*5k Ω=4V, as long as so the normal phase input end of IC12B is 4V.Realize 10mA ~ 50mA to export, only need the OUT terminal voltage Vout of IC1 to be 0.8V ~ 4V.Arrangement can obtain, I
f=Vout*R3/ (R2*R4) is the collector current of triode TR1, and this is just formed holds by the OUT of IC1 the constant-current source controlled.
In Fig. 3, the precision of R2, R3, R4 is F level ± 1%.Consider based on safety operation area, TR1 can select 2SA715, and its parameter is V
cEO=35V, I
cM=1.5A, P
cM=10W, its electric current, voltage, power have surplus.Because this pipe is discontinuous operation, even if during full current work, can not also radiation fin.
Be illustrated in figure 4 reverse voltage source, IC3 is D/A chip, and for the base stage of TR3 and TR4 differential pair tube arranges bias potential, the former is just, the latter is negative.Here utilize TR3 and TR4 to form differential pair tube, R6 and R7 forms linear feedback.The OUT of IC3 is held equal with the base voltage of TR3, suppose that the OUT end of IC3 is 4V, so the emitter vdd voltage of TR6 equals 4.096*3.2=13.1V.Realize 1.5V ~ 13V output area, only need the OUT terminal voltage Vout of IC3 to be that 0.47V ~ 4.06V, IC3 can meet completely.Current drives amplification is made up of TR5 and TR6.Constitute reverse voltage source.
Here TR5 is N channel junction field-effect pipe, V
gSbe zero, I
donly and V
dSthere is faint relation, when constant-current source is used.Here TR6 is NPN pipe, and parameter is BV
cEO=35V, I
cM=1.5A, P
cM=10W, each parameter has surplus, for improving power output.
Pulse edge rectifier circuit, the pulse that this circuit is exported by single-chip microcomputer, narrowed by pulsewidth after monostable trigger-action circuit, again after before and after unsaturated two-stage ECL circuit pulse signals, edge is accelerated, test signal needed for exporting through third level UHF Power pipe again, its rising edge ascending time (ON time) can reach 0.4nS, and electric current can be greater than 250mA.Because triode is current driving apparatus, during conducting, the impact of junction capacitance on signal is less.
Wherein, pulse signal generator as shown in Figure 5, is made up of two rest-set flip-flops (IC4A, IC4B) and CPU (89C2051), can frequency modulation rate, time of delay, duty ratio.Pulse signal (such as 50kHz square wave) is exported by the P12 pin of CPU (89C2051).IC4A carrys out the control lag time, t by regulating the IC5 adjustable resistor of 10k Ω
y(nS)=0.33*10*30+50=149nS, and burst length t
y(nS)=0.33*6.2*220+50=500.12nS, K=0.33 is the coefficient that this monostable trigger-action circuit is given here.
The monostable trigger-action circuit of test pulse signal is for coordinating high-impedance sampling oscilloscope to use by normal display waveform completely.Such sampling oscilloscope needs to trigger in advance, and IC4A provides the suitable triggered time in advance under CPU control IC5, and IC4B provides and triggers the signal that interior pulse generator is closed in test, width about 0.5 μ s.
In addition, along accelerating circuit before and after pulse signal as shown in Figure 6, this main circuit will have employed emitter coupled logic (ECL) circuit, and it not only can amp pulse, also can by before and after pulse along accelerating.Undersaturated ECL circuit is formed herein with microwave tube, microwave tube be wherein operated in cut-off or amplify and not in saturation condition, effectively prevent the storage effect of electric charge, collector load resistor is very little, thus the discharge and recharge time constant of its output parasitic capacitance is very little, be conducive to improving switching speed, thus the speed-raising of paired pulses edge.Triode TR7, TR8 and TR9 in Fig. 6, TR10 constitute two-stage ECL circuit respectively.In nonsaturated circuit, switching speed is primarily of f
t, I
cm, R
l, C
ob, C
idecide.If the resistance value of base potential, collector electrode and emitter is suitable, the signal being greater than some strength makes pipe ON operation, bottom pulse signal lower than that part of certain amplitude because of pipe cut-off then export time clipped; Because pipe is saturated when pulse amplitude is too high, when exporting, pruned in top; Export pulse and only retain that part of pulse waist.Such effect is that the rise/fall speed on edge before and after pulse is accelerated.
First order ECL circuit is made up of high-frequency small power pipe TR7 and TR8: input pulse rising edge ascending time is about 7nS, and during output, forward position is less than 2nS.Here f can be chosen
tthe high-frequency tube 9018, I of=1GHz
cf during=20mA
talso have 900MHz, minimum VCE=2.5V.TR7, TR8 form ECL circuit, and the electric current flowing through R12 is distributed by TR7, TR8.If TR7 conducting, the electric current flowing through R12 is managed from TR7; Otherwise TR8 conducting, the electric current flowing through R12 is managed from TR8.By analyzing, pulse signal is held from the Q end of IC4B and out here, and TR7 is to provide bias potential, namely for arranging quiescent point.At this, the emitter current potential of the base potential of TR7 to be-4.5V, TR8 base potential be-4V, TR8 is-4.7V, and the electric current flowing through emitter resistance R12 is (12-4.7)/360=20.2mA, can play the fireballing advantage of TR7, TR8 to greatest extent.R12 plays Current Negative Three-Point Capacitance effect, can expand the linear amplification region of circuit at the corresponding levels.When the amplitude of input signal is larger, a cut-off in TR7, TR8 and another is saturated, the top of pulse during output and bottom are reamed, and leave waist, thus only by before and after pulse along accelerating not amplified pulse amplitudes.
Second level ECL circuit is made up of power tube TR9 and TR10 in high frequency: export rising edge ascending time and be less than 0.8nS.Here f is chosen
tfor the 2SC3355 of 6.5GHz, I
cf during=55mA
treach 6GHz, minimum V
cE=2.5V is unsaturated amplifier.The electric current flowing through R16 is distributed by TR9, TR10.Here TR10 provides bias potential, namely for arranging quiescent point.The base potential of TR9 is that the base potential of about-1.2V, TR10 is-2V, TR9, the emitter current potential of TR10 is-2V, and the electric current flowing through R16 is (12-2)/180=55mA, can play the fireballing advantage of TR9, TR10 to greatest extent.ECL circuit at the corresponding levels also by before and after pulse along accelerating not enlargement range.
The load resistance value of secondary ECL circuit is also very important, because load resistance is large, the product of it and load capacitance is just large, and between transistor collector-base stage, the effect of feedback capacity is also large, and the front and back exporting pulse are just restricted along speed.
Third level high frequency (7GHz) power tube TR11 (optional BFG591) is saturated switch, and the rising, the fall time that export edge before and after pulse are less than 0.4nS.It is exported by TR9 collector electrode and drives, V
-trrthe test pulse of end for being sent to diode.Time static, TR9 electric current flows through Ro, makes TR11 base voltage for-0.5V and ending, and when positive pulse is added to TR7 base stage, TR9 turns off.The electric current 55mA of Ro flows rapidly into TR11 base stage makes its conducting.Edge before and after pulse is not only accelerated but also is exaggerated amplitude by the third level, and its amplitude is determined by the VR set-point of Fig. 4.
Three grades of circuit not only achieve the Q end output pulse amplitude amplification of IC4B, but also accelerate the speed of porch.
T reverse recovery time as shown in Figure 7
rrsignal processing circuit is according to test t
rrnational standard (GB6571-86. and GB 4023-1997.) require to design, have employed high-frequency triode and form three grades of ECL circuit.With aforementioned ECL circuit unlike, pay special attention to here first order pipe base potential arrange.The first order is made up of TR12, TR13.Reverse recovery current I
rrthe voltage V presented by load RL
-trrsignal inputs TR12 base stage through R20; The preset level V of TR13 base stage
-seti can be set to
rrmaximum I
rrm10% (i.e. 0.1I
rrm) by voltage during RL, i.e. V
-set=0.1I
rrmrL.In diode reverse recovery process, | V
-trr| higher than | V
-set| time, TR12 conducting, TR13 ends, V
-trrsignal enters next stage circuit through TR12.TR14 and TR15, TR18 and TR19 form secondary voltage follower, this follower energy amplified current and do not amplify voltage but keep waveform and pulse duration=t
rr.And TR16, TR17 form second level ECL circuit, similar with the effect of TR12, TR13.TR20, TR21 are third level ECL circuit, convert voltage mode signals Uo to by TR21 collector resistance R29, as the input of A/D module.Uo=Io*t
rr* R29/T, wherein Io is the collector current of TR21, and T is the cycle of VR pulse, and when T is constant, R29 both end voltage only and t
rrrelevant with W1, R30.Last R29 both end voltage is sent to A/D modular converter driving display and changes numerical monitor into.Because the cut-off frequency f of each pipe
tlimited, thus t
rrhave non-linear at below 3nS voltage mode signals Uo, can be solved by software compensation, finally can make t
rrmeasured value reach about 1nS.Because TR20, TR21 form ECL circuit, TR21 conducting then TR2 cut-off, so the collector current that Io is TR21 is also the collector current of TR22 simultaneously.TR22 is used for wave shape correcting, and here because TR22 base bias is definite value-5V, so the pressure reduction of the emitter voltage of TR22 and the-12V of R30, W1 end is definite value, and Io is also steady state value (being controlled by W1, R30).
Because this circuit object is that trr analog waveform is transformed into voltage as far as possible linearly, so that A/D conversion.As for t
rrsection forward position, original signal is very fast (0.4nS) just, and this circuit does not play acceleration.The comparison speed of this circuit overall can reach 1nS, resolution 0.1nS, and overall signal delay can reach 0.45nS, inputs the ability of anti-common mode+1.5 and-3.0V in addition.
The front secondary of this circuit and follower use the little parasitic capacitance triode of spy of 1.5GHz, and afterbody adopts the highly reliable Low dark curient triode of 1GHz, and object reduces temperature drift, improves reliability.
RT12032-1 type liquid crystal display can be selected to carry out the t of display measurement condition and gained
rretc. parameter, A/D converter can choose 12 Bits Serial analog to digital converter TLC2543C, and the two can select ICL7109 module to drive; The management of control, input through keyboard, computing and each relay can adopt the 89C52 integrated circuit taking on host CPU role to realize.These circuit are commonly used, and repeat no more herein.
experimental example
Test the t of 1N4148 type switching diode
rr, the measuring condition of setting is optimum configurations: I
f=10mA, I
r=40mA.
As shown in Figure 8, at 20 DEG C, during test, measure t with oscilloscope active probe
rrbe 7.8 nS.
As shown in Figure 9, at 100 DEG C, during test, measure t with oscilloscope active probe
rrbe 19.4 nS.
Usually, 1N4148 type switching diode is at I
f=10mA to I
r=1mA, V
r=6V, R
lnominal value t when=100 Ω, 25 oC
rr=4 nS, the result measured when developing 20 DEG C, device with the present invention is close, and difference wherein mainly comes from measuring condition difference.The value of active probe measurement is different from by the value that passive probe is measured.So, answer careful selection oscilloscope and supporting probe during measurement.
Claims (3)
1. a pulse edge rectifier circuit, it is characterized in that: include before and after pulse signal generator and pulse signal along accelerating circuit, described pulse signal generator includes for generation of the inceptive impulse generating processor (CPU) of frequency and the adjustable inceptive impulse signal of duty ratio, for receiving the main rest-set flip-flop (IC4A) of inceptive impulse signal, and be connected on main rest-set flip-flop from rest-set flip-flop (IC4B), described main rest-set flip-flop (IC4A) is also connected with the adjustable rheostat (IC5) for the control lag time
,be connected along the input of accelerating circuit with the pulse signal output end (out) from rest-set flip-flop (IC4B) before and after described pulse signal, this pulse edge rectifier circuit includes first order ECL (emitter coupled logic) circuit that signal connects successively, second level ECL circuit and the high frequency power pipe (TR11) as saturated switch, described first order ECL circuit includes high-frequency small power pipe I (TR7) and high-frequency small power pipe II (TR8), this first order ECL circuit be used for by before and after inceptive impulse signal along accelerating not amplified pulse amplitudes, second level ECL circuit to include in high frequency power tube II (TR10) in power tube I (TR9) and high frequency, this second level ECL circuit be used for by before and after inceptive impulse signal along accelerating further not amplified pulse amplitudes, described high frequency power pipe (TR11) is for accelerating edge before and after pulse and be exaggerated amplitude, on the collector electrode of this high frequency power pipe (TR11), also input is connected with the reverse voltage source providing bias voltage, the collector electrode of this high frequency power pipe (TR11) is provided with test pulse output (V-trr).
2. a kind of pulse edge rectifier circuit according to claim 1, it is characterized in that: the front and back of the input pulse of described first order ECL circuit are about 7nS along the rise/fall time, be about 2nS during output, the front and back of the output pulse of described second level ECL circuit along the rise/fall time lower than 0.8nS.
3., based on a reverse recovery time of diode testing apparatus for pulse edge rectifier circuit as claimed in claim 1, its feature also comprises with lower unit:
(1) pulse edge rectifier circuit, this pulse edge rectifier circuit exports nS level edge pulse signal (VR);
(2) reverse bias discharge circuit, comprise and connecting successively and the charging capacitor (Co) at nS level edge pulse signal (VR), measured diode (Dx) and load resistance (RL), one end ground connection of this load resistance (RL), the other end is connected with signal processing circuit reverse recovery time, this, signal processing circuit was used for measured diode (Dx) reverse recovery time (trr) analog waveform to be transformed into voltage linearly reverse recovery time, and outputted in oscilloscope by A/D conversion;
(3) forward current source is also connected with between the measured diode (Dx) described in and charging capacitor (Co).
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| CN201420189519.4U CN204180034U (en) | 2014-04-17 | 2014-04-17 | Pulse edge rectifier circuit and reverse recovery time of diode testing apparatus |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420189519.4U CN204180034U (en) | 2014-04-17 | 2014-04-17 | Pulse edge rectifier circuit and reverse recovery time of diode testing apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105823973A (en) * | 2016-03-16 | 2016-08-03 | 温州大学 | Multi-standard tester for reverse recovery time of diodes |
| CN108809277A (en) * | 2018-06-25 | 2018-11-13 | 中国人民解放军火箭军工程大学 | A kind of pulse signal generation device |
| CN109167590A (en) * | 2018-08-09 | 2019-01-08 | 浙江优勝科技有限公司 | A kind of pulse-generating circuit |
| CN110763971A (en) * | 2019-10-12 | 2020-02-07 | 温州大学 | Terahertz transit time device switch transient current waveform and parameter measuring device |
| CN116298753A (en) * | 2023-02-27 | 2023-06-23 | 佛山市联动科技股份有限公司 | Reverse recovery time testing device and method for semiconductor device |
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2014
- 2014-04-17 CN CN201420189519.4U patent/CN204180034U/en not_active Expired - Lifetime
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105823973A (en) * | 2016-03-16 | 2016-08-03 | 温州大学 | Multi-standard tester for reverse recovery time of diodes |
| CN105823973B (en) * | 2016-03-16 | 2017-02-22 | 温州大学 | Multi-standard tester for reverse recovery time of diodes |
| CN108809277A (en) * | 2018-06-25 | 2018-11-13 | 中国人民解放军火箭军工程大学 | A kind of pulse signal generation device |
| CN108809277B (en) * | 2018-06-25 | 2021-09-24 | 中国人民解放军火箭军工程大学 | Pulse signal generating device |
| CN109167590A (en) * | 2018-08-09 | 2019-01-08 | 浙江优勝科技有限公司 | A kind of pulse-generating circuit |
| CN109167590B (en) * | 2018-08-09 | 2022-06-24 | 浙江优勝科技有限公司 | Pulse generating circuit |
| CN110763971A (en) * | 2019-10-12 | 2020-02-07 | 温州大学 | Terahertz transit time device switch transient current waveform and parameter measuring device |
| CN110763971B (en) * | 2019-10-12 | 2020-09-29 | 温州大学 | Terahertz transit time device switch transient current waveform and parameter measuring device |
| CN116298753A (en) * | 2023-02-27 | 2023-06-23 | 佛山市联动科技股份有限公司 | Reverse recovery time testing device and method for semiconductor device |
| CN116298753B (en) * | 2023-02-27 | 2024-01-30 | 佛山市联动科技股份有限公司 | Reverse recovery time testing device and method for semiconductor device |
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