CN204089874U - A kind of switch supporting packet storage - Google Patents
A kind of switch supporting packet storage Download PDFInfo
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- CN204089874U CN204089874U CN201420527030.3U CN201420527030U CN204089874U CN 204089874 U CN204089874 U CN 204089874U CN 201420527030 U CN201420527030 U CN 201420527030U CN 204089874 U CN204089874 U CN 204089874U
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Abstract
A kind of switch supporting packet storage.It comprises CPU administration module, FPGA function module, Switching Module, packet storage module and PHY module; Wherein: CPU administration module is connected with Switching Module with FPGA function module respectively, FPGA function module is connected with PHY module with Switching Module, packet storage module respectively.The utility model effect: switch realizes the storage of message will for providing favourable foundation when Digitized transformation stands in emergency review, step by step search the relevant abnormalities situation that message transmissions occur by contributing to when problem analysis from source stored messages, under making net adopt net hop pattern, this process of message transmissions has had definite analysis foundation.Owing to adopting high performance FPGA to carry out administrative analysis to message, the obvious increase bringing exchange process time delay due to packet storage can not be caused, ensure that the reliability of switch store-and-forward delay.
Description
Technical field
The utility model belongs to power system network switch device technical field, particularly relates to a kind of switch supporting packet storage.
Background technology
Along with reaching its maturity of Automation Technology of Digitized Transformer, net is adopted net jumping mode and is widely used in existing digital transformer substation.As the key unit of digital transformer substation network, the critical role of switch in digital transformer substation highlights day by day.Network messages a large amount of in digital transformer substation instead of electric current and voltage in the secondary cable transfer station in original normal station and coherent signal, and this mode makes to occur that certain fault is difficult to trace to the source for the reason of accident in station.Although now in digital transformer substation extensive use network message analytical equipment the association message in digital transformer substation is analyzed and emergency review, network message analytical equipment obtains corresponding message from certain Single port of switch usually.Be limited to this Receive message mode, the message that network analyzing apparatus can only provide these switches carries out analyzing stored, but going out active once there is the message that sends of station equipment through switch, network analyzing apparatus cannot capture association message to carry out analysis and recollects.Also analysis cannot be caught by this abnormal network analytical equipment of delay transport caused because some is abnormal in switch transmitting procedure.The uncertainty of the otherness and time delay that pass in and out message in switch message repeating process will become the not expugnable difficult point of network message analytical equipment, and especially the propagation delay time analysis of switch realizes comparatively difficulty in network message analytical equipment aspect.
Summary of the invention
In order to solve the problem, the purpose of this utility model is to provide a kind of switch supporting packet storage.
In order to achieve the above object, the switch of support packet storage that the utility model provides comprises: CPU administration module, FPGA function module, Switching Module, packet storage module and PHY module; Wherein: CPU administration module is connected with Switching Module with FPGA function module respectively, FPGA function module is connected with PHY module with Switching Module, packet storage module respectively;
CPU administration module is take microprocessor as the controller module of core, for carrying out relevant configuration to Switching Module and FPGA function module, and carries out the process of switch associated the Internet protocol;
FPGA function module is the logical circuit that a programmable gate array chip is formed, message for receiving PHY module carries out relevant treatment, when packet sending and receiving, correlation analysis is carried out to message, and the copy orientation realizing message is stored into the transmission to Switching Module of packet storage module and message;
Switching Module is the core parts exchange chip of switch, is connected with between CPU administration module by serial peripheral SPI interface;
Packet storage module is external memory device, for storing relevant message information;
PHY module is physical layer interface chip, for providing the access passage of ethernet port for FPGA function module.
Described FPGA function module mainly comprises crystal oscillator, reset circuit, power circuit, download program circuit, memory expansion part; Be connected by MII interface between FPGA function module with PHY module, be also connected by the MAC of MII interface with each port of Switching Module inside with the connection between Switching Module, FPGA function module needs external packet storage module to realize memory function.
Described civilian memory module adopts the solid state hard disc of 1T to ensure enough memory spaces, and the interface between FPGA function module and packet storage module adopts SATA interface.
Described PHY module is connected by MII interface with FPGA function module, for outwards providing SFP/RJ45 interface, is convenient to the connection of optical fiber and twisted-pair feeder.
The effect of the switch of the support packet storage that the utility model provides:
Switch realizes the storage of message will for providing favourable foundation when Digitized transformation stands in emergency review, step by step search the relevant abnormalities situation that message transmissions occur by contributing to when problem analysis from source stored messages, under making net adopt net hop pattern, this process of message transmissions has had definite analysis foundation.Owing to adopting high performance FPGA to carry out administrative analysis to message, the obvious increase bringing exchange process time delay due to packet storage can not be caused, ensure that the reliability of switch store-and-forward delay.Simultaneously by switch is stored and the comparative analysis that E-Packets we can know the admission control situation of switch and the store-and-forward delay of switch, for the related performance indicators analyzing switch, there is certain reference significance.
Accompanying drawing explanation
The overall structure block diagram of the switch of the support packet storage that Fig. 1 provides for the utility model.
Fig. 2 is FPGA function module peripheral structure block diagram in the utility model.
Embodiment
Be described in detail below in conjunction with the switch of the drawings and specific embodiments to the support packet storage that the utility model provides.
As shown in Figure 1, the switch of support packet storage that the utility model provides comprises: CPU administration module 1, FPGA function module 2, Switching Module 3, packet storage module 4 and PHY module 5; Wherein: CPU administration module 1 is connected with Switching Module 3 with FPGA function module 2 respectively, FPGA function module 2 is connected with PHY module 5 with Switching Module 3, packet storage module 4 respectively;
CPU administration module 1 is take microprocessor as the controller module of core, for carrying out relevant configuration to Switching Module 3 and FPGA function module 2, and carries out the process of switch associated the Internet protocol;
FPGA function module 2 is the logical circuit that a programmable gate array chip is formed, message for receiving PHY module 5 carries out relevant treatment, when packet sending and receiving, correlation analysis is carried out to message, and the copy orientation realizing message is stored into the transmission to Switching Module 3 of packet storage module 4 and message;
The peripheral structure block diagram of FPGA function module 2 as shown in Figure 2, mainly comprises the parts such as crystal oscillator, reset circuit, power circuit, download program circuit, memory expansion.Be connected by MII interface between FPGA function module 2 with PHY module 5, also be connected by the MAC of MII interface with each port of Switching Module 3 inside with the connection between Switching Module 3, FPGA function module 2 needs external packet storage module 4 to realize memory function;
Switching Module 3 is the core parts exchange chip of switch, is connected with CPU administration module 1 by serial peripheral SPI interface, for carrying out storage forwarding to the message received from FPGA function module 2;
Packet storage module 4 is external memory device, for storing relevant message information;
Described packet storage module 4 adopts the solid state hard disc of 1T to ensure enough memory spaces, and the interface between FPGA function module 2 and packet storage module 4 adopts SATA interface.
PHY module 5 is physical layer interface chip, for providing the access passage of ethernet port for FPGA function module 2;
PHY module 5 is connected by MII interface with FPGA function module 2, for outwards providing SFP/RJ45 interface, is convenient to the connection of optical fiber and twisted-pair feeder; The association message received is passed to FPGA function module 2 by MII interface by the external interface of PHY module 5.
Undertaken being connected and exchanges data by MII data-interface between FPGA function module 2 with PHY module 5; When message is delivered to FPGA function module 2 from PHY module 5, FPGA function module 2 is by monitoring and analyzing the signal on MII interface, the timestamp in this moment is obtained the time of reception at message, the acquisition point of timestamp is positioned between data link layer and physical layer, just timestamp is stamped when receiving first bit of sampled data bag, like this can the time delay of cancellation protocol stack and shake, the timestamp of acquisition is the most accurate.While acquisition message time of reception stamp, the message received carries out " copy " by FPGA function module 2, a message wherein carries out packet parsing by FPGA function module 2, judge type and the MMS/GOOSE/SV of message, according to the difference of type of message by among these packet storages to packet storage module 4 in advance within ready-portioned different packet storage space, the time of reception of message that also has simultaneously stored with message stabs information, another part of message that FPGA function module 2 copies passes to the MAC in the Switching Module 3 be attached thereto by the MII interface between FPGA function module 2 and Switching Module 3, then Switching Module 3 carries out orderly storage forwarding according to the storage forwarding rule of itself.
When message is gone out from a certain port repeat according to forwarding rule through storing, FPGA function module 2 monitors the signal on the MII interface of this port be attached thereto, the transmitting time stamp of this message is produced from the moment that Switching Module 3 sends at message, processing mode when receiving with message is identical, FPGA function module 2 is used for a for message copy the storage area being together stored into corresponding message with message transmitting time stamp, another part of message is then passed to the PHY module 5 being attached thereto and connecing by FPGA function module 2, thus realizes the transmission of message.
The storage of switch message achieves and stores by class, the message subregion of port accepts and transmission stores, the classification that difference again according to type of message in different storage areas realizes dissimilar message stores, and this storage mode is greatly for the analysis of later stage stored messages provides convenient.Such as we can by contrast same frame message time of reception stamp and transmitting time stab learn the store-and-forward delay of this message in switch inside.
The feature of the switch of the support packet storage that the utility model provides:
Because the analysis message of existing network message analytical equipment is all derived from exchanger side, all messages are switch and E-Packet, and the source message that the merge cells of really or intelligent terminal etc. send, and cannot trace to the source to recollect accident.Consider the forwarding mechanism of switch storage forwarding, net is adopted net and is jumped the source message that sends of all devices and all can forward through switch again, this mode switch is become secondary device that first receives device source message, we can utilize switch to carry out real-time storage to the message received, when this message forwards from target port, we store message at this, thus in message reception and two moment of transmission, real-time storage is carried out to message, under being convenient to abnormal conditions, analysis emergency review is carried out to stored messages.
The utility model is illustrated by above-described embodiment; the utility model is not limited to above-described embodiment; multiple variants and modifications can also be made according to instruction of the present utility model; on the basis of packet storage, such as realize the off-line analysis work etc. of message, within these variants and modifications all drop on the utility model scope required for protection.
Claims (4)
1. support a switch for packet storage, it is characterized in that: the switch of described support packet storage comprises: CPU administration module (1), FPGA function module (2), Switching Module (3), packet storage module (4) and PHY module (5); Wherein: CPU administration module (1) is connected with Switching Module (3) with FPGA function module (2) respectively, FPGA function module (2) is connected with PHY module (5) with Switching Module (3), packet storage module (4) respectively;
CPU administration module (1) is take microprocessor as the controller module of core, for carrying out relevant configuration to Switching Module (3) and FPGA function module (2), and carries out the process of switch associated the Internet protocol;
FPGA function module (2) is the logical circuit that a programmable gate array chip is formed, message for receiving PHY module (5) carries out relevant treatment, when packet sending and receiving, correlation analysis is carried out to message, and the copy orientation realizing message is stored into the transmission to Switching Module (3) of packet storage module (4) and message;
The core parts exchange chip that Switching Module (3) is switch, by being connected between serial peripheral SPI interface with CPU administration module (1);
Packet storage module (4) is external memory device, for storing relevant message information;
PHY module (5) is physical layer interface chip, for providing the access passage of ethernet port for FPGA function module (2).
2. the switch of support packet storage according to claim 1, is characterized in that: described FPGA function module (2) mainly comprises crystal oscillator, reset circuit, power circuit, download program circuit, memory expansion part; Be connected by MII interface between FPGA function module (2) with PHY module (5), also be connected by the MAC of MII interface with each port of Switching Module (3) inside with the connection between Switching Module (3), FPGA function module (2) needs external packet storage module (4) to realize memory function.
3. the switch of support packet storage according to claim 1, it is characterized in that: described civilian memory module (4) adopts the solid state hard disc of 1T to ensure enough memory spaces, and the interface between FPGA function module (2) and packet storage module (4) adopts SATA interface.
4. the switch of support packet storage according to claim 1, it is characterized in that: described PHY module (5) is connected by MII interface with FPGA function module (2), for outwards providing SFP/RJ45 interface, be convenient to the connection of optical fiber and twisted-pair feeder.
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| CN201420527030.3U CN204089874U (en) | 2014-09-12 | 2014-09-12 | A kind of switch supporting packet storage |
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| CN201420527030.3U CN204089874U (en) | 2014-09-12 | 2014-09-12 | A kind of switch supporting packet storage |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104702354A (en) * | 2015-03-16 | 2015-06-10 | 毕节供电局 | FPGA-based (field programmable gate array-based) PTN (packet transport network) equipment time delay monitoring device and method |
| WO2016180044A1 (en) * | 2015-05-11 | 2016-11-17 | 中兴通讯股份有限公司 | Message sending method and device |
| CN107707492A (en) * | 2017-11-22 | 2018-02-16 | 杭州迪普科技股份有限公司 | A kind of method and device reported with downward message |
| CN110365556A (en) * | 2019-08-22 | 2019-10-22 | 深圳市三旺通信股份有限公司 | The implementation method of ethernet signal linear speed acquisition monitoring and analysis |
| CN110430099A (en) * | 2019-08-22 | 2019-11-08 | 深圳市三旺通信股份有限公司 | A kind of method of the acquisition of ethernet signal linear speed monitoring and analysis |
| CN110445693A (en) * | 2019-08-22 | 2019-11-12 | 深圳市三旺通信股份有限公司 | The method for realizing ethernet signal linear speed acquisition monitoring and analysis |
| CN110460499A (en) * | 2019-08-22 | 2019-11-15 | 深圳市三旺通信股份有限公司 | The method of ethernet signal linear speed acquisition monitoring and analysis |
| CN110474823A (en) * | 2019-08-22 | 2019-11-19 | 深圳市三旺通信股份有限公司 | A kind of device for realizing ethernet signal linear speed acquisition monitoring and analysis |
| CN110505121A (en) * | 2019-08-22 | 2019-11-26 | 深圳市三旺通信股份有限公司 | A method of realizing ethernet signal linear speed acquisition monitoring and analysis |
-
2014
- 2014-09-12 CN CN201420527030.3U patent/CN204089874U/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104702354A (en) * | 2015-03-16 | 2015-06-10 | 毕节供电局 | FPGA-based (field programmable gate array-based) PTN (packet transport network) equipment time delay monitoring device and method |
| WO2016180044A1 (en) * | 2015-05-11 | 2016-11-17 | 中兴通讯股份有限公司 | Message sending method and device |
| CN106302157A (en) * | 2015-05-11 | 2017-01-04 | 中兴通讯股份有限公司 | File transmitting method and device |
| CN107707492A (en) * | 2017-11-22 | 2018-02-16 | 杭州迪普科技股份有限公司 | A kind of method and device reported with downward message |
| CN107707492B (en) * | 2017-11-22 | 2020-05-12 | 杭州迪普科技股份有限公司 | Method and device for reporting and issuing message |
| CN110365556A (en) * | 2019-08-22 | 2019-10-22 | 深圳市三旺通信股份有限公司 | The implementation method of ethernet signal linear speed acquisition monitoring and analysis |
| CN110430099A (en) * | 2019-08-22 | 2019-11-08 | 深圳市三旺通信股份有限公司 | A kind of method of the acquisition of ethernet signal linear speed monitoring and analysis |
| CN110445693A (en) * | 2019-08-22 | 2019-11-12 | 深圳市三旺通信股份有限公司 | The method for realizing ethernet signal linear speed acquisition monitoring and analysis |
| CN110460499A (en) * | 2019-08-22 | 2019-11-15 | 深圳市三旺通信股份有限公司 | The method of ethernet signal linear speed acquisition monitoring and analysis |
| CN110474823A (en) * | 2019-08-22 | 2019-11-19 | 深圳市三旺通信股份有限公司 | A kind of device for realizing ethernet signal linear speed acquisition monitoring and analysis |
| CN110505121A (en) * | 2019-08-22 | 2019-11-26 | 深圳市三旺通信股份有限公司 | A method of realizing ethernet signal linear speed acquisition monitoring and analysis |
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Address after: 300010 Tianjin city Hebei District Wujing Road No. 39 Patentee after: State Grid Corporation of China Patentee after: State Grid Tianjin Electric Power Company Address before: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Patentee before: State Grid Corporation of China Patentee before: State Grid Tianjin Electric Power Company |
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Granted publication date: 20150107 Termination date: 20180912 |