CN110505121A - A method of realizing ethernet signal linear speed acquisition monitoring and analysis - Google Patents
A method of realizing ethernet signal linear speed acquisition monitoring and analysis Download PDFInfo
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- CN110505121A CN110505121A CN201910782903.2A CN201910782903A CN110505121A CN 110505121 A CN110505121 A CN 110505121A CN 201910782903 A CN201910782903 A CN 201910782903A CN 110505121 A CN110505121 A CN 110505121A
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- gate array
- programmable gate
- field programmable
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- ethernet
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/14—Network analysis or design
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0876—Network utilisation, e.g. volume of load or congestion level
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Environmental & Geological Engineering (AREA)
- Small-Scale Networks (AREA)
Abstract
The invention belongs to Ethernet communication technology fields, disclose a kind of method for realizing ethernet signal linear speed acquisition monitoring and analysis, it include: that field programmable gate array is directly mounted in the MII bus between MAC and PHY, field programmable gate array has ethernet port, Consol mouthfuls and storage unit；Field programmable gate array is read out, monitors and analyzes to the data packet transmitted in MII bus, stores the data packet, monitoring and analysis result by the storage unit；Field programmable gate array externally provides the data packet, monitoring and analysis result by its ethernet port and Consol mouthfuls.The present invention realizes the ability effectively improved to ethernet device diagnosis, reduces maintenance cost.
Description
Technical field
The invention belongs to Ethernet communication technology field more particularly to a kind of realization ethernet signal linear speed acquisition monitoring and
The method of analysis.
Background technique
Ethernet device is widely used in industry spot, and equipment job site environment is often more complicated and harsh, once
Equipment breaks down, and field technician is difficult effectively to be analyzed and accurate judgement, will cause high maintenance cost.
Summary of the invention
The embodiment of the present invention is designed to provide a kind of method for realizing ethernet signal linear speed acquisition monitoring and analysis,
The ability to ethernet device diagnosis can be effectively improved, maintenance cost is reduced.
The embodiments of the present invention are implemented as follows:
A method of realizing ethernet signal linear speed acquisition monitoring and analysis, comprising:
Field programmable gate array, field programmable gate array tool are directly mounted in MII bus between MAC and PHY
There are ethernet mac function MII interface, ethernet PHY functional interface and serial port function interface, field programmable gate array to have
Ethernet port, Consol mouthfuls and storage unit；
Field programmable gate array is read out, monitors and analyzes to the data packet transmitted in MII bus, realizes Ethernet
Linear speed acquisition, monitoring and the analysis of signal store the data packet, monitoring and analysis result by the storage unit；
Field programmable gate array externally provides the data packet, monitoring by its ethernet port and Consol mouthfuls and divides
Analyse result.
Wherein, the MII bus can be RMII bus, RGMII bus, SGMII bus or QSGMII bus.
Wherein, the storage unit is memory ram item, Flash, standard machinery hard disk or solid state hard disk.
The embodiment of the present invention is inside embedded network equipment, by the interface between MAC and PHY, i.e., MAC in PHY it
Between interface on mount FPGA, realize ethernet signal linear speed acquisition, monitoring and analysis.Simultaneously externally provide network interface and
Serial ports is checked and is judged to equipment fault for field technician.The present invention can effectively improve the ability to device diagnostic,
Reduce maintenance cost.
Detailed description of the invention
Fig. 1 is the functional block diagram for the method that the present invention realizes ethernet signal linear speed acquisition monitoring and analysis.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Specific implementation of the invention is described in detail below in conjunction with specific embodiment:
As shown in Figure 1, a kind of method for realizing ethernet signal linear speed acquisition monitoring and analysis, comprising:
Field programmable gate array, field programmable gate array tool are directly mounted in MII bus between MAC and PHY
There are ethernet mac function MII interface, ethernet PHY functional interface and serial port function interface, field programmable gate array to have
Ethernet port, Consol mouthfuls and storage unit；
Field programmable gate array is read out, monitors and analyzes to the data packet transmitted in MII bus, realizes Ethernet
Linear speed acquisition, monitoring and the analysis of signal store the data packet, monitoring and analysis result by the storage unit；
Field programmable gate array externally provides the data packet, monitoring by its ethernet port and Consol mouthfuls and divides
Analyse result.
In figure, PHY is connect by P0 to Pn with Ethernet Ports ethernet port.
It about field programmable gate array, is analyzed according to function logic, is to realize three kinds of functional interfaces, ethernet mac
Function MII interface, ethernet PHY functional interface and serial port function interface.These implementation methods can be to field programmable gate
Array program is realized.Then, ethernet mac function MII interface is connected between MAC the and PHY bus of collected equipment；It will
Phy interface directly connects a network interface RJ45；Serial interface is connected to serial ports input and output part.It is thus as shown in Figure 1, collected
MAC is sent to the data of PHY, can also reach on the ethernet mac function MII interface bus of field programmable gate array, scene can
When programming gate array monitors to have data in MII bus, so that it may which the MAC for getting collected equipment is sent to the data of PHY.Together
Sample, when collected equipment MAC is received from the data of PHY layer, also to reach scene from the data of PHY layer to come can be compiled
On the ethernet mac function MII interface bus of journey gate array, when field programmable gate array monitors to have data in MII bus,
The MAC that collected equipment can be got receives the data of PHY.
The implementation that the present invention uses is as shown in Figure 1:
(1) MAC layer and PHY layer pass through MII interface communication, mount FPGA in MII bus, FPGA reads data packet
Take, analyze, under the premise of not influencing between ethernet port data storage forwarding linear speed acquisition, monitoring, analysis and store with
Too network data packet.
(2) FPGA mounts storage unit, realizes processing and storage to network packet.
(3) FPGA unit externally provides ethernet port and Consol mouthfuls, and FPGA processing unit carries out ethernet signal
Acquisition, monitoring and analysis facilitate field technician to pass through PC to failure and check and judge.
(4) it is forwarded between ethernet port by the storage that MAC carries out Ethernet data bag, these Ethernet data bags
It is acquired and is read by FPGA unit to whole linear speeds, storage unit stores these data packets.
The present invention is to mount FPGA on interface between MAC layer and PHY layer, and FPGA is read out Ethernet data bag
And processing, realize the linear speed acquisition of ethernet signal, monitoring and analysis；The acquisition of Ethernet data bag linear speed is realized in the present invention,
The data storage forwarding between ethernet port is not influenced while monitoring and analysis and is not take up Ethernet resource；The MAC
Interface between PHY can be MII bus, can also be RMII bus, RGMII bus, SGMII bus, QSGMII bus
Deng, but it is not limited to above several buses；FPGA stores collected ethernet signal by storage unit, and storage unit can be with
For memory ram item, Flash, standard machinery hard disk or solid state hard disk can also be.
Technical term explanation in the present invention:
MAC:Media Access Control, that is, media access control；
PHY:Port Physical Layer, that is, port physical layer；
MII:Media Independent Interface, that is, Media Independent Interface；
FPGA:Field Programmable Gate Array, that is, field programmable gate array；
GMII (Gigabit MII): GMII is 8bit parallel synchronous transceiver interface, using 8 interface data, work clock
125MHz, therefore transmission rate is up to 1000Mbps.The 10/100Mbps working method of compatible MII defined simultaneously；
The gmii interface that RGMII simplifies is known as RGMII, GMII and RGMII and is all made of 8 bit data interfaces, work clock
125MHz, therefore transmission rate is up to 1000Mbps；
RMII:Reduced Media Independant Interface simplify the media independent interface, is the ether of standard
One of network interface has less I/O to transmit than MII；
SGMII--Serial Gigabit Media Independent Interface, SGMII are between PHY and MAC
Interface, similar with GMII and RGMII, only GMII and RGMII is parallel, and is needed with Lu Shizhong, PCB layout
It is relatively cumbersome, and be not suitable with backboard application, and SGMII be it is serial, do not need to provide other clock, MAC and PHY are needed
CDR is wanted to go recovered clock.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to restrict the invention, all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (3)
1. a kind of method for realizing ethernet signal linear speed acquisition monitoring and analysis characterized by comprising
Directly mount field programmable gate array in MII bus between MAC and PHY, field programmable gate array have with
MAC function MII interface, ethernet PHY functional interface and serial port function interface are netted very much, field programmable gate array has ether
Net port, Consol mouthfuls and storage unit；
Field programmable gate array is read out, monitors and analyzes to the data packet transmitted in MII bus, realizes ethernet signal
Linear speed acquisition, monitoring and analysis, pass through the storage unit and store the data packet, monitoring and analysis result；
Field programmable gate array externally provides the data packet, monitoring and analysis knot by its ethernet port and Consol mouthfuls
Fruit.
2. a kind of method for realizing ethernet signal linear speed acquisition monitoring and analysis according to claim 1, feature exist
In: the MII bus can be RMII bus, RGMII bus, SGMII bus or QSGMII bus.
3. a kind of method for realizing ethernet signal linear speed acquisition monitoring and analysis according to claim 1, feature exist
In: the storage unit is memory ram item, Flash, standard machinery hard disk or solid state hard disk.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910782903.2A CN110505121A (en) | 2019-08-22 | 2019-08-22 | A method of realizing ethernet signal linear speed acquisition monitoring and analysis |
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| CN201910782903.2A CN110505121A (en) | 2019-08-22 | 2019-08-22 | A method of realizing ethernet signal linear speed acquisition monitoring and analysis |
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Citations (5)
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| CN204089874U (en) * | 2014-09-12 | 2015-01-07 | 国家电网公司 | A kind of switch supporting packet storage |
| CN104702354A (en) * | 2015-03-16 | 2015-06-10 | 毕节供电局 | FPGA-based (field programmable gate array-based) PTN (packet transport network) equipment time delay monitoring device and method |
| CN205647557U (en) * | 2016-05-19 | 2016-10-12 | 龙芯中科技术有限公司 | Ethernet interface circuit and network equipment |
| CN206442403U (en) * | 2016-12-21 | 2017-08-25 | 淮北师范大学 | A kind of vehicle communication experiment porch |
-
2019
- 2019-08-22 CN CN201910782903.2A patent/CN110505121A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103210609A (en) * | 2010-11-16 | 2013-07-17 | Abb研究有限公司 | Electronic device for communication in a data network including a protective circuit for identifying unwanted data |
| CN204089874U (en) * | 2014-09-12 | 2015-01-07 | 国家电网公司 | A kind of switch supporting packet storage |
| CN104702354A (en) * | 2015-03-16 | 2015-06-10 | 毕节供电局 | FPGA-based (field programmable gate array-based) PTN (packet transport network) equipment time delay monitoring device and method |
| CN205647557U (en) * | 2016-05-19 | 2016-10-12 | 龙芯中科技术有限公司 | Ethernet interface circuit and network equipment |
| CN206442403U (en) * | 2016-12-21 | 2017-08-25 | 淮北师范大学 | A kind of vehicle communication experiment porch |
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Application publication date: 20191126 |
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